Lines Matching +full:reg +full:- +full:property

11 - compatible: should be one of the following
12   - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13   Must provide a second register area and marvell,pad-type.
14   - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15   - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
16   - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
18 - clocks:
23 - clock-names:
24   Array of names corresponding to clocks property.
28 - reg:
29   * For "marvell,armada-3700-sdhci", two register areas.
32     Please follow the examples with compatible "marvell,armada-3700-sdhci"
34     Please also check property marvell,pad-type in below.
39 - marvell,xenon-sdhc-id:
43   If Xenon IP contains only one SDHC, this property is optional.
45 - marvell,xenon-phy-type:
48   marvell,xenon-phy-type = "emmc 5.1 phy"
49   eMMC 5.1 PHY is the default choice if this property is not provided.
51   marvell,xenon-phy-type = "emmc 5.0 phy"
54   Please note that this property only presents the type of PHY.
55   It doesn't stand for the entire SDHC type or property.
59 - marvell,xenon-phy-znr:
63   ZNR is set as 0xF by default if this property is not provided.
65 - marvell,xenon-phy-zpr:
69   ZPR is set as 0xF by default if this property is not provided.
71 - marvell,xenon-phy-nr-success-tun:
75   Set as 0x4 by default if this property is not provided.
77 - marvell,xenon-phy-tun-step-divider:
79   Set as 64 by default if this property is not provided.
81 - marvell,xenon-phy-slow-mode:
82   If this property is selected, transfers will bypass PHY.
84   Disabled by default. Please only try this property if timing issues
88 - marvell,xenon-tun-count:
89   Xenon SDHC SoC usually doesn't provide re-tuning counter in
91   This property provides the re-tuning counter.
92   If this property is not set, default re-tuning counter will
95 - marvell,pad-type:
97   Only valid when "marvell,armada-3700-sdhci" is selected.
98   Two types: "sd" and "fixed-1-8v".
101   If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC.
102   Please follow the examples with compatible "marvell,armada-3700-sdhci"
106 - For eMMC:
109 		compatible = "marvell,armada-ap806-sdhci";
110 		reg = <0xaa0000 0x1000>;
113 		clock-names = "core", "axi";
114 		bus-width = <4>;
115 		marvell,xenon-phy-slow-mode;
116 		marvell,xenon-tun-count = <11>;
117 		non-removable;
118 		no-sd;
119 		no-sdio;
124 - For SD/SDIO:
127 		compatible = "marvell,armada-cp110-sdhci";
128 		reg = <0xab0000 0x1000>;
130 		vqmmc-supply = <&sd_vqmmc_regulator>;
131 		vmmc-supply = <&sd_vmmc_regulator>;
133 		clock-names = "core", "axi";
134 		bus-width = <4>;
135 		marvell,xenon-tun-count = <9>;
138 - For eMMC with compatible "marvell,armada-3700-sdhci":
141 		compatible = "marvell,armada-3700-sdhci";
142 		reg = <0xaa0000 0x1000>,
146 		clock-names = "core";
147 		bus-width = <8>;
148 		mmc-ddr-1_8v;
149 		mmc-hs400-1_8v;
150 		non-removable;
151 		no-sd;
152 		no-sdio;
156 		marvell,pad-type = "fixed-1-8v";
159 - For SD/SDIO with compatible "marvell,armada-3700-sdhci":
162 		compatible = "marvell,armada-3700-sdhci";
163 		reg = <0xab0000 0x1000>,
166 		vqmmc-supply = <&sd_regulator>;
169 		clock-names = "core";
170 		bus-width = <4>;
172 		marvell,pad-type = "sd";