Lines Matching +full:reg +full:- +full:property
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
42 reg:
49 this property is required and must be set to 0.
51 On ARM 11 MPcore based systems this property is
54 Bits [11:0] in the reg cell must be set to
57 All other bits in the reg cell must be set to 0.
59 On 32-bit ARM v7 or later systems this property is
63 Bits [23:0] in the reg cell must be set to
66 All other bits in the reg cell must be set to 0.
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
73 The first reg cell bits [7:0] must be set to
76 The second reg cell bits [23:0] must be set to
79 * If cpus node's #address-cells property is set to 1
81 The reg cell bits [23:0] must be set to bits [23:0]
84 All other bits in the reg cells must be set to 0.
88 - apple,avalanche
89 - apple,blizzard
90 - apple,icestorm
91 - apple,firestorm
92 - arm,arm710t
93 - arm,arm720t
94 - arm,arm740t
95 - arm,arm7ej-s
96 - arm,arm7tdmi
97 - arm,arm7tdmi-s
98 - arm,arm9es
99 - arm,arm9ej-s
100 - arm,arm920t
101 - arm,arm922t
102 - arm,arm925
103 - arm,arm926e-s
104 - arm,arm926ej-s
105 - arm,arm940t
106 - arm,arm946e-s
107 - arm,arm966e-s
108 - arm,arm968e-s
109 - arm,arm9tdmi
110 - arm,arm1020e
111 - arm,arm1020t
112 - arm,arm1022e
113 - arm,arm1026ej-s
114 - arm,arm1136j-s
115 - arm,arm1136jf-s
116 - arm,arm1156t2-s
117 - arm,arm1156t2f-s
118 - arm,arm1176jzf
119 - arm,arm1176jz-s
120 - arm,arm1176jzf-s
121 - arm,arm11mpcore
122 - arm,armv8 # Only for s/w models
123 - arm,cortex-a5
124 - arm,cortex-a7
125 - arm,cortex-a8
126 - arm,cortex-a9
127 - arm,cortex-a12
128 - arm,cortex-a15
129 - arm,cortex-a17
130 - arm,cortex-a32
131 - arm,cortex-a34
132 - arm,cortex-a35
133 - arm,cortex-a53
134 - arm,cortex-a55
135 - arm,cortex-a57
136 - arm,cortex-a65
137 - arm,cortex-a72
138 - arm,cortex-a73
139 - arm,cortex-a75
140 - arm,cortex-a76
141 - arm,cortex-a77
142 - arm,cortex-a78
143 - arm,cortex-a78ae
144 - arm,cortex-a78c
145 - arm,cortex-a510
146 - arm,cortex-a520
147 - arm,cortex-a710
148 - arm,cortex-a715
149 - arm,cortex-a720
150 - arm,cortex-m0
151 - arm,cortex-m0+
152 - arm,cortex-m1
153 - arm,cortex-m3
154 - arm,cortex-m4
155 - arm,cortex-r4
156 - arm,cortex-r5
157 - arm,cortex-r7
158 - arm,cortex-r52
159 - arm,cortex-x1
160 - arm,cortex-x1c
161 - arm,cortex-x2
162 - arm,cortex-x3
163 - arm,cortex-x4
164 - arm,neoverse-e1
165 - arm,neoverse-n1
166 - arm,neoverse-n2
167 - arm,neoverse-v1
168 - brcm,brahma-b15
169 - brcm,brahma-b53
170 - brcm,vulcan
171 - cavium,thunder
172 - cavium,thunder2
173 - faraday,fa526
174 - intel,sa110
175 - intel,sa1100
176 - marvell,feroceon
177 - marvell,mohawk
178 - marvell,pj4a
179 - marvell,pj4b
180 - marvell,sheeva-v5
181 - marvell,sheeva-v7
182 - nvidia,tegra132-denver
183 - nvidia,tegra186-denver
184 - nvidia,tegra194-carmel
185 - qcom,krait
186 - qcom,kryo
187 - qcom,kryo240
188 - qcom,kryo250
189 - qcom,kryo260
190 - qcom,kryo280
191 - qcom,kryo360
192 - qcom,kryo385
193 - qcom,kryo465
194 - qcom,kryo468
195 - qcom,kryo485
196 - qcom,kryo560
197 - qcom,kryo570
198 - qcom,kryo660
199 - qcom,kryo685
200 - qcom,kryo780
201 - qcom,oryon
202 - qcom,scorpion
204 enable-method:
207 # On ARM v8 64-bit this property is required
208 - enum:
209 - psci
210 - spin-table
211 # On ARM 32-bit systems this property is optional
212 - enum:
213 - actions,s500-smp
214 - allwinner,sun6i-a31
215 - allwinner,sun8i-a23
216 - allwinner,sun9i-a80-smp
217 - allwinner,sun8i-a83t-smp
218 - amlogic,meson8-smp
219 - amlogic,meson8b-smp
220 - arm,realview-smp
221 - aspeed,ast2600-smp
222 - brcm,bcm11351-cpu-method
223 - brcm,bcm23550
224 - brcm,bcm2836-smp
225 - brcm,bcm63138
226 - brcm,bcm-nsp-smp
227 - brcm,brahma-b15
228 - marvell,armada-375-smp
229 - marvell,armada-380-smp
230 - marvell,armada-390-smp
231 - marvell,armada-xp-smp
232 - marvell,98dx3236-smp
233 - marvell,mmp3-smp
234 - mediatek,mt6589-smp
235 - mediatek,mt81xx-tz-smp
236 - qcom,gcc-msm8660
237 - qcom,kpss-acc-v1
238 - qcom,kpss-acc-v2
239 - qcom,msm8226-smp
240 - qcom,msm8909-smp
241 # Only valid on ARM 32-bit, see above for ARM v8 64-bit
242 - qcom,msm8916-smp
243 - renesas,apmu
244 - renesas,r9a06g032-smp
245 - rockchip,rk3036-smp
246 - rockchip,rk3066-smp
247 - socionext,milbeaut-m10v-smp
248 - ste,dbx500-smp
249 - ti,am3352
250 - ti,am4372
252 cpu-release-addr:
254 - $ref: /schemas/types.yaml#/definitions/uint32
255 - $ref: /schemas/types.yaml#/definitions/uint64
257 The DT specification defines this as 64-bit always, but some 32-bit Arm
258 systems have used a 32-bit value which must be supported.
259 Required for systems that have an "enable-method"
260 property value of "spin-table".
262 cpu-idle-states:
263 $ref: /schemas/types.yaml#/definitions/phandle-array
268 by this cpu (see ./idle-states.yaml).
270 capacity-dmips-mhz:
272 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
273 DMIPS/MHz, relative to highest capacity-dmips-mhz
276 cci-control-port: true
278 dynamic-power-coefficient:
289 calculate the dynamic power as below -
291 Pdyn = dynamic-power-coefficient * V^2 * f
295 performance-domains:
300 dvfs/performance-domain.yaml.
302 power-domains:
307 power-domain-names:
310 power-domains property.
322 Required for systems that have an "enable-method" property
323 value of "qcom,kpss-acc-v1" or "qcom,kpss-acc-v2"
332 Required for systems that have an "enable-method" property
333 value of "qcom,kpss-acc-v1", "qcom,kpss-acc-v2", "qcom,msm8226-smp" or
334 "qcom,msm8916-smp".
336 * arm/msm/qcom,kpss-acc.txt
343 Optional for systems that have an "enable-method"
344 property value of "rockchip,rk3066-smp"
346 the cpu-core power-domains.
348 secondary-boot-reg:
351 Required for systems that have an "enable-method" property value of
352 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
358 The secondary-boot-reg property is a u32 value that specifies the
365 # If the enable-method property contains one of those values
367 enable-method:
370 - brcm,bcm11351-cpu-method
371 - brcm,bcm23550
372 - brcm,bcm-nsp-smp
373 # and if enable-method is present
375 - enable-method
379 - secondary-boot-reg
382 - device_type
383 - reg
384 - compatible
387 rockchip,pmu: [enable-method]
392 - |
394 #size-cells = <0>;
395 #address-cells = <1>;
399 compatible = "arm,cortex-a15";
400 reg = <0x0>;
405 compatible = "arm,cortex-a15";
406 reg = <0x1>;
411 compatible = "arm,cortex-a7";
412 reg = <0x100>;
417 compatible = "arm,cortex-a7";
418 reg = <0x101>;
422 - |
423 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
425 #size-cells = <0>;
426 #address-cells = <1>;
430 compatible = "arm,cortex-a8";
431 reg = <0x0>;
435 - |
436 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
438 #size-cells = <0>;
439 #address-cells = <1>;
443 compatible = "arm,arm926ej-s";
444 reg = <0x0>;
448 - |
449 // Example 4 (ARM Cortex-A57 64-bit system):
451 #size-cells = <0>;
452 #address-cells = <2>;
456 compatible = "arm,cortex-a57";
457 reg = <0x0 0x0>;
458 enable-method = "spin-table";
459 cpu-release-addr = <0 0x20000000>;
464 compatible = "arm,cortex-a57";
465 reg = <0x0 0x1>;
466 enable-method = "spin-table";
467 cpu-release-addr = <0 0x20000000>;
472 compatible = "arm,cortex-a57";
473 reg = <0x0 0x100>;
474 enable-method = "spin-table";
475 cpu-release-addr = <0 0x20000000>;
480 compatible = "arm,cortex-a57";
481 reg = <0x0 0x101>;
482 enable-method = "spin-table";
483 cpu-release-addr = <0 0x20000000>;
488 compatible = "arm,cortex-a57";
489 reg = <0x0 0x10000>;
490 enable-method = "spin-table";
491 cpu-release-addr = <0 0x20000000>;
496 compatible = "arm,cortex-a57";
497 reg = <0x0 0x10001>;
498 enable-method = "spin-table";
499 cpu-release-addr = <0 0x20000000>;
504 compatible = "arm,cortex-a57";
505 reg = <0x0 0x10100>;
506 enable-method = "spin-table";
507 cpu-release-addr = <0 0x20000000>;
512 compatible = "arm,cortex-a57";
513 reg = <0x0 0x10101>;
514 enable-method = "spin-table";
515 cpu-release-addr = <0 0x20000000>;
520 compatible = "arm,cortex-a57";
521 reg = <0x1 0x0>;
522 enable-method = "spin-table";
523 cpu-release-addr = <0 0x20000000>;
528 compatible = "arm,cortex-a57";
529 reg = <0x1 0x1>;
530 enable-method = "spin-table";
531 cpu-release-addr = <0 0x20000000>;
536 compatible = "arm,cortex-a57";
537 reg = <0x1 0x100>;
538 enable-method = "spin-table";
539 cpu-release-addr = <0 0x20000000>;
544 compatible = "arm,cortex-a57";
545 reg = <0x1 0x101>;
546 enable-method = "spin-table";
547 cpu-release-addr = <0 0x20000000>;
552 compatible = "arm,cortex-a57";
553 reg = <0x1 0x10000>;
554 enable-method = "spin-table";
555 cpu-release-addr = <0 0x20000000>;
560 compatible = "arm,cortex-a57";
561 reg = <0x1 0x10001>;
562 enable-method = "spin-table";
563 cpu-release-addr = <0 0x20000000>;
568 compatible = "arm,cortex-a57";
569 reg = <0x1 0x10100>;
570 enable-method = "spin-table";
571 cpu-release-addr = <0 0x20000000>;
576 compatible = "arm,cortex-a57";
577 reg = <0x1 0x10101>;
578 enable-method = "spin-table";
579 cpu-release-addr = <0 0x20000000>;