Home
last modified time | relevance | path

Searched +full:post +full:- +full:clocks (Results 1 – 25 of 212) sorted by relevance

123456789

/linux/Documentation/devicetree/bindings/clock/
H A Dkeystone-pll.txt2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - #clock-cells : from common clock binding; shall be set to 0.
13 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
14 - clocks : parent clock phandle
15 - reg - pll control0 and pll multiplier registers
16 - reg-names : control, multiplier and post-divider. The multiplier and
17 post-divider registers are applicable only for main pll clock
18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
23 #clock-cells = <0>;
[all …]
H A Dst,stm32-rcc.txt6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
21 between gated clocks and other clocks and an index specifying the clock to
[all …]
/linux/drivers/clk/ingenic/
H A Dcgu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 * Copyright (c) 2013-2015 Imagination Technologies
13 #include <linux/clk-provider.h>
18 * struct ingenic_cgu_pll_info - information about a PLL
33 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.
34 * the index of the lowest bit of the post-VCO divider value in
36 * @od_bits: the size of the post-VCO divider field in bits, or 0 if no
38 * @od_max: the maximum post-VCO divider value
39 * @od_encoding: a pointer to an array mapping post-VCO divider values to
40 * their encoded values in the PLL control register, or -1 for
[all …]
/linux/Documentation/devicetree/bindings/ata/
H A Dsata_highbank.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
41 calxeda,led-order:
43 $ref: /schemas/types.yaml#/definitions/uint32-array
[all …]
/linux/Documentation/gpu/
H A Dmeson.rst5 .. kernel-doc:: drivers/gpu/drm/meson/meson_drv.c
16 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
18 D |-------| |----| | | | | HDMI PLL |
19 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
20 R |-------| |----| Processing | | | | |
21 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
22 R |-------| CSC |----| Scalers | | Encp ----------|----|----HDMI-TX----|
23 A | osd1 | | | Blenders | | Encl ----------|----|---------------|
24 M |-------|______|----|____________| |________________| | |
30 .. kernel-doc:: drivers/gpu/drm/meson/meson_viu.c
[all …]
/linux/drivers/media/platform/verisilicon/
H A Dhantro.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-core.h>
26 #include <media/videobuf2-dma-contig.h>
45 * struct hantro_irq - irq handler and name
56 * struct hantro_variant - information about VPU hardware variant
[all …]
/linux/Documentation/devicetree/bindings/display/hisilicon/
H A Dhisi-ade.txt1 Device-Tree bindings for hisilicon ADE display controller driver
4 data from memory, do composition, do post image processing, generate RGB
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
[all …]
/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2e-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
8 clocks {
10 #clock-cells = <0>;
11 compatible = "ti,keystone,main-pll-clock";
12 clocks = <&refclksys>;
14 reg-names = "control", "multiplier", "post-divider";
18 #clock-cells = <0>;
19 compatible = "ti,keystone,pll-clock";
20 clocks = <&refclkpass>;
[all …]
/linux/Documentation/devicetree/bindings/mailbox/
H A Dst,stm32-ipcc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 The IPCC block provides a non blocking signaling mechanism to post and
16 - Fabien Dessenne <fabien.dessenne@foss.st.com>
17 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
21 const: st,stm32mp1-ipcc
26 clocks:
31 - description: rx channel occupied
[all …]
/linux/Documentation/devicetree/bindings/dsp/
H A Dmediatek,mt8186-dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8186-dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
14 advanced pre- and post- audio processing.
19 - mediatek,mt8186-dsp
20 - mediatek,mt8188-dsp
24 - description: Address and size of the DSP config registers
25 - description: Address and size of the DSP SRAM
[all …]
H A Dmediatek,mt8195-dsp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dsp/mediatek,mt8195-dsp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - YC Hung <yc.hung@mediatek.com>
14 advanced pre- and post- audio processing.
18 const: mediatek,mt8195-dsp
22 - description: Address and size of the DSP Cfg registers
23 - description: Address and size of the DSP SRAM
25 reg-names:
[all …]
/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
[all …]
/linux/drivers/clk/samsung/
H A Dclk-cpu.c1 // SPDX-License-Identifier: GPL-2.0-only
13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
14 * clock for CPU domain. The rates of these auxiliary clocks are related to the
19 * clock and the corresponding rate changes of the auxiliary clocks of the CPU
23 * clocks.
27 * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
37 #include <linux/clk-provider.h>
40 #include "clk-cpu.h"
48 * struct exynos_cpuclk_regs - Register offsets for CPU related clocks
71 * struct exynos_cpuclk_chip - Chip specific data for CPU clock
[all …]
/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-pwrseq-simple.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
19 const: mmc-pwrseq-simple
21 reset-gpios:
28 They will be de-asserted right after the power has been provided to the
31 clocks:
33 description: Handle for the entry in clock-names.
[all …]
/linux/Documentation/devicetree/bindings/net/
H A Dhisilicon-femac.txt4 - compatible: should contain one of the following version strings:
5 * "hisilicon,hisi-femac-v1"
6 * "hisilicon,hisi-femac-v2"
7 and the soc string "hisilicon,hi3516cv300-femac".
8 - reg: specifies base physical address(s) and size of the device registers.
11 - interrupts: should contain the MAC interrupt.
12 - clocks: A phandle to the MAC main clock.
13 - resets: should contain the phandle to the MAC reset signal(required) and
15 - reset-names: should contain the reset signal name "mac"(required)
17 - phy-mode: see ethernet.txt [1].
[all …]
H A Drenesas,ethertsn.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Ethernet TSN End-station
10 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
17 - $ref: ethernet-controller.yaml#
22 - enum:
23 - renesas,r8a779g0-ethertsn # R-Car V4H
24 - const: renesas,rcar-gen4-ethertsn
[all …]
H A Dhisilicon-hix5hd2-gmac.txt4 - compatible: should contain one of the following SoC strings:
5 * "hisilicon,hix5hd2-gmac"
6 * "hisilicon,hi3798cv200-gmac"
7 * "hisilicon,hi3516a-gmac"
9 * "hisilicon,hisi-gmac-v1"
10 * "hisilicon,hisi-gmac-v2"
13 - reg: specifies base physical address(s) and size of the device registers.
16 - interrupts: should contain the MAC interrupt.
17 - #address-cells: must be <1>.
18 - #size-cells: must be <0>.
[all …]
/linux/Documentation/devicetree/bindings/media/
H A Dnvidia,tegra-vde.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/nvidia,tegra-vde.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
17 - items:
18 - enum:
19 - nvidia,tegra132-vde
[all …]
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-h6-orangepi-lite2.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 #include "sun50i-h6-orangepi.dtsi"
8 compatible = "xunlong,orangepi-lite2", "allwinner,sun50i-h6";
11 serial1 = &uart1; /* BT-UART */
15 compatible = "mmc-pwrseq-simple";
16 clocks = <&rtc CLK_OSC32K_FANOUT>;
17 clock-names = "ext_clock";
18 reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
19 post-power-on-delay-ms = <200>;
24 vmmc-supply = <&reg_cldo2>;
[all …]
/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra210-ahub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/sound/nvidia,tegra210-ahub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 for audio pre-processing, post-processing and a programmable full
17 - Jon Hunter <jonathanh@nvidia.com>
18 - Sameer Pujar <spujar@nvidia.com>
22 pattern: "^ahub@[0-9a-f]*$"
26 - enum:
27 - nvidia,tegra210-ahub
[all …]
/linux/Documentation/devicetree/bindings/phy/
H A Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
7 - compatible : Shall be "apm,xgene-phy".
8 - reg : PHY memory resource is the SDS PHY access resource.
9 - #phy-cells : Shall be 1 as it expects one argument for setting
14 - status : Shall be "ok" if enabled or "disabled" if disabled.
16 - clocks : Reference to the clock entry.
17 - apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
19 Two set of 3-tuple setting for each (up to 3)
22 - apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
[all …]
/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
62 * turn ON only the valid clocks.
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
[all …]
/linux/arch/arm/boot/dts/nxp/imx/
H A Dmba6ulx.dtsi1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2018-2022 TQ-Systems GmbH
4 * Author: Markus Niebel <Markus.Niebel@tq-group.com>
8 model = "TQ-Systems MBA6ULx Baseboard";
18 stdout-path = &uart1;
22 compatible = "pwm-backlight";
23 power-supply = <&reg_mba6ul_3v3>;
24 enable-gpios = <&expander_out0 4 GPIO_ACTIVE_HIGH>;
29 compatible = "gpio-beeper";
33 gpio_buttons: gpio-keys {
[all …]
/linux/drivers/clk/keystone/
H A Dpll.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Murali Karicheri <m-karicheri2@ti.com>
9 #include <linux/clk-provider.h>
26 * struct clk_pll_data - pll data structure
28 * register of pll controller, else it is in the pll_ctrl0((bit 11-6)
36 * @pllod: PLL register map address for post divider bits
45 * @postdiv: Fixed post divider
64 * struct clk_pll - Main pll clock
79 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc()
84 * get bits 0-5 of multiplier from pllctrl PLLM register in clk_pllclk_recalc()
[all …]
/linux/arch/arm/boot/dts/allwinner/
H A Dsunxi-h3-h5-emlid-neutis.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
8 #include "sunxi-common-regulators.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
18 stdout-path = "serial0:115200n8";
22 compatible = "mmc-pwrseq-simple";
23 reset-gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
24 post-power-on-delay-ms = <200>;
25 clocks = <&rtc CLK_OSC32K_FANOUT>;
26 clock-names = "ext_clock";
31 cpu-supply = <&vdd_cpux>;
[all …]

123456789