Lines Matching +full:post +full:- +full:clocks
1 // SPDX-License-Identifier: GPL-2.0-only
13 * auxiliary clocks supplied to the CPU domain such as the debug blocks and AXI
14 * clock for CPU domain. The rates of these auxiliary clocks are related to the
19 * clock and the corresponding rate changes of the auxiliary clocks of the CPU
23 * clocks.
27 * CPU domain PLL is reconfigured, the CPU domain clocks are driven using an
37 #include <linux/clk-provider.h>
40 #include "clk-cpu.h"
48 * struct exynos_cpuclk_regs - Register offsets for CPU related clocks
71 * struct exynos_cpuclk_chip - Chip specific data for CPU clock
72 * @regs: register offsets for CPU related clocks
83 * struct exynos_cpuclk - information about clock supplied to a CPU core
94 * @chip: chip-specific data for the CPU clock
111 /* ---- Common code --------------------------------------------------------- */
156 pr_err("%s: re-parenting mux timed-out\n", __func__);
167 const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
168 void __iomem *base = cpuclk->base;
171 div0 = readl(base + regs->div_cpu0);
173 writel(div0, base + regs->div_cpu0);
174 wait_until_divider_stable(base + regs->div_stat_cpu0, mask);
177 /* ---- Exynos 3/4/5 -------------------------------------------------------- */
195 /* handler for pre-rate change notification from parent clock */
199 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
200 const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
201 void __iomem *base = cpuclk->base;
202 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
207 while ((cfg_data->prate * 1000) != ndata->new_rate) {
208 if (cfg_data->prate == 0)
209 return -EINVAL;
213 spin_lock_irqsave(cpuclk->lock, flags);
216 * For the selected PLL clock frequency, get the pre-defined divider
220 div0 = cfg_data->div0;
221 if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
222 div1 = cfg_data->div1;
223 if (readl(base + regs->mux_sel) & E4210_MUX_HPM_MASK)
224 div1 = readl(base + regs->div_cpu1) &
234 * (this can result in too high speed of armclk output clocks).
236 if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
237 unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
240 alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
243 if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
256 mux_reg = readl(base + regs->mux_sel);
257 writel(mux_reg | (1 << 16), base + regs->mux_sel);
258 wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 2);
261 writel(div0, base + regs->div_cpu0);
262 wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL);
264 if (cpuclk->flags & CLK_CPU_HAS_DIV1) {
265 writel(div1, base + regs->div_cpu1);
266 wait_until_divider_stable(base + regs->div_stat_cpu1,
270 spin_unlock_irqrestore(cpuclk->lock, flags);
274 /* handler for post-rate change notification from parent clock */
278 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
279 const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
280 void __iomem *base = cpuclk->base;
286 if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
287 while ((cfg_data->prate * 1000) != ndata->new_rate) {
288 if (cfg_data->prate == 0)
289 return -EINVAL;
294 spin_lock_irqsave(cpuclk->lock, flags);
297 mux_reg = readl(base + regs->mux_sel);
298 writel(mux_reg & ~(1 << 16), base + regs->mux_sel);
299 wait_until_mux_stable(base + regs->mux_stat, 16, MUX_MASK, 1);
301 if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) {
302 div |= (cfg_data->div0 & E4210_DIV0_ATB_MASK);
307 spin_unlock_irqrestore(cpuclk->lock, flags);
311 /* ---- Exynos5433 ---------------------------------------------------------- */
322 /* handler for pre-rate change notification from parent clock */
326 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
327 const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
328 void __iomem *base = cpuclk->base;
329 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent);
334 while ((cfg_data->prate * 1000) != ndata->new_rate) {
335 if (cfg_data->prate == 0)
336 return -EINVAL;
340 spin_lock_irqsave(cpuclk->lock, flags);
343 * For the selected PLL clock frequency, get the pre-defined divider
346 div0 = cfg_data->div0;
347 div1 = cfg_data->div1;
355 * (this can result in too high speed of armclk output clocks).
357 if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
358 unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
361 alt_div = DIV_ROUND_UP(alt_prate, tmp_rate) - 1;
369 mux_reg = readl(base + regs->mux_sel);
370 writel(mux_reg | 1, base + regs->mux_sel);
371 wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 2);
374 writel(div0, base + regs->div_cpu0);
375 wait_until_divider_stable(base + regs->div_stat_cpu0, DIV_MASK_ALL);
377 writel(div1, base + regs->div_cpu1);
378 wait_until_divider_stable(base + regs->div_stat_cpu1, DIV_MASK_ALL);
380 spin_unlock_irqrestore(cpuclk->lock, flags);
384 /* handler for post-rate change notification from parent clock */
388 const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
389 void __iomem *base = cpuclk->base;
394 spin_lock_irqsave(cpuclk->lock, flags);
397 mux_reg = readl(base + regs->mux_sel);
398 writel(mux_reg & ~1, base + regs->mux_sel);
399 wait_until_mux_stable(base + regs->mux_stat, 0, MUX_MASK, 1);
402 spin_unlock_irqrestore(cpuclk->lock, flags);
406 /* ---- Exynos850 ----------------------------------------------------------- */
448 return -ENOENT;
452 return -ENOENT;
456 return -EINVAL;
467 ret = clk_set_rate(alt_parent->clk, div_rate);
475 /* Handler for pre-rate change notification from parent clock */
480 const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
481 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg;
482 const struct clk_hw *alt_parent = cpuclk->alt_parent;
483 void __iomem *base = cpuclk->base;
491 if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK)
495 while ((cfg_data->prate * 1000) != ndata->new_rate) {
496 if (cfg_data->prate == 0)
497 return -EINVAL;
507 * (this can result in too high speed of armclk output clocks).
509 if (alt_prate > ndata->old_rate || ndata->old_rate > ndata->new_rate) {
510 unsigned long tmp_rate = min(ndata->old_rate, ndata->new_rate);
517 spin_lock_irqsave(cpuclk->lock, flags);
520 mux_reg = readl(base + regs->mux);
521 writel(mux_reg | 1, base + regs->mux);
522 wait_until_mux_stable(base + regs->mux, 16, 1, 0);
526 unsigned long div = (cfg_data->div0 >> shifts[i]) & 0xf;
529 val = readl(base + regs->divs[i]);
531 writel(val, base + regs->divs[i]);
532 wait_until_divider_stable(base + regs->divs[i], E850_BUSY_MASK);
535 spin_unlock_irqrestore(cpuclk->lock, flags);
540 /* Handler for post-rate change notification from parent clock */
544 const struct exynos_cpuclk_regs * const regs = cpuclk->chip->regs;
545 const struct clk_hw *alt_parent = cpuclk->alt_parent;
546 void __iomem *base = cpuclk->base;
551 if (ndata->new_rate == E850_OSCCLK || ndata->old_rate == E850_OSCCLK)
554 spin_lock_irqsave(cpuclk->lock, flags);
557 mux_reg = readl(base + regs->mux);
558 writel(mux_reg & ~1, base + regs->mux);
559 wait_until_mux_stable(base + regs->mux, 16, 1, 0);
561 spin_unlock_irqrestore(cpuclk->lock, flags);
567 /* -------------------------------------------------------------------------- */
569 /* Common round rate callback usable for all types of CPU clocks */
578 /* Common recalc rate callback usable for all types of CPU clocks */
598 * This notifier function is called for the pre-rate and post-rate change
611 err = cpuclk->chip->pre_rate_cb(ndata, cpuclk);
613 err = cpuclk->chip->post_rate_cb(ndata, cpuclk);
653 hws = ctx->clk_data.hws;
654 parent = hws[clk_data->parent_id];
655 alt_parent = hws[clk_data->alt_parent_id];
658 return -EINVAL;
663 return -ENOMEM;
667 init.name = clk_data->name;
673 cpuclk->alt_parent = alt_parent;
674 cpuclk->hw.init = &init;
675 cpuclk->base = ctx->reg_base + clk_data->offset;
676 cpuclk->lock = &ctx->lock;
677 cpuclk->flags = clk_data->flags;
678 cpuclk->clk_nb.notifier_call = exynos_cpuclk_notifier_cb;
679 cpuclk->chip = &exynos_clkcpu_chips[clk_data->reg_layout];
681 ret = clk_notifier_register(parent->clk, &cpuclk->clk_nb);
684 __func__, clk_data->name);
689 for (num_cfgs = 0; clk_data->cfg[num_cfgs].prate != 0; )
692 cpuclk->cfg = kmemdup_array(clk_data->cfg, num_cfgs, sizeof(*cpuclk->cfg),
694 if (!cpuclk->cfg) {
695 ret = -ENOMEM;
699 ret = clk_hw_register(NULL, &cpuclk->hw);
702 clk_data->name);
706 samsung_clk_add_lookup(ctx, &cpuclk->hw, clk_data->id);
710 kfree(cpuclk->cfg);
712 clk_notifier_unregister(parent->clk, &cpuclk->clk_nb);