Lines Matching +full:post +full:- +full:clocks
1 Device-Tree bindings for hisilicon ADE display controller driver
4 data from memory, do composition, do post image processing, generate RGB
8 - compatible: value should be "hisilicon,hi6220-ade".
9 - reg: physical base address and length of the ADE controller's registers.
10 - hisilicon,noc-syscon: ADE NOC QoS syscon.
11 - resets: The ADE reset controller node.
12 - interrupt: the ldi vblank interrupt number used.
13 - clocks: a list of phandle + clock-specifier pairs, one for each entry
14 in clock-names.
15 - clock-names: should contain:
20 - assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
21 phandle + clock-specifier pairs.
22 - assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
27 - port: the output port. This contains one endpoint subnode, with its
28 remote-endpoint set to the phandle of the connected DSI input endpoint.
32 - dma-coherent: Present if dma operations are coherent.
39 compatible = "hisilicon,hi6220-ade";
41 reg-names = "ade_base";
42 hisilicon,noc-syscon = <&medianoc_ade>;
46 clocks = <&media_ctrl HI6220_ADE_CORE>,
50 clock-names = "clk_ade_core",
54 assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
56 assigned-clock-rates = <360000000>, <288000000>;
57 dma-coherent;
61 remote-endpoint = <&dsi_in>;