Lines Matching +full:post +full:- +full:clocks
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
16 - reg: should be register base and length as documented in the
18 - #reset-cells: 1, see below
19 - #clock-cells: 2, device nodes should specify the clock in their "clocks"
21 between gated clocks and other clocks and an index specifying the clock to
23 - clocks: External oscillator clock phandle
24 - high speed external clock signal (HSE)
25 - external I2S clock (I2S_CKIN)
30 #reset-cells = <1>;
31 #clock-cells = <2>
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
34 clocks = <&clk_hse>, <&clk_i2s_ckin>;
37 Specifying gated clocks
50 human-readble format.
53 - include/dt-bindings/mfd/stm32f4-rcc.h
59 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
64 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
67 Specifying other clocks
76 2 CLK_LSI (low-power clock source)
77 3 CLK_LSE (generated from a 32.768 kHz low-speed external
80 5 CLK_RTC (real-time clock)
83 8 CLK_LCD (LCD-TFT)
84 9 CLK_I2S (I2S clocks)
85 10 CLK_SAI1 (audio clocks)
87 12 CLK_I2SQ_PDIV (post divisor of pll i2s q divisor)
88 13 CLK_SAIQ_PDIV (post divisor of pll sai q divisor)
92 16 CLK_HDMI_CEC (HDMI-CEC clock)
93 17 CLK_SPDIF (SPDIF-Rx clock)
94 18 CLK_USART1 (U(s)arts clocks)
102 26 CLK_I2C1 (I2S clocks)
117 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>