Lines Matching +full:post +full:- +full:clocks

1 // SPDX-License-Identifier: GPL-2.0
5  * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
8 clocks {
10 		#clock-cells = <0>;
11 		compatible = "ti,keystone,main-pll-clock";
12 		clocks = <&refclksys>;
14 		reg-names = "control", "multiplier", "post-divider";
18 		#clock-cells = <0>;
19 		compatible = "ti,keystone,pll-clock";
20 		clocks = <&refclkpass>;
21 		clock-output-names = "papllclk";
23 		reg-names = "control";
27 		#clock-cells = <0>;
28 		compatible = "ti,keystone,pll-clock";
29 		clocks = <&refclkddr3a>;
30 		clock-output-names = "ddr-3a-pll-clk";
32 		reg-names = "control";
36 		#clock-cells = <0>;
37 		compatible = "ti,keystone,psc-clock";
38 		clocks = <&chipclk16>;
39 		clock-output-names = "usb1";
41 		reg-names = "control", "domain";
42 		domain-id = <0>;
46 		#clock-cells = <0>;
47 		compatible = "ti,keystone,psc-clock";
48 		clocks = <&chipclk12>;
49 		clock-output-names = "hyperlink-0";
51 		reg-names = "control", "domain";
52 		domain-id = <5>;
56 		#clock-cells = <0>;
57 		compatible = "ti,keystone,psc-clock";
58 		clocks = <&chipclk12>;
59 		clock-output-names = "pcie1";
61 		reg-names = "control", "domain";
62 		domain-id = <18>;
66 		#clock-cells = <0>;
67 		compatible = "ti,keystone,psc-clock";
68 		clocks = <&chipclk13>;
69 		clock-output-names = "xge";
71 		reg-names = "control", "domain";
72 		domain-id = <29>;
76 	 * Below are set of fixed, input clocks definitions,
78 	 * Those clocks can be used as reference clocks for some HW modules
82 		#clock-cells = <0>;
83 		compatible = "fixed-clock";
84 		clock-frequency = <0>;
85 		clock-output-names = "tsipclka";
89 		#clock-cells = <0>;
90 		compatible = "fixed-clock";
91 		clock-frequency = <0>;
92 		clock-output-names = "tsipclkb";