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/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5351.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3
16 https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
19 - Alvin Šipraga <alsi@bang-olufsen.dk>
24 - silabs,si5351a # Si5351A, 20-QFN package
25 - silabs,si5351a-msop # Si5351A, 10-MSOP package
26 - silabs,si5351b # Si5351B, 20-QFN package
27 - silabs,si5351c # Si5351C, 20-QFN package
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H A Dqcom,ipq9574-nsscc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Anusha Rao <quic_anusha@quicinc.com>
18 include/dt-bindings/clock/qcom,ipq9574-nsscc.h
19 include/dt-bindings/reset/qcom,ipq9574-nsscc.h
23 const: qcom,ipq9574-nsscc
27 - description: Board XO source
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H A Dbrcm,iproc-clocks.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
25 - brcm,bcm63138-armpll
26 - brcm,cygnus-armpll
27 - brcm,cygnus-genpll
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H A Dcirrus,cs2000-cp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 The CS2000-CP is an extremely versatile system clocking device that
21 - cirrus,cs2000-cp
28 clock-names:
30 - const: clk_in
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/linux/include/linux/platform_data/
H A Dsi5351.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * enum si5351_pll_src - Si5351 pll clock source
12 * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
13 * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
22 * enum si5351_multisynth_src - Si5351 multisynth clock source
24 * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
25 * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
34 * enum si5351_clkout_src - Si5351 clock output clock source
36 * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
37 * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
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/linux/drivers/video/fbdev/via/
H A Dvia_clock.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved.
4 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved.
8 * clock and PLL management functions
12 #include <linux/via-core.h>
21 static inline u32 cle266_encode_pll(struct via_pll_config pll) in cle266_encode_pll() argument
23 return (pll.multiplier << 8) in cle266_encode_pll()
24 | (pll.rshift << 6) in cle266_encode_pll()
25 | pll.divisor; in cle266_encode_pll()
28 static inline u32 k800_encode_pll(struct via_pll_config pll) in k800_encode_pll() argument
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/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
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H A Dnvidia,tegra194-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra194-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra194-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
25 reg-names:
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H A Dnvidia,tegra186-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra186-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
18 const: nvidia,tegra186-xusb
22 - description: base and length of the xHCI host registers
23 - description: base and length of the XUSB FPCI registers
25 reg-names:
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/linux/sound/soc/codecs/
H A Dadav80x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Author: Lars-Peter Clausen <lars@metafoo.de>
46 #define ADAV80X_PLL_CLK_SRC_PLL_XIN(pll) 0x00 argument
47 #define ADAV80X_PLL_CLK_SRC_PLL_MCLKI(pll) (0x40 << (pll)) argument
48 #define ADAV80X_PLL_CLK_SRC_PLL_MASK(pll) (0x40 << (pll)) argument
56 #define ADAV80X_PLL_CTRL1_PLLPD(pll) (0x04 << (pll)) argument
59 #define ADAV80X_PLL_CTRL2_FIELD(pll, x) ((x) << ((pll) * 4)) argument
61 #define ADAV80X_PLL_CTRL2_FS_48(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x00) argument
62 #define ADAV80X_PLL_CTRL2_FS_32(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x08) argument
63 #define ADAV80X_PLL_CTRL2_FS_44(pll) ADAV80X_PLL_CTRL2_FIELD((pll), 0x0c) argument
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H A Dda7213.c1 // SPDX-License-Identifier: GPL-2.0-or-later
34 /* -54dB */
35 0x0, 0x11, TLV_DB_SCALE_ITEM(-5400, 0, 0),
36 /* -52.5dB to 15dB */
37 0x12, 0x3f, TLV_DB_SCALE_ITEM(-5250, 150, 0)
42 /* -78dB to 12dB */
43 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
52 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
53 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
54 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
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/linux/drivers/clk/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
43 source "drivers/clk/versatile/Kconfig"
46 bool "PLL Driver for HSDK platform"
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
87 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
91 tristate "Raspberry Pi RP1-based clock support"
96 This multi-function device has 3 main PLLs and several clock
97 generators to drive the internal sub-peripherals.
106 multi-function device has one fixed-rate oscillator, clocked
137 be pre-programmed to support other configurations and features not yet
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H A Dclk-k210.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #define pr_fmt(fmt) "k210-clk: " fmt
15 #include <linux/clk-provider.h>
18 #include <soc/canaan/k210-sysctl.h>
20 #include <dt-bindings/clock/k210-clk.h>
253 * PLL control register bits.
268 * PLL lock register bits.
322 * struct k210_sysclk - sysclk driver data
354 struct k210_pll *pll) in k210_init_pll() argument
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/linux/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
197 /* Input: Signal Type - to be converted to Encoder mode */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
218 enum controller_id controller_id; /* (Which CRTC uses this PLL) */
219 enum clock_source_id pll_id; /* Clock Source Id */
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
225 /* Calculated Reference divider of Display PLL */
227 /* Calculated Feedback divider of Display PLL */
229 /* Calculated Fractional Feedback divider of Display PLL */
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/linux/Documentation/userspace-api/media/mediactl/
H A Dmedia-types.rst1 .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later
3 .. _media-controller-types:
10 .. _media-entity-functions:
11 .. _MEDIA-ENT-F-UNKNOWN:
12 .. _MEDIA-ENT-F-V4L2-SUBDEV-UNKNOWN:
13 .. _MEDIA-ENT-F-IO-V4L:
14 .. _MEDIA-ENT-F-IO-VBI:
15 .. _MEDIA-ENT-F-IO-SWRADIO:
16 .. _MEDIA-ENT-F-IO-DTV:
17 .. _MEDIA-ENT-F-DTV-DEMOD:
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/linux/include/dt-bindings/clock/
H A Dtegra186-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
419 * appropriate clock source, program the source rate and execute a
420 * specific sequence to switch to the new clock source for both memory
751 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
809 …DQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
813 /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enab…
818 * @brief GPC2CLK-div-2
827 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
829 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
831 /** Fixed 408MHz PLL for use by peripheral clocks */
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H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
66 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
75 * appropriate clock source, program the source rate and execute a
76 * specific sequence to switch to the new clock source for both memory
196 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
198 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain …
200 /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
206 /** Fixed frequency 960MHz PLL for USB and EAVB */
382 /** @brief NAFLL clock source for BPMP */
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/linux/drivers/net/ethernet/intel/ice/
H A Dice_tspll.c1 // SPDX-License-Identifier: GPL-2.0
49 * ice_tspll_clk_freq_str - Convert time_ref_freq to string
75 * ice_tspll_default_freq - Return default frequency for a MAC type
78 * Return: default TSPLL frequency for a correct MAC type, -ERANGE otherwise.
88 return -ERANGE; in ice_tspll_default_freq()
93 * ice_tspll_check_params - Check if TSPLL params are correct
96 * @clk_src: Clock source to select (TIME_REF or TCXO)
111 dev_warn(ice_hw_to_dev(hw), "Invalid clock source %u\n", in ice_tspll_check_params()
116 if ((hw->mac_type == ICE_MAC_GENERIC_3K_E825 || in ice_tspll_check_params()
118 clk_freq != ice_tspll_default_freq(hw->mac_type)) { in ice_tspll_check_params()
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/linux/arch/arm/boot/dts/marvell/
H A Ddove-cubox.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
20 compatible = "gpio-leds";
21 pinctrl-0 = <&pmx_gpio_18>;
22 pinctrl-names = "default";
24 led-power {
27 default-state = "keep";
31 usb_power: regulator-1 {
32 compatible = "regulator-fixed";
33 regulator-name = "USB Power";
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/linux/drivers/clk/qcom/
H A Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
21 * clocks from CMN PLL on IPQ5424 are the same as IPQ9574.
23 * +---------+
25 * +--+---+--+
28 * +-------+---+------+
29 * | +-------------> eth0-50mhz
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/linux/drivers/clk/imx/
H A Dclk-pllv1.c1 // SPDX-License-Identifier: GPL-2.0
3 #include <linux/clk-provider.h>
12 #define MFN_SIGN (BIT(MFN_BITS - 1))
13 #define MFN_MASK (MFN_SIGN - 1)
16 * struct clk_pllv1 - IMX PLLv1 clock descriptor
18 * @hw: clock source
19 * @base: base address of pll registers
22 * PLL clock version 1, found on i.MX1/21/25/27/31/35
32 static inline bool is_imx1_pllv1(struct clk_pllv1 *pll) in is_imx1_pllv1() argument
34 return pll->type == IMX_PLLV1_IMX1; in is_imx1_pllv1()
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/linux/drivers/clk/mxs/
H A Dclk-imx23.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 #include <linux/clk-provider.h>
60 * Source ssp clock from ref_io than ref_xtal, in clk_misc_init()
66 * 480 MHz seems too high to be ssp clock source directly, in clk_misc_init()
73 static const char *const sel_pll[] __initconst = { "pll", "ref_xtal", };
81 ref_xtal, pll, ref_cpu, ref_emi, ref_pix, ref_io, saif_sel, enumerator
102 dcnp = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl"); in mx23_clocks_init()
113 clks[pll] = mxs_clk_pll("pll", "ref_xtal", PLLCTRL0, 16, 480000000); in mx23_clocks_init()
114 clks[ref_cpu] = mxs_clk_ref("ref_cpu", "pll", FRAC, 0); in mx23_clocks_init()
115 clks[ref_emi] = mxs_clk_ref("ref_emi", "pll", FRAC, 1); in mx23_clocks_init()
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/linux/arch/arm/mach-lpc32xx/
H A Dpm.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm/mach-lpc32xx/pm.c
5 * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
15 * direct-run, and halt modes. When switching between halt and run modes,
16 * the CPU transistions through direct-run mode. For Linux, direct-run
22 * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
25 * Direct-run mode:
28 * source or the frequency of the main oscillator. In this mode, the
36 * wake the system up back into direct-run mode.
41 * SDRAM will still be accessible in direct-run mode. In DDR based systems,
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/linux/include/video/
H A Dsstfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
105 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
106 # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
108 # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
109 # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
176 #define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */
178 #define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */
179 #define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */
183 #define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */
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/linux/drivers/clk/tegra/
H A Dclk.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
76 * @rate: input frequency from source
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
99 * @flags: hardware-specific flags
106 * TEGRA_DIVIDER_ROUND_UP - This flags indicates to round up the divider value.
107 * TEGRA_DIVIDER_FIXED - Fixed rate PLL dividers has addition override bit, this
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