Lines Matching +full:pll +full:- +full:source

1 // SPDX-License-Identifier: GPL-2.0-only
3  * arch/arm/mach-lpc32xx/pm.c
5  * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
15  * direct-run, and halt modes. When switching between halt and run modes,
16  * the CPU transistions through direct-run mode. For Linux, direct-run
22  * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
25  * Direct-run mode:
28  * source or the frequency of the main oscillator. In this mode, the
36  * wake the system up back into direct-run mode.
41  * SDRAM will still be accessible in direct-run mode. In DDR based systems,
42  * a transition to direct-run mode will stop all DDR accesses (no clocks).
44  * and exit DRAM self-refresh modes must not be executed in DRAM. A small
51  *  Places DRAMs in self-refresh mode
52  *  Enter direct-run mode
53  *  Save state of HCLK_PLL PLL
54  *  Disable HCLK_PLL PLL
55  *  Enter halt mode - CPU and buses will stop
56  *  System enters direct-run mode when an enabled event occurs
57  *  HCLK PLL state is restored
89 		return -ENOMEM;  in lpc32xx_pm_enter()
94 	 * when the PLL is stopped.  in lpc32xx_pm_enter()
126 	 * Setup SDRAM self-refresh clock to automatically disable o  in lpc32xx_pm_init()
127 	 * start of self-refresh. This only needs to be done once.  in lpc32xx_pm_init()