Lines Matching +full:pll +full:- +full:source
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
105 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
106 # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
108 # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
109 # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
176 #define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */
178 #define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */
179 #define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */
183 #define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */
192 # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */
193 # define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */
195 # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */
196 #define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */
231 #define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */
232 #define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */
237 #define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */
239 * pll parameter register:
242 * 8 freq registers (0-7) for video clock (CLK0)
243 * 2 freq registers (a-b) for graphic clock (CLK1)
245 #define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */
288 set the source signal driving the pin. conclusion : just use the default
346 struct pll_timing pll; member