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/linux/Documentation/devicetree/bindings/net/
H A Dadi,adin.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADIN1200/ADIN1300 PHY
10 - Marcelo Schmitt <marcelo.schmitt@analog.com>
16 - $ref: ethernet-phy.yaml#
19 adi,rx-internal-delay-ps:
21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
22 internal delay (phy-mode is 'rgmii-id' or 'rgmii-rxid') in pico-seconds.
26 adi,tx-internal-delay-ps:
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H A Dnxp,tja11xx.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP TJA11xx PHY
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
20 - ethernet-phy-id0180.dc40
21 - ethernet-phy-id0180.dc41
22 - ethernet-phy-id0180.dc48
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H A Drockchip-dwmac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/rockchip-dwmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - David Wu <david.wu@rock-chips.com>
18 - rockchip,px30-gmac
19 - rockchip,rk3128-gmac
20 - rockchip,rk3228-gmac
21 - rockchip,rk3288-gmac
22 - rockchip,rk3308-gmac
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H A Dti,cpsw-switch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/ti,cpsw-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Siddharth Vadapalli <s-vadapalli@ti.com>
11 - Roger Quadros <rogerq@kernel.org>
14 The 3-port switch gigabit ethernet subsystem provides ethernet packet
18 the management data input output (MDIO) for physical layer device (PHY)
24 - const: ti,cpsw-switch
25 - items:
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H A Dsnps,dwc-qos-ethernet.txt13 - compatible: One of:
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
15 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
22 - reg: Address and length of the register set for the device
23 - clocks: Phandle and clock specifiers for each entry in clock-names, in the
24 same order. See ../clock/clock-bindings.txt.
25 - clock-names: May contain any/all of the following depending on the IP
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/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
28 power-domains:
34 Three input clocks referring to left input reference clock, refclk and right input reference
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H A Dphy-cadence-torrent.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Torrent SD0801 PHY
10 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
12 PHY also supports multilink multiprotocol combinations including protocols
16 - Swapnil Jakhade <sjakhade@cadence.com>
17 - Yuti Amonkar <yamonkar@cadence.com>
22 - cdns,torrent-phy
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H A Dmediatek,hdmi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,hdmi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek High Definition Multimedia Interface (HDMI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
16 The HDMI PHY serializes the HDMI encoder's three channel 10-bit parallel
17 output and drives the HDMI pads.
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H A Dphy-rockchip-naneng-combphy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip SoC Naneng Combo Phy
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3528-naneng-combphy
16 - rockchip,rk3562-naneng-combphy
17 - rockchip,rk3568-naneng-combphy
18 - rockchip,rk3576-naneng-combphy
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H A Dmediatek,dsi-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek MIPI Display Serial Interface (DSI) PHY
11 - Chun-Kuang Hu <chunkuang.hu@kernel.org>
12 - Philipp Zabel <p.zabel@pengutronix.de>
13 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 description: The MIPI DSI PHY supports up to 4-lane output.
19 pattern: "^dsi-phy@[0-9a-f]+$"
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H A Dti,phy-j721e-wiz.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Kishon Vijay Abraham I <kishon@ti.com>
16 - ti,j721e-wiz-16g
17 - ti,j721e-wiz-10g
18 - ti,j721s2-wiz-10g
19 - ti,am64-wiz-10g
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/linux/drivers/clk/sunxi/
H A Dclk-a20-gmac.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright 2013 Chen-Yu Tsai
7 * Chen-Yu Tsai <wens@csie.org>
10 #include <linux/clk-provider.h>
29 * sun7i_a20_gmac_clk_setup - Setup function for A20/A31 GMAC clock module
30 * @node: &struct device_node for the clock
32 * This clock looks something like this
34 * MII TX clock from PHY >-----|___________ _________|----> to GMAC core
35 * GMAC Int. RGMII TX clk >----|___________\__/__gate---|----> to PHY
36 * Ext. 125MHz RGMII TX clk >--|__divider__/ |
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/linux/drivers/clk/qcom/
H A Dipq-cmn-pll.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
7 * CMN PLL block expects the reference clock from on-board Wi-Fi block,
8 * and supplies fixed rate clocks as output to the networking hardware
10 * process engine), the externally connected PHY or switch devices, and
13 * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
14 * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
15 * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
16 * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
19 * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-ldb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Liu Ying <victor.liu@nxp.com>
29 in dual mode or split mode. In dual mode, the two channels output identical
34 the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in
41 - fsl,imx8qm-ldb
42 - fsl,imx8qxp-ldb
44 "#address-cells":
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/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ul-var-som.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Support for Variscite VAR-SOM-MX6UL Module
9 /dts-v1/;
12 #include <dt-bindings/clock/imx6ul-clock.h>
13 #include <dt-bindings/gpio/gpio.h>
16 model = "Variscite VAR-SOM-MX6UL module";
17 compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
24 reg_gpio_dvfs: reg-gpio-dvfs {
25 compatible = "regulator-gpio";
26 regulator-min-microvolt = <1300000>;
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H A Dimx6ul-var-som-concerto.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL
10 #include "imx6ul-var-som.dtsi"
11 #include <dt-bindings/leds/common.h>
14 model = "Variscite VAR-SOM-MX6UL Concerto Board";
15 compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
18 stdout-path = &uart1;
21 gpio-keys {
22 compatible = "gpio-keys";
23 pinctrl-names = "default";
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/linux/drivers/gpu/drm/amd/display/include/
H A Dbios_parser_types.h2 * Copyright 2012-15 Advanced Micro Devices, Inc.
158 /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should
159 * be pixel clock * deep_color_ratio (in KHz)
197 /* Input: Signal Type - to be converted to Encoder mode */
201 /* Input: Pixel Clock (requested Pixel clock based on Video timing
205 /* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */
207 /* Output: If non-zero, this refDiv value should be used to calculate
210 /* Output: If non-zero, this postDiv value should be used to calculate
219 enum clock_source_id pll_id; /* Clock Source Id */
220 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */
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/linux/Documentation/devicetree/bindings/pci/
H A Drockchip-dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
22 - description: AHB clock for PCIe master
23 - description: AHB clock for PCIe slave
24 - description: AHB clock for PCIe dbi
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/linux/Documentation/devicetree/bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 +------------------------------------------------------------+
15 +--------+ | +----------------+ +-----------+ |
16 | DPDMA | --->| | --> | Video | Video +-------------+ |
17 | 4x vid | | | | | Rendering | -+--> | | | +------+
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
19 +--------+ | | Buffer Manager | +-----------+ | | Source | | +------+
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/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-dsi.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include "phy-mtk-mipi-dsi.h"
18 dev_dbg(mipi_tx->dev, "set rate: %lu Hz\n", rate); in mtk_mipi_tx_pll_set_rate()
20 mipi_tx->data_rate = rate; in mtk_mipi_tx_pll_set_rate()
30 return mipi_tx->data_rate; in mtk_mipi_tx_pll_recalc_rate()
33 static int mtk_mipi_tx_power_on(struct phy *phy) in mtk_mipi_tx_power_on() argument
35 struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy); in mtk_mipi_tx_power_on()
39 ret = clk_prepare_enable(mipi_tx->pll_hw.clk); in mtk_mipi_tx_power_on()
44 mipi_tx->driver_data->mipi_tx_enable_signal(phy); in mtk_mipi_tx_power_on()
48 static int mtk_mipi_tx_power_off(struct phy *phy) in mtk_mipi_tx_power_off() argument
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/linux/Documentation/devicetree/bindings/usb/
H A Dsnps,dwc3-common.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
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/linux/Documentation/devicetree/bindings/clock/
H A Dsamsung,exynos5260-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/samsung,exynos5260-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung Exynos5260 SoC clock controller
10 - Chanwoo Choi <cw00.choi@samsung.com>
11 - Krzysztof Kozlowski <krzk@kernel.org>
12 - Sylwester Nawrocki <s.nawrocki@samsung.com>
13 - Tomasz Figa <tomasz.figa@gmail.com>
16 Expected external clocks, defined in DTS as fixed-rate clocks with a matching
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H A Dbrcm,iproc-clocks.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/brcm,iproc-clocks.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ray Jui <rjui@broadcom.com>
11 - Scott Branden <sbranden@broadcom.com>
14 The iProc clock controller manages clocks that are common to the iProc family.
20 reference clock of the onboard crystal.
25 - brcm,bcm63138-armpll
26 - brcm,cygnus-armpll
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/linux/drivers/phy/marvell/
H A Dphy-mvebu-a3700-comphy.c1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
23 #include <linux/phy.h>
24 #include <linux/phy/phy.h>
36 /* SATA and USB3 PHY offset compared to SATA PHY */
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
178 * It is used only for SATA PHY initialization.
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/linux/Documentation/devicetree/bindings/media/i2c/
H A Dtoshiba,tc358746.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marco Felsch <kernel@pengutronix.de>
12 description: |-
13 The Toshiba TC358746 converts a parallel video stream into a MIPI CSI-2
14 stream. The direction can be either parallel-in -> csi-out or csi-in ->
15 parallel-out The chip is programmable through I2C and SPI but the SPI
16 interface is only supported in parallel-in -> csi-out mode.
19 parallel-in -> csi-out path.
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