xref: /linux/Documentation/devicetree/bindings/net/nxp,tja11xx.yaml (revision 3fd6c59042dbba50391e30862beac979491145fe)

# SPDX-License-Identifier: GPL-2.0+
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/nxp,tja11xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: NXP TJA11xx PHY

maintainers:
  - Andrew Lunn <andrew@lunn.ch>
  - Florian Fainelli <f.fainelli@gmail.com>
  - Heiner Kallweit <hkallweit1@gmail.com>

description:
  Bindings for NXP TJA11xx automotive PHYs

properties:
  compatible:
    enum:
      - ethernet-phy-id0180.dc40
      - ethernet-phy-id0180.dc41
      - ethernet-phy-id0180.dc48
      - ethernet-phy-id0180.dd00
      - ethernet-phy-id0180.dd01
      - ethernet-phy-id0180.dd02
      - ethernet-phy-id0180.dc80
      - ethernet-phy-id0180.dc82
      - ethernet-phy-id001b.b010
      - ethernet-phy-id001b.b013
      - ethernet-phy-id001b.b030
      - ethernet-phy-id001b.b031

allOf:
  - $ref: ethernet-phy.yaml#
  - if:
      properties:
        compatible:
          contains:
            enum:
              - ethernet-phy-id0180.dc40
              - ethernet-phy-id0180.dc41
              - ethernet-phy-id0180.dc48
              - ethernet-phy-id0180.dd00
              - ethernet-phy-id0180.dd01
              - ethernet-phy-id0180.dd02

    then:
      properties:
        nxp,rmii-refclk-in:
          type: boolean
          description: |
            The REF_CLK is provided for both transmitted and received data
            in RMII mode. This clock signal is provided by the PHY and is
            typically derived from an external 25MHz crystal. Alternatively,
            a 50MHz clock signal generated by an external oscillator can be
            connected to pin REF_CLK. A third option is to connect a 25MHz
            clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
            as input or output according to the actual circuit connection.
            If present, indicates that the REF_CLK will be configured as
            interface reference clock input when RMII mode enabled.
            If not present, the REF_CLK will be configured as interface
            reference clock output when RMII mode enabled.
            Only supported on TJA1100 and TJA1101.

  - if:
      properties:
        compatible:
          contains:
            enum:
              - ethernet-phy-id001b.b010
              - ethernet-phy-id001b.b013
              - ethernet-phy-id001b.b030
              - ethernet-phy-id001b.b031

    then:
      properties:
        nxp,rmii-refclk-out:
          type: boolean
          description: Enable 50MHz RMII reference clock output on REF_CLK pin.

patternProperties:
  "^ethernet-phy@[0-9a-f]+$":
    type: object
    additionalProperties: false
    description: |
      Some packages have multiple PHYs. Secondary PHY should be defines as
      subnode of the first (parent) PHY.

    properties:
      reg:
        minimum: 0
        maximum: 31
        description:
          The ID number for the child PHY. Should be +1 of parent PHY.

    required:
      - reg

unevaluatedProperties: false

examples:
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        tja1101_phy0: ethernet-phy@4 {
            compatible = "ethernet-phy-id0180.dc40";
            reg = <0x4>;
            nxp,rmii-refclk-in;
        };
    };
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        tja1102_phy0: ethernet-phy@4 {
            reg = <0x4>;
            #address-cells = <1>;
            #size-cells = <0>;

            tja1102_phy1: ethernet-phy@5 {
                reg = <0x5>;
            };
        };
    };