Lines Matching +full:phy +full:- +full:output +full:- +full:reference +full:- +full:clock
1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Felipe Balbi <balbi@kernel.org>
14 vendor-specific implementation or as a standalone component.
17 - $ref: usb-drd.yaml#
18 - if:
24 - dr_mode
28 $ref: usb-xhci.yaml#
35 usb-phy:
38 - description: USB2/HS PHY
39 - description: USB3/SS PHY
45 phy-names:
49 - items:
50 enum: [ usb2-phy, usb3-phy ]
51 - items:
52 pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$"
54 snps,usb2-lpm-disable:
63 snps,usb2-gadget-lpm-disable:
68 snps,reserved-endpoints:
70 Reserve endpoints for other needs, e.g, for tracing control and output.
72 $ref: /schemas/types.yaml#/definitions/uint8-array
79 snps,dis-start-transfer-quirk:
81 When set, disable isoc START TRANSFER command failure SW work-around
82 for DWC_usb31 version 1.70a-ea06 and prior.
91 snps,has-lpm-erratum:
95 snps,lpm-nyet-threshold:
119 description: When set core will delay PHY power change from P0 to P1/P2/P3.
133 description: When set core will set Tx de-emphasis value
138 The value driven to the PHY is controlled by the LTSSM during USB3
142 - 0 # -6dB de-emphasis
143 - 1 # -3.5dB de-emphasis
144 - 2 # No de-emphasis
147 description: When set core will disable USB3 suspend phy
151 description: When set core will disable USB2 suspend phy
157 to the PHY.
160 snps,dis-u1-entry-quirk:
164 snps,dis-u2-entry-quirk:
170 When set core will disable receiver detection in PHY P3 power state.
173 snps,dis-u2-freeclk-exists-quirk:
176 PHY doesn't provide a free-running PHY clock.
179 snps,dis-del-phy-power-chg-quirk:
181 When set core will change PHY power from P0 to P1/P2/P3 without delay.
184 snps,dis-tx-ipgap-linecheck-quirk:
188 snps,parkmode-disable-ss-quirk:
193 snps,parkmode-disable-hs-quirk:
204 snps,dis-split-quirk:
207 avoid -EPROTO errors with usbhid on some devices (Hikey 970).
210 snps,gfladj-refclk-lpm-sel-quirk:
215 snps,resume-hs-terminations:
222 snps,ulpi-ext-vbus-drv:
224 Some ULPI USB PHY does not support internal VBUS supply, and driving
226 bit. When set, the xhci host will configure the USB2 PHY drives VBUS
230 snps,is-utmi-l1-suspend:
232 True when DWC3 asserts output signal utmi_l1_suspend_n, false when
236 snps,hird-threshold:
242 High-Speed PHY interface selection between UTMI+ and ULPI when the
247 snps,quirk-frame-length-adjustment:
249 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
256 snps,ref-clock-period-ns:
258 Value for REFCLKPER field of GUCTL register for reference clock period in
260 clock.
262 This binding is deprecated. Instead, provide an appropriate reference clock.
267 snps,rx-thr-num-pkt:
274 flow-controlled endpoint. It is only used for SuperSpeed.
281 snps,rx-max-burst:
297 snps,tx-thr-num-pkt:
310 snps,tx-max-burst:
323 snps,rx-thr-num-pkt-prd:
326 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
332 snps,rx-max-burst-prd:
335 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
341 snps,tx-thr-num-pkt-prd:
344 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
350 snps,tx-max-burst-prd:
353 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
359 tx-fifo-resize:
367 tx-fifo-max-num:
375 snps,incr-burst-type-adjustment:
382 $ref: /schemas/types.yaml#/definitions/uint32-array
389 num-hc-interrupters:
394 $ref: /schemas/connector/usb-connector.yaml#
402 This port is used with the 'usb-role-switch' property to connect the
409 controller using the OF graph bindings specified if the "usb-role-switch"
421 wakeup-source:
427 - compatible
428 - reg