1*3f12669bSRaphael Gallais-Pou# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*3f12669bSRaphael Gallais-Pou%YAML 1.2 3*3f12669bSRaphael Gallais-Pou--- 4*3f12669bSRaphael Gallais-Pou$id: http://devicetree.org/schemas/display/st,stm32mp25-lvds.yaml# 5*3f12669bSRaphael Gallais-Pou$schema: http://devicetree.org/meta-schemas/core.yaml# 6*3f12669bSRaphael Gallais-Pou 7*3f12669bSRaphael Gallais-Poutitle: STMicroelectronics STM32 LVDS Display Interface Transmitter 8*3f12669bSRaphael Gallais-Pou 9*3f12669bSRaphael Gallais-Poumaintainers: 10*3f12669bSRaphael Gallais-Pou - Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com> 11*3f12669bSRaphael Gallais-Pou - Yannick Fertre <yannick.fertre@foss.st.com> 12*3f12669bSRaphael Gallais-Pou 13*3f12669bSRaphael Gallais-Poudescription: | 14*3f12669bSRaphael Gallais-Pou The STMicroelectronics STM32 LVDS Display Interface Transmitter handles the 15*3f12669bSRaphael Gallais-Pou LVDS protocol: it maps the pixels received from the upstream Pixel-DMA (LTDC) 16*3f12669bSRaphael Gallais-Pou onto the LVDS PHY. 17*3f12669bSRaphael Gallais-Pou 18*3f12669bSRaphael Gallais-Pou It is composed of three sub blocks: 19*3f12669bSRaphael Gallais-Pou - LVDS host: handles the LVDS protocol (FPD / OpenLDI) and maps its input 20*3f12669bSRaphael Gallais-Pou pixels onto the data lanes of the PHY 21*3f12669bSRaphael Gallais-Pou - LVDS PHY: parallelize the data and drives the LVDS data lanes 22*3f12669bSRaphael Gallais-Pou - LVDS wrapper: handles top-level settings 23*3f12669bSRaphael Gallais-Pou 24*3f12669bSRaphael Gallais-Pou The LVDS controller driver supports the following high-level features: 25*3f12669bSRaphael Gallais-Pou - FDP-Link-I and OpenLDI (v0.95) protocols 26*3f12669bSRaphael Gallais-Pou - Single-Link or Dual-Link operation 27*3f12669bSRaphael Gallais-Pou - Single-Display or Double-Display (with the same content duplicated on both) 28*3f12669bSRaphael Gallais-Pou - Flexible Bit-Mapping, including JEIDA and VESA 29*3f12669bSRaphael Gallais-Pou - RGB888 or RGB666 output 30*3f12669bSRaphael Gallais-Pou - Synchronous design, with one input pixel per clock cycle 31*3f12669bSRaphael Gallais-Pou 32*3f12669bSRaphael Gallais-Pouproperties: 33*3f12669bSRaphael Gallais-Pou compatible: 34*3f12669bSRaphael Gallais-Pou const: st,stm32mp25-lvds 35*3f12669bSRaphael Gallais-Pou 36*3f12669bSRaphael Gallais-Pou "#clock-cells": 37*3f12669bSRaphael Gallais-Pou const: 0 38*3f12669bSRaphael Gallais-Pou description: 39*3f12669bSRaphael Gallais-Pou Provides the internal LVDS PHY clock to the framework. 40*3f12669bSRaphael Gallais-Pou 41*3f12669bSRaphael Gallais-Pou reg: 42*3f12669bSRaphael Gallais-Pou maxItems: 1 43*3f12669bSRaphael Gallais-Pou 44*3f12669bSRaphael Gallais-Pou clocks: 45*3f12669bSRaphael Gallais-Pou items: 46*3f12669bSRaphael Gallais-Pou - description: APB peripheral clock 47*3f12669bSRaphael Gallais-Pou - description: Reference clock for the internal PLL 48*3f12669bSRaphael Gallais-Pou 49*3f12669bSRaphael Gallais-Pou clock-names: 50*3f12669bSRaphael Gallais-Pou items: 51*3f12669bSRaphael Gallais-Pou - const: pclk 52*3f12669bSRaphael Gallais-Pou - const: ref 53*3f12669bSRaphael Gallais-Pou 54*3f12669bSRaphael Gallais-Pou resets: 55*3f12669bSRaphael Gallais-Pou maxItems: 1 56*3f12669bSRaphael Gallais-Pou 57*3f12669bSRaphael Gallais-Pou ports: 58*3f12669bSRaphael Gallais-Pou $ref: /schemas/graph.yaml#/properties/ports 59*3f12669bSRaphael Gallais-Pou 60*3f12669bSRaphael Gallais-Pou properties: 61*3f12669bSRaphael Gallais-Pou port@0: 62*3f12669bSRaphael Gallais-Pou $ref: /schemas/graph.yaml#/properties/port 63*3f12669bSRaphael Gallais-Pou description: 64*3f12669bSRaphael Gallais-Pou LVDS input port node, connected to the LTDC RGB output port. 65*3f12669bSRaphael Gallais-Pou 66*3f12669bSRaphael Gallais-Pou port@1: 67*3f12669bSRaphael Gallais-Pou $ref: /schemas/graph.yaml#/properties/port 68*3f12669bSRaphael Gallais-Pou description: 69*3f12669bSRaphael Gallais-Pou LVDS output port node, connected to a panel or bridge input port. 70*3f12669bSRaphael Gallais-Pou 71*3f12669bSRaphael Gallais-Pou required: 72*3f12669bSRaphael Gallais-Pou - port@0 73*3f12669bSRaphael Gallais-Pou - port@1 74*3f12669bSRaphael Gallais-Pou 75*3f12669bSRaphael Gallais-Pourequired: 76*3f12669bSRaphael Gallais-Pou - compatible 77*3f12669bSRaphael Gallais-Pou - "#clock-cells" 78*3f12669bSRaphael Gallais-Pou - reg 79*3f12669bSRaphael Gallais-Pou - clocks 80*3f12669bSRaphael Gallais-Pou - clock-names 81*3f12669bSRaphael Gallais-Pou - resets 82*3f12669bSRaphael Gallais-Pou - ports 83*3f12669bSRaphael Gallais-Pou 84*3f12669bSRaphael Gallais-PouadditionalProperties: false 85*3f12669bSRaphael Gallais-Pou 86*3f12669bSRaphael Gallais-Pouexamples: 87*3f12669bSRaphael Gallais-Pou - | 88*3f12669bSRaphael Gallais-Pou #include <dt-bindings/clock/st,stm32mp25-rcc.h> 89*3f12669bSRaphael Gallais-Pou #include <dt-bindings/reset/st,stm32mp25-rcc.h> 90*3f12669bSRaphael Gallais-Pou 91*3f12669bSRaphael Gallais-Pou lvds: lvds@48060000 { 92*3f12669bSRaphael Gallais-Pou compatible = "st,stm32mp25-lvds"; 93*3f12669bSRaphael Gallais-Pou reg = <0x48060000 0x2000>; 94*3f12669bSRaphael Gallais-Pou #clock-cells = <0>; 95*3f12669bSRaphael Gallais-Pou clocks = <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; 96*3f12669bSRaphael Gallais-Pou clock-names = "pclk", "ref"; 97*3f12669bSRaphael Gallais-Pou resets = <&rcc LVDS_R>; 98*3f12669bSRaphael Gallais-Pou 99*3f12669bSRaphael Gallais-Pou ports { 100*3f12669bSRaphael Gallais-Pou #address-cells = <1>; 101*3f12669bSRaphael Gallais-Pou #size-cells = <0>; 102*3f12669bSRaphael Gallais-Pou 103*3f12669bSRaphael Gallais-Pou port@0 { 104*3f12669bSRaphael Gallais-Pou reg = <0>; 105*3f12669bSRaphael Gallais-Pou lvds_in: endpoint { 106*3f12669bSRaphael Gallais-Pou remote-endpoint = <<dc_ep1_out>; 107*3f12669bSRaphael Gallais-Pou }; 108*3f12669bSRaphael Gallais-Pou }; 109*3f12669bSRaphael Gallais-Pou 110*3f12669bSRaphael Gallais-Pou port@1 { 111*3f12669bSRaphael Gallais-Pou reg = <1>; 112*3f12669bSRaphael Gallais-Pou lvds_out0: endpoint { 113*3f12669bSRaphael Gallais-Pou remote-endpoint = <&lvds_panel_in>; 114*3f12669bSRaphael Gallais-Pou }; 115*3f12669bSRaphael Gallais-Pou }; 116*3f12669bSRaphael Gallais-Pou }; 117*3f12669bSRaphael Gallais-Pou }; 118*3f12669bSRaphael Gallais-Pou 119*3f12669bSRaphael Gallais-Pou... 120