xref: /linux/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
1e7c7970aSHyun Kwon# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2e7c7970aSHyun Kwon%YAML 1.2
3e7c7970aSHyun Kwon---
4e7c7970aSHyun Kwon$id: http://devicetree.org/schemas/display/xlnx/xlnx,zynqmp-dpsub.yaml#
5e7c7970aSHyun Kwon$schema: http://devicetree.org/meta-schemas/core.yaml#
6e7c7970aSHyun Kwon
7e7c7970aSHyun Kwontitle: Xilinx ZynqMP DisplayPort Subsystem
8e7c7970aSHyun Kwon
9e7c7970aSHyun Kwondescription: |
10e7c7970aSHyun Kwon  The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11e7c7970aSHyun Kwon  implements the display and audio pipelines based on the DisplayPort v1.2
12e7c7970aSHyun Kwon  standard. The subsystem includes multiple functional blocks as below:
13e7c7970aSHyun Kwon
14e7c7970aSHyun Kwon               +------------------------------------------------------------+
15e7c7970aSHyun Kwon  +--------+   | +----------------+     +-----------+                       |
16e7c7970aSHyun Kwon  | DPDMA  | --->|                | --> |   Video   | Video +-------------+ |
17e7c7970aSHyun Kwon  | 4x vid |   | |                |     | Rendering | -+--> |             | |   +------+
18e7c7970aSHyun Kwon  | 2x aud |   | |  Audio/Video   | --> | Pipeline  |  |    | DisplayPort |---> | PHY0 |
19e7c7970aSHyun Kwon  +--------+   | | Buffer Manager |     +-----------+  |    |   Source    | |   +------+
20e7c7970aSHyun Kwon               | |    and STC     |     +-----------+  |    | Controller  | |   +------+
21e7c7970aSHyun Kwon  Live Video --->|                | --> |   Audio   | Audio |             |---> | PHY1 |
22e7c7970aSHyun Kwon               | |                |     |   Mixer   | --+-> |             | |   +------+
23e7c7970aSHyun Kwon  Live Audio --->|                | --> |           |  ||   +-------------+ |
24e7c7970aSHyun Kwon               | +----------------+     +-----------+  ||                   |
25e7c7970aSHyun Kwon               +---------------------------------------||-------------------+
26e7c7970aSHyun Kwon                                                       vv
27e7c7970aSHyun Kwon                                                 Blended Video and
28e7c7970aSHyun Kwon                                                 Mixed Audio to PL
29e7c7970aSHyun Kwon
30e7c7970aSHyun Kwon  The Buffer Manager interacts with external interface such as DMA engines or
31e7c7970aSHyun Kwon  live audio/video streams from the programmable logic. The Video Rendering
32e7c7970aSHyun Kwon  Pipeline blends the video and graphics layers and performs colorspace
33e7c7970aSHyun Kwon  conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
34e7c7970aSHyun Kwon  Source Controller handles the DisplayPort protocol and connects to external
35e7c7970aSHyun Kwon  PHYs.
36e7c7970aSHyun Kwon
37e7c7970aSHyun Kwon  The subsystem supports 2 video and 2 audio streams, and various pixel formats
38e7c7970aSHyun Kwon  and depths up to 4K@30 resolution.
39e7c7970aSHyun Kwon
40e7c7970aSHyun Kwon  Please refer to "Zynq UltraScale+ Device Technical Reference Manual"
41e7c7970aSHyun Kwon  (https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf)
42e7c7970aSHyun Kwon  for more details.
43e7c7970aSHyun Kwon
44e7c7970aSHyun Kwonmaintainers:
45e7c7970aSHyun Kwon  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
46e7c7970aSHyun Kwon
47e7c7970aSHyun Kwonproperties:
48e7c7970aSHyun Kwon  compatible:
49e7c7970aSHyun Kwon    const: xlnx,zynqmp-dpsub-1.7
50e7c7970aSHyun Kwon
51e7c7970aSHyun Kwon  reg:
52e7c7970aSHyun Kwon    maxItems: 4
53e7c7970aSHyun Kwon  reg-names:
54e7c7970aSHyun Kwon    items:
55e7c7970aSHyun Kwon      - const: dp
56e7c7970aSHyun Kwon      - const: blend
57e7c7970aSHyun Kwon      - const: av_buf
58e7c7970aSHyun Kwon      - const: aud
59e7c7970aSHyun Kwon
60e7c7970aSHyun Kwon  interrupts:
61e7c7970aSHyun Kwon    maxItems: 1
62e7c7970aSHyun Kwon
63e7c7970aSHyun Kwon  clocks:
64e7c7970aSHyun Kwon    description:
65e7c7970aSHyun Kwon      The APB clock and at least one video clock are mandatory, the audio clock
66e7c7970aSHyun Kwon      is optional.
67e7c7970aSHyun Kwon    minItems: 2
68e7c7970aSHyun Kwon    items:
69e7c7970aSHyun Kwon      - description: dp_apb_clk is the APB clock
70e7c7970aSHyun Kwon      - description: dp_aud_clk is the Audio clock
71e7c7970aSHyun Kwon      - description:
72e7c7970aSHyun Kwon          dp_vtc_pixel_clk_in is the non-live video clock (from Processing
73e7c7970aSHyun Kwon          System)
74e7c7970aSHyun Kwon      - description:
75e7c7970aSHyun Kwon          dp_live_video_in_clk is the live video clock (from Programmable
76e7c7970aSHyun Kwon          Logic)
77e7c7970aSHyun Kwon  clock-names:
78e7c7970aSHyun Kwon    oneOf:
79e7c7970aSHyun Kwon      - minItems: 2
80e7c7970aSHyun Kwon        items:
81e7c7970aSHyun Kwon          - const: dp_apb_clk
82e7c7970aSHyun Kwon          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
83e7c7970aSHyun Kwon          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
84e7c7970aSHyun Kwon      - minItems: 3
85e7c7970aSHyun Kwon        items:
86e7c7970aSHyun Kwon          - const: dp_apb_clk
87e7c7970aSHyun Kwon          - const: dp_aud_clk
88e7c7970aSHyun Kwon          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
89e7c7970aSHyun Kwon          - enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
90e7c7970aSHyun Kwon
91e7c7970aSHyun Kwon  power-domains:
92e7c7970aSHyun Kwon    maxItems: 1
93e7c7970aSHyun Kwon
94e7c7970aSHyun Kwon  resets:
95e7c7970aSHyun Kwon    maxItems: 1
96e7c7970aSHyun Kwon
97e7c7970aSHyun Kwon  dmas:
98e7c7970aSHyun Kwon    items:
99e7c7970aSHyun Kwon      - description: Video layer, plane 0 (RGB or luma)
100e7c7970aSHyun Kwon      - description: Video layer, plane 1 (U/V or U)
101e7c7970aSHyun Kwon      - description: Video layer, plane 2 (V)
102e7c7970aSHyun Kwon      - description: Graphics layer
103e7c7970aSHyun Kwon  dma-names:
104e7c7970aSHyun Kwon    items:
105e7c7970aSHyun Kwon      - const: vid0
106e7c7970aSHyun Kwon      - const: vid1
107e7c7970aSHyun Kwon      - const: vid2
108e7c7970aSHyun Kwon      - const: gfx0
109e7c7970aSHyun Kwon
110e7c7970aSHyun Kwon  phys:
111e7c7970aSHyun Kwon    description: PHYs for the DP data lanes
112e7c7970aSHyun Kwon    minItems: 1
113e7c7970aSHyun Kwon    maxItems: 2
114e7c7970aSHyun Kwon  phy-names:
115e7c7970aSHyun Kwon    minItems: 1
116e7c7970aSHyun Kwon    items:
117e7c7970aSHyun Kwon      - const: dp-phy0
118e7c7970aSHyun Kwon      - const: dp-phy1
119e7c7970aSHyun Kwon
120*833cad8cSLaurent Pinchart  ports:
121*833cad8cSLaurent Pinchart    $ref: /schemas/graph.yaml#/properties/ports
122*833cad8cSLaurent Pinchart    description: |
123*833cad8cSLaurent Pinchart      Connections to the programmable logic and the DisplayPort PHYs. Each port
124*833cad8cSLaurent Pinchart      shall have a single endpoint.
125*833cad8cSLaurent Pinchart
126*833cad8cSLaurent Pinchart    properties:
127*833cad8cSLaurent Pinchart      port@0:
128*833cad8cSLaurent Pinchart        $ref: /schemas/graph.yaml#/properties/port
129*833cad8cSLaurent Pinchart        description: The live video input from the programmable logic
130*833cad8cSLaurent Pinchart
131*833cad8cSLaurent Pinchart      port@1:
132*833cad8cSLaurent Pinchart        $ref: /schemas/graph.yaml#/properties/port
133*833cad8cSLaurent Pinchart        description: The live graphics input from the programmable logic
134*833cad8cSLaurent Pinchart
135*833cad8cSLaurent Pinchart      port@2:
136*833cad8cSLaurent Pinchart        $ref: /schemas/graph.yaml#/properties/port
137*833cad8cSLaurent Pinchart        description: The live audio input from the programmable logic
138*833cad8cSLaurent Pinchart
139*833cad8cSLaurent Pinchart      port@3:
140*833cad8cSLaurent Pinchart        $ref: /schemas/graph.yaml#/properties/port
141*833cad8cSLaurent Pinchart        description: The blended video output to the programmable logic
142*833cad8cSLaurent Pinchart
143*833cad8cSLaurent Pinchart      port@4:
144*833cad8cSLaurent Pinchart        $ref: /schemas/graph.yaml#/properties/port
145*833cad8cSLaurent Pinchart        description: The mixed audio output to the programmable logic
146*833cad8cSLaurent Pinchart
147*833cad8cSLaurent Pinchart      port@5:
148*833cad8cSLaurent Pinchart        $ref: /schemas/graph.yaml#/properties/port
149*833cad8cSLaurent Pinchart        description: The DisplayPort output
150*833cad8cSLaurent Pinchart
151*833cad8cSLaurent Pinchart    required:
152*833cad8cSLaurent Pinchart      - port@0
153*833cad8cSLaurent Pinchart      - port@1
154*833cad8cSLaurent Pinchart      - port@2
155*833cad8cSLaurent Pinchart      - port@3
156*833cad8cSLaurent Pinchart      - port@4
157*833cad8cSLaurent Pinchart      - port@5
158*833cad8cSLaurent Pinchart
159e7c7970aSHyun Kwonrequired:
160e7c7970aSHyun Kwon  - compatible
161e7c7970aSHyun Kwon  - reg
162e7c7970aSHyun Kwon  - reg-names
163e7c7970aSHyun Kwon  - interrupts
164e7c7970aSHyun Kwon  - clocks
165e7c7970aSHyun Kwon  - clock-names
166e7c7970aSHyun Kwon  - power-domains
167e7c7970aSHyun Kwon  - resets
168e7c7970aSHyun Kwon  - dmas
169e7c7970aSHyun Kwon  - dma-names
170e7c7970aSHyun Kwon  - phys
171e7c7970aSHyun Kwon  - phy-names
172*833cad8cSLaurent Pinchart  - ports
173e7c7970aSHyun Kwon
174e7c7970aSHyun KwonadditionalProperties: false
175e7c7970aSHyun Kwon
176e7c7970aSHyun Kwonexamples:
177e7c7970aSHyun Kwon  - |
178e7c7970aSHyun Kwon    #include <dt-bindings/phy/phy.h>
179e7c7970aSHyun Kwon    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
180e7c7970aSHyun Kwon
181e7c7970aSHyun Kwon    display@fd4a0000 {
182e7c7970aSHyun Kwon        compatible = "xlnx,zynqmp-dpsub-1.7";
18364ff609bSRob Herring        reg = <0xfd4a0000 0x1000>,
18464ff609bSRob Herring              <0xfd4aa000 0x1000>,
18564ff609bSRob Herring              <0xfd4ab000 0x1000>,
18664ff609bSRob Herring              <0xfd4ac000 0x1000>;
187e7c7970aSHyun Kwon        reg-names = "dp", "blend", "av_buf", "aud";
188e7c7970aSHyun Kwon        interrupts = <0 119 4>;
189e7c7970aSHyun Kwon        interrupt-parent = <&gic>;
190e7c7970aSHyun Kwon
191e7c7970aSHyun Kwon        clock-names = "dp_apb_clk", "dp_aud_clk", "dp_live_video_in_clk";
192e7c7970aSHyun Kwon        clocks = <&dp_aclk>, <&clkc 17>, <&si570_1>;
193e7c7970aSHyun Kwon
194e7c7970aSHyun Kwon        power-domains = <&pd_dp>;
195e7c7970aSHyun Kwon        resets = <&reset ZYNQMP_RESET_DP>;
196e7c7970aSHyun Kwon
197e7c7970aSHyun Kwon        dma-names = "vid0", "vid1", "vid2", "gfx0";
198e7c7970aSHyun Kwon        dmas = <&xlnx_dpdma 0>,
199e7c7970aSHyun Kwon               <&xlnx_dpdma 1>,
200e7c7970aSHyun Kwon               <&xlnx_dpdma 2>,
201e7c7970aSHyun Kwon               <&xlnx_dpdma 3>;
202e7c7970aSHyun Kwon
2035628d9f1SMichal Simek        phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
2045628d9f1SMichal Simek               <&psgtr 0 PHY_TYPE_DP 1 3>;
205e7c7970aSHyun Kwon
206e7c7970aSHyun Kwon        phy-names = "dp-phy0", "dp-phy1";
207*833cad8cSLaurent Pinchart
208*833cad8cSLaurent Pinchart        ports {
209*833cad8cSLaurent Pinchart            #address-cells = <1>;
210*833cad8cSLaurent Pinchart            #size-cells = <0>;
211*833cad8cSLaurent Pinchart
212*833cad8cSLaurent Pinchart            port@0 {
213*833cad8cSLaurent Pinchart                reg = <0>;
214*833cad8cSLaurent Pinchart            };
215*833cad8cSLaurent Pinchart            port@1 {
216*833cad8cSLaurent Pinchart                reg = <1>;
217*833cad8cSLaurent Pinchart            };
218*833cad8cSLaurent Pinchart            port@2 {
219*833cad8cSLaurent Pinchart                reg = <2>;
220*833cad8cSLaurent Pinchart            };
221*833cad8cSLaurent Pinchart            port@3 {
222*833cad8cSLaurent Pinchart                reg = <3>;
223*833cad8cSLaurent Pinchart            };
224*833cad8cSLaurent Pinchart            port@4 {
225*833cad8cSLaurent Pinchart                reg = <4>;
226*833cad8cSLaurent Pinchart            };
227*833cad8cSLaurent Pinchart            port@5 {
228*833cad8cSLaurent Pinchart                reg = <5>;
229*833cad8cSLaurent Pinchart                dpsub_dp_out: endpoint {
230*833cad8cSLaurent Pinchart                    remote-endpoint = <&dp_connector>;
231*833cad8cSLaurent Pinchart                };
232*833cad8cSLaurent Pinchart            };
233*833cad8cSLaurent Pinchart        };
234e7c7970aSHyun Kwon    };
235e7c7970aSHyun Kwon
236e7c7970aSHyun Kwon...
237