1ad044f01SKishon Vijay Abraham I# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2ad044f01SKishon Vijay Abraham I# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/ 3ad044f01SKishon Vijay Abraham I%YAML 1.2 4ad044f01SKishon Vijay Abraham I--- 5e43462c1SRob Herring$id: http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml# 6e43462c1SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 7ad044f01SKishon Vijay Abraham I 8ad044f01SKishon Vijay Abraham Ititle: TI J721E WIZ (SERDES Wrapper) 9ad044f01SKishon Vijay Abraham I 10ad044f01SKishon Vijay Abraham Imaintainers: 11ad044f01SKishon Vijay Abraham I - Kishon Vijay Abraham I <kishon@ti.com> 12ad044f01SKishon Vijay Abraham I 13ad044f01SKishon Vijay Abraham Iproperties: 14ad044f01SKishon Vijay Abraham I compatible: 15ad044f01SKishon Vijay Abraham I enum: 16ad044f01SKishon Vijay Abraham I - ti,j721e-wiz-16g 17ad044f01SKishon Vijay Abraham I - ti,j721e-wiz-10g 18f12faa3bSMatt Ranostay - ti,j721s2-wiz-10g 196c363eafSKishon Vijay Abraham I - ti,am64-wiz-10g 20d5f2e747SRoger Quadros - ti,j7200-wiz-10g 21cbdbe312SMatt Ranostay - ti,j784s4-wiz-10g 22ad044f01SKishon Vijay Abraham I 23ad044f01SKishon Vijay Abraham I power-domains: 24ad044f01SKishon Vijay Abraham I maxItems: 1 25ad044f01SKishon Vijay Abraham I 26ad044f01SKishon Vijay Abraham I clocks: 27d5f2e747SRoger Quadros minItems: 3 28d5f2e747SRoger Quadros maxItems: 4 29ad044f01SKishon Vijay Abraham I description: clock-specifier to represent input to the WIZ 30ad044f01SKishon Vijay Abraham I 31ad044f01SKishon Vijay Abraham I clock-names: 32d5f2e747SRoger Quadros minItems: 3 33ad044f01SKishon Vijay Abraham I items: 34ad044f01SKishon Vijay Abraham I - const: fck 35ad044f01SKishon Vijay Abraham I - const: core_ref_clk 36ad044f01SKishon Vijay Abraham I - const: ext_ref_clk 37d5f2e747SRoger Quadros - const: core_ref1_clk 38ad044f01SKishon Vijay Abraham I 39ad044f01SKishon Vijay Abraham I num-lanes: 40ad044f01SKishon Vijay Abraham I minimum: 1 41ad044f01SKishon Vijay Abraham I maximum: 4 42ad044f01SKishon Vijay Abraham I 43ad044f01SKishon Vijay Abraham I "#address-cells": 44ad044f01SKishon Vijay Abraham I const: 1 45ad044f01SKishon Vijay Abraham I 46ad044f01SKishon Vijay Abraham I "#size-cells": 47ad044f01SKishon Vijay Abraham I const: 1 48ad044f01SKishon Vijay Abraham I 49ad044f01SKishon Vijay Abraham I "#reset-cells": 50ad044f01SKishon Vijay Abraham I const: 1 51ad044f01SKishon Vijay Abraham I 526c363eafSKishon Vijay Abraham I "#clock-cells": 536c363eafSKishon Vijay Abraham I const: 1 546c363eafSKishon Vijay Abraham I 55ad044f01SKishon Vijay Abraham I ranges: true 56ad044f01SKishon Vijay Abraham I 576385cbe9SRoger Quadros typec-dir-gpios: 586385cbe9SRoger Quadros maxItems: 1 596385cbe9SRoger Quadros description: 606385cbe9SRoger Quadros GPIO to signal Type-C cable orientation for lane swap. 616385cbe9SRoger Quadros If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to 62*47aab533SBjorn Helgaas achieve the functionality of an external type-C plug flip mux. 636385cbe9SRoger Quadros 646385cbe9SRoger Quadros typec-dir-debounce-ms: 656385cbe9SRoger Quadros minimum: 100 666385cbe9SRoger Quadros maximum: 1000 676385cbe9SRoger Quadros default: 100 686385cbe9SRoger Quadros description: 696385cbe9SRoger Quadros Number of milliseconds to wait before sampling typec-dir-gpio. 706385cbe9SRoger Quadros If not specified, the default debounce of 100ms will be used. 716385cbe9SRoger Quadros Type-C spec states minimum CC pin debounce of 100 ms and maximum 726385cbe9SRoger Quadros of 200 ms. However, some solutions might need more than 200 ms. 736385cbe9SRoger Quadros 74f88321a3SRob Herring refclk-dig: 75f88321a3SRob Herring type: object 76c77c1853SRob Herring additionalProperties: false 77f88321a3SRob Herring description: | 78f88321a3SRob Herring WIZ node should have subnode for refclk_dig to select the reference 79f88321a3SRob Herring clock source for the reference clock used in the PHY and PMA digital 80f88321a3SRob Herring logic. 811aa54982SRoger Quadros deprecated: true 82f88321a3SRob Herring properties: 83f88321a3SRob Herring clocks: 84f88321a3SRob Herring minItems: 2 85f88321a3SRob Herring maxItems: 4 86f88321a3SRob Herring description: Phandle to two (Torrent) or four (Sierra) clock nodes representing 87f88321a3SRob Herring the inputs to refclk_dig 88f88321a3SRob Herring 89f88321a3SRob Herring "#clock-cells": 90f88321a3SRob Herring const: 0 91f88321a3SRob Herring 92a50abe2eSKrzysztof Kozlowski clock-output-names: 93a50abe2eSKrzysztof Kozlowski maxItems: 1 94a50abe2eSKrzysztof Kozlowski 95f88321a3SRob Herring assigned-clocks: 96f88321a3SRob Herring maxItems: 1 97f88321a3SRob Herring 98f88321a3SRob Herring assigned-clock-parents: 99f88321a3SRob Herring maxItems: 1 100f88321a3SRob Herring 101f88321a3SRob Herring required: 102f88321a3SRob Herring - clocks 103f88321a3SRob Herring - "#clock-cells" 104f88321a3SRob Herring - assigned-clocks 105f88321a3SRob Herring - assigned-clock-parents 106f88321a3SRob Herring 107d5f2e747SRoger Quadros ti,scm: 108d5f2e747SRoger Quadros $ref: /schemas/types.yaml#/definitions/phandle 109d5f2e747SRoger Quadros description: | 110d5f2e747SRoger Quadros phandle to System Control Module for syscon regmap access. 111d5f2e747SRoger Quadros 112ad044f01SKishon Vijay Abraham IpatternProperties: 113ad044f01SKishon Vijay Abraham I "^pll[0|1]-refclk$": 114ad044f01SKishon Vijay Abraham I type: object 115c77c1853SRob Herring additionalProperties: false 116ad044f01SKishon Vijay Abraham I description: | 117ad044f01SKishon Vijay Abraham I WIZ node should have subnodes for each of the PLLs present in 118ad044f01SKishon Vijay Abraham I the SERDES. 1191aa54982SRoger Quadros deprecated: true 120ad044f01SKishon Vijay Abraham I properties: 121ad044f01SKishon Vijay Abraham I clocks: 122ad044f01SKishon Vijay Abraham I maxItems: 2 123ad044f01SKishon Vijay Abraham I description: Phandle to clock nodes representing the two inputs to PLL. 124ad044f01SKishon Vijay Abraham I 125ad044f01SKishon Vijay Abraham I "#clock-cells": 126ad044f01SKishon Vijay Abraham I const: 0 127ad044f01SKishon Vijay Abraham I 128a50abe2eSKrzysztof Kozlowski clock-output-names: 129a50abe2eSKrzysztof Kozlowski maxItems: 1 130a50abe2eSKrzysztof Kozlowski 131ad044f01SKishon Vijay Abraham I assigned-clocks: 132ad044f01SKishon Vijay Abraham I maxItems: 1 133ad044f01SKishon Vijay Abraham I 134ad044f01SKishon Vijay Abraham I assigned-clock-parents: 135ad044f01SKishon Vijay Abraham I maxItems: 1 136ad044f01SKishon Vijay Abraham I 137ad044f01SKishon Vijay Abraham I required: 138ad044f01SKishon Vijay Abraham I - clocks 139ad044f01SKishon Vijay Abraham I - "#clock-cells" 140ad044f01SKishon Vijay Abraham I - assigned-clocks 141ad044f01SKishon Vijay Abraham I - assigned-clock-parents 142ad044f01SKishon Vijay Abraham I 143ad044f01SKishon Vijay Abraham I "^cmn-refclk1?-dig-div$": 144ad044f01SKishon Vijay Abraham I type: object 145c77c1853SRob Herring additionalProperties: false 146ad044f01SKishon Vijay Abraham I description: 147ad044f01SKishon Vijay Abraham I WIZ node should have subnodes for each of the PMA common refclock 148ad044f01SKishon Vijay Abraham I provided by the SERDES. 1491aa54982SRoger Quadros deprecated: true 150ad044f01SKishon Vijay Abraham I properties: 151ad044f01SKishon Vijay Abraham I clocks: 152ad044f01SKishon Vijay Abraham I maxItems: 1 153ad044f01SKishon Vijay Abraham I description: Phandle to the clock node representing the input to the 154ad044f01SKishon Vijay Abraham I divider clock. 155ad044f01SKishon Vijay Abraham I 156ad044f01SKishon Vijay Abraham I "#clock-cells": 157ad044f01SKishon Vijay Abraham I const: 0 158ad044f01SKishon Vijay Abraham I 159a50abe2eSKrzysztof Kozlowski clock-output-names: 160a50abe2eSKrzysztof Kozlowski maxItems: 1 161a50abe2eSKrzysztof Kozlowski 162ad044f01SKishon Vijay Abraham I required: 163ad044f01SKishon Vijay Abraham I - clocks 164ad044f01SKishon Vijay Abraham I - "#clock-cells" 165ad044f01SKishon Vijay Abraham I 166ad044f01SKishon Vijay Abraham I "^serdes@[0-9a-f]+$": 167ad044f01SKishon Vijay Abraham I type: object 168ad044f01SKishon Vijay Abraham I description: | 169ad044f01SKishon Vijay Abraham I WIZ node should have '1' subnode for the SERDES. It could be either 170ad044f01SKishon Vijay Abraham I Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the 171ad044f01SKishon Vijay Abraham I bindings specified in 17234168172SMauro Carvalho Chehab Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml 173ad044f01SKishon Vijay Abraham I Torrent SERDES should follow the bindings specified in 174b8a1707fSMauro Carvalho Chehab Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml 175ad044f01SKishon Vijay Abraham I 176ad044f01SKishon Vijay Abraham Irequired: 177ad044f01SKishon Vijay Abraham I - compatible 178ad044f01SKishon Vijay Abraham I - power-domains 179ad044f01SKishon Vijay Abraham I - clocks 180ad044f01SKishon Vijay Abraham I - clock-names 181ad044f01SKishon Vijay Abraham I - num-lanes 182ad044f01SKishon Vijay Abraham I - "#address-cells" 183ad044f01SKishon Vijay Abraham I - "#size-cells" 184ad044f01SKishon Vijay Abraham I - "#reset-cells" 185ad044f01SKishon Vijay Abraham I - ranges 186ad044f01SKishon Vijay Abraham I 187d5f2e747SRoger QuadrosallOf: 188d5f2e747SRoger Quadros - if: 189d5f2e747SRoger Quadros properties: 190d5f2e747SRoger Quadros compatible: 191d5f2e747SRoger Quadros contains: 192d5f2e747SRoger Quadros const: ti,j7200-wiz-10g 193d5f2e747SRoger Quadros then: 194d5f2e747SRoger Quadros required: 195d5f2e747SRoger Quadros - ti,scm 196d5f2e747SRoger Quadros 1977f464532SRob HerringadditionalProperties: false 1987f464532SRob Herring 199ad044f01SKishon Vijay Abraham Iexamples: 200ad044f01SKishon Vijay Abraham I - | 201ad044f01SKishon Vijay Abraham I #include <dt-bindings/soc/ti,sci_pm_domain.h> 202ad044f01SKishon Vijay Abraham I 203ad044f01SKishon Vijay Abraham I wiz@5000000 { 204ad044f01SKishon Vijay Abraham I compatible = "ti,j721e-wiz-16g"; 205ad044f01SKishon Vijay Abraham I #address-cells = <1>; 206ad044f01SKishon Vijay Abraham I #size-cells = <1>; 207ad044f01SKishon Vijay Abraham I power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>; 208ad044f01SKishon Vijay Abraham I clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>; 209ad044f01SKishon Vijay Abraham I clock-names = "fck", "core_ref_clk", "ext_ref_clk"; 210ad044f01SKishon Vijay Abraham I assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>; 211ad044f01SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>; 212ad044f01SKishon Vijay Abraham I num-lanes = <2>; 213ad044f01SKishon Vijay Abraham I #reset-cells = <1>; 214ad044f01SKishon Vijay Abraham I ranges = <0x5000000 0x5000000 0x10000>; 215ad044f01SKishon Vijay Abraham I 216ad044f01SKishon Vijay Abraham I pll0-refclk { 217ad044f01SKishon Vijay Abraham I clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>; 218ad044f01SKishon Vijay Abraham I #clock-cells = <0>; 219ad044f01SKishon Vijay Abraham I assigned-clocks = <&wiz1_pll0_refclk>; 220ad044f01SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 293 13>; 221ad044f01SKishon Vijay Abraham I }; 222ad044f01SKishon Vijay Abraham I 223ad044f01SKishon Vijay Abraham I pll1-refclk { 224ad044f01SKishon Vijay Abraham I clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>; 225ad044f01SKishon Vijay Abraham I #clock-cells = <0>; 226ad044f01SKishon Vijay Abraham I assigned-clocks = <&wiz1_pll1_refclk>; 227ad044f01SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 293 0>; 228ad044f01SKishon Vijay Abraham I }; 229ad044f01SKishon Vijay Abraham I 230ad044f01SKishon Vijay Abraham I cmn-refclk-dig-div { 231ad044f01SKishon Vijay Abraham I clocks = <&wiz1_refclk_dig>; 232ad044f01SKishon Vijay Abraham I #clock-cells = <0>; 233ad044f01SKishon Vijay Abraham I }; 234ad044f01SKishon Vijay Abraham I 235ad044f01SKishon Vijay Abraham I cmn-refclk1-dig-div { 236ad044f01SKishon Vijay Abraham I clocks = <&wiz1_pll1_refclk>; 237ad044f01SKishon Vijay Abraham I #clock-cells = <0>; 238ad044f01SKishon Vijay Abraham I }; 239ad044f01SKishon Vijay Abraham I 240ad044f01SKishon Vijay Abraham I refclk-dig { 241f516fb70SRob Herring clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, 242f516fb70SRob Herring <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; 243ad044f01SKishon Vijay Abraham I #clock-cells = <0>; 244ad044f01SKishon Vijay Abraham I assigned-clocks = <&wiz0_refclk_dig>; 245ad044f01SKishon Vijay Abraham I assigned-clock-parents = <&k3_clks 292 11>; 246ad044f01SKishon Vijay Abraham I }; 247ad044f01SKishon Vijay Abraham I 248ad044f01SKishon Vijay Abraham I serdes@5000000 { 24928ffe8bfSRob Herring compatible = "ti,sierra-phy-t0"; 250ad044f01SKishon Vijay Abraham I reg-names = "serdes"; 251ad044f01SKishon Vijay Abraham I reg = <0x5000000 0x10000>; 252ad044f01SKishon Vijay Abraham I #address-cells = <1>; 253ad044f01SKishon Vijay Abraham I #size-cells = <0>; 254ad044f01SKishon Vijay Abraham I resets = <&serdes_wiz0 0>; 255ad044f01SKishon Vijay Abraham I reset-names = "sierra_reset"; 256ad044f01SKishon Vijay Abraham I clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>; 257ad044f01SKishon Vijay Abraham I clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div"; 258ad044f01SKishon Vijay Abraham I }; 259ad044f01SKishon Vijay Abraham I }; 260