Lines Matching +full:phy +full:- +full:output +full:- +full:reference +full:- +full:clock

1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP TJA11xx PHY
10   - Andrew Lunn <andrew@lunn.ch>
11   - Florian Fainelli <f.fainelli@gmail.com>
12   - Heiner Kallweit <hkallweit1@gmail.com>
20       - ethernet-phy-id0180.dc40
21       - ethernet-phy-id0180.dc41
22       - ethernet-phy-id0180.dc48
23       - ethernet-phy-id0180.dd00
24       - ethernet-phy-id0180.dd01
25       - ethernet-phy-id0180.dd02
26       - ethernet-phy-id0180.dc80
27       - ethernet-phy-id0180.dc82
28       - ethernet-phy-id001b.b010
29       - ethernet-phy-id001b.b013
30       - ethernet-phy-id001b.b030
31       - ethernet-phy-id001b.b031
34   - $ref: ethernet-phy.yaml#
35   - if:
40               - ethernet-phy-id0180.dc40
41               - ethernet-phy-id0180.dc41
42               - ethernet-phy-id0180.dc48
43               - ethernet-phy-id0180.dd00
44               - ethernet-phy-id0180.dd01
45               - ethernet-phy-id0180.dd02
49         nxp,rmii-refclk-in:
53             in RMII mode. This clock signal is provided by the PHY and is
55             a 50MHz clock signal generated by an external oscillator can be
57             clock to pin CLK_IN_OUT. So, the REF_CLK should be configured
58             as input or output according to the actual circuit connection.
60             interface reference clock input when RMII mode enabled.
62             reference clock output when RMII mode enabled.
65   - if:
70               - ethernet-phy-id001b.b010
71               - ethernet-phy-id001b.b013
72               - ethernet-phy-id001b.b030
73               - ethernet-phy-id001b.b031
77         nxp,rmii-refclk-out:
79           description: Enable 50MHz RMII reference clock output on REF_CLK pin.
82   "^ethernet-phy@[0-9a-f]+$":
86       Some packages have multiple PHYs. Secondary PHY should be defines as
87       subnode of the first (parent) PHY.
94           The ID number for the child PHY. Should be +1 of parent PHY.
97       - reg
102   - |
104         #address-cells = <1>;
105         #size-cells = <0>;
107         tja1101_phy0: ethernet-phy@4 {
108             compatible = "ethernet-phy-id0180.dc40";
110             nxp,rmii-refclk-in;
113   - |
115         #address-cells = <1>;
116         #size-cells = <0>;
118         tja1102_phy0: ethernet-phy@4 {
120             #address-cells = <1>;
121             #size-cells = <0>;
123             tja1102_phy1: ethernet-phy@5 {