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Searched +full:ma35d1 +full:- +full:reset (Results 1 – 10 of 10) sorted by relevance

/linux/Documentation/devicetree/bindings/reset/
H A Dnuvoton,ma35d1-reset.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reset/nuvoton,ma35d1-reset.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton MA35D1 Reset Controller
10 - Chi-Fang Li <cfli0@nuvoton.com>
11 - Jacky Huang <ychuang3@nuvoton.com>
14 The system reset controller can be used to reset various peripheral
15 controllers in MA35D1 SoC.
20 - const: nuvoton,ma35d1-reset
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/linux/arch/arm64/boot/dts/nuvoton/
H A Dma35d1.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 * Author: Shan-Chun Hung <schung@nuvoton.com>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
12 #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
15 compatible = "nuvoton,ma35d1";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
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/linux/Documentation/devicetree/bindings/mmc/
H A Dnuvoton,ma35d1-sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/nuvoton,ma35d1-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton MA35D1 SD/SDIO/MMC Controller
10 - Shan-Chun Hung <shanchun1218@gmail.com>
13 - $ref: sdhci-common.yaml#
18 - nuvoton,ma35d1-sdhci
29 pinctrl-names:
32 - const: default
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/linux/drivers/phy/nuvoton/
H A Dphy-ma35d1-usb2.c1 // SPDX-License-Identifier: GPL-2.0
19 #define PHY0POR BIT(0) /* PHY Power-On Reset Control Bit */
21 #define PHY0COMN BIT(2) /* PHY Common Block Power-Down Control */
36 ret = clk_prepare_enable(p_phy->clk); in ma35_usb_phy_power_on()
38 dev_err(p_phy->dev, "Failed to enable PHY clock: %d\n", ret); in ma35_usb_phy_power_on()
42 regmap_read(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, &val); in ma35_usb_phy_power_on()
48 ret = regmap_read_poll_timeout(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, val, in ma35_usb_phy_power_on()
55 * reset USB PHY0. in ma35_usb_phy_power_on()
58 regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, (PHY0POR | PHY0SUSPEND)); in ma35_usb_phy_power_on()
62 regmap_update_bits(p_phy->sysreg, MA35_SYS_REG_USBPMISCR, 0x7, PHY0SUSPEND); in ma35_usb_phy_power_on()
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/linux/drivers/reset/
H A Dreset-ma35d1.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Chi-Fang Li <cfli0@nuvoton.com>
16 #include <linux/reset-controller.h>
18 #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
24 /* protect registers against concurrent read-modify-write */
135 data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_restart_handler()
146 return -EINVAL; in ma35d1_reset_update()
148 spin_lock_irqsave(&data->lock, flags); in ma35d1_reset_update()
149 reg = readl_relaxed(data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_update()
154 writel_relaxed(reg, data->base + ma35d1_reset_map[id].reg_ofs); in ma35d1_reset_update()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
6 bool "Reset Controller Support"
9 Generic Reset Controller support.
11 This framework is designed to abstract reset handling of devices
12 via GPIOs or SoC-internal reset controller modules.
19 tristate "Altera Arria10 System Resource Reset"
22 This option enables support for the external reset functions for
26 tristate "ASPEED Reset Driver"
30 This enables the reset controller driver for AST2700.
33 bool "AR71xx Reset Driver" if COMPILE_TEST
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-y += core.o
3 obj-y += amlogic/
4 obj-y += hisilicon/
5 obj-y += starfive/
6 obj-y += sti/
7 obj-y += tegra/
8 obj-$(CONFIG_RESET_A10SR) += reset-a10sr.o
9 obj-$(CONFIG_RESET_ASPEED) += reset-aspeed.o
10 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
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/linux/include/dt-bindings/reset/
H A Dnuvoton,ma35d1-reset.h1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
4 * Author: Chi-Fen Li <cfli0@nuvoton.com>
6 * Device Tree binding constants for MA35D1 reset controller.
/linux/drivers/mmc/host/
H A Dsdhci-of-ma35d1.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Author: Shan-Chun Hung <shanchun1218@gmail.com>
16 #include <linux/dma-mapping.h>
28 #include <linux/reset.h>
32 #include "sdhci-pltfm.h"
77 if (likely(!len || (ALIGN(addr, SZ_128M) == ALIGN(addr + len - 1, SZ_128M)))) { in ma35_adma_write_desc()
82 offset = addr & (SZ_128M - 1); in ma35_adma_write_desc()
83 tmplen = SZ_128M - offset; in ma35_adma_write_desc()
87 len -= tmplen; in ma35_adma_write_desc()
115 switch (ios->signal_voltage) { in ma35_start_signal_voltage_switch()
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/linux/drivers/mtd/nand/raw/
H A Dnuvoton-ma35d1-nand-controller.c1 // SPDX-License-Identifier: GPL-2.0
6 #include <linux/dma-mapping.h>
119 return -ERANGE; in ma35_ooblayout_ecc()
121 oob_region->length = chip->ecc.total; in ma35_ooblayout_ecc()
122 oob_region->offset = mtd->oobsize - oob_region->length; in ma35_ooblayout_ecc()
133 return -ERANGE; in ma35_ooblayout_free()
135 oob_region->length = mtd->oobsize - chip->ecc.total - 2; in ma35_ooblayout_free()
136 oob_region->offset = 2; in ma35_ooblayout_free()
152 writel(0xff, nand->regs + MA35_NFI_REG_NANDRA0); in ma35_clear_spare()
158 u32 value = readl(nand->regs + MA35_NFI_REG_NANDRA0 + offset); in read_remaining_bytes()
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