1*db93caa6SShan-Chun Hung# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*db93caa6SShan-Chun Hung%YAML 1.2 3*db93caa6SShan-Chun Hung--- 4*db93caa6SShan-Chun Hung$id: http://devicetree.org/schemas/mmc/nuvoton,ma35d1-sdhci.yaml# 5*db93caa6SShan-Chun Hung$schema: http://devicetree.org/meta-schemas/core.yaml# 6*db93caa6SShan-Chun Hung 7*db93caa6SShan-Chun Hungtitle: Nuvoton MA35D1 SD/SDIO/MMC Controller 8*db93caa6SShan-Chun Hung 9*db93caa6SShan-Chun Hungmaintainers: 10*db93caa6SShan-Chun Hung - Shan-Chun Hung <shanchun1218@gmail.com> 11*db93caa6SShan-Chun Hung 12*db93caa6SShan-Chun HungallOf: 13*db93caa6SShan-Chun Hung - $ref: sdhci-common.yaml# 14*db93caa6SShan-Chun Hung 15*db93caa6SShan-Chun Hungproperties: 16*db93caa6SShan-Chun Hung compatible: 17*db93caa6SShan-Chun Hung enum: 18*db93caa6SShan-Chun Hung - nuvoton,ma35d1-sdhci 19*db93caa6SShan-Chun Hung 20*db93caa6SShan-Chun Hung reg: 21*db93caa6SShan-Chun Hung maxItems: 1 22*db93caa6SShan-Chun Hung 23*db93caa6SShan-Chun Hung interrupts: 24*db93caa6SShan-Chun Hung maxItems: 1 25*db93caa6SShan-Chun Hung 26*db93caa6SShan-Chun Hung clocks: 27*db93caa6SShan-Chun Hung maxItems: 1 28*db93caa6SShan-Chun Hung 29*db93caa6SShan-Chun Hung pinctrl-names: 30*db93caa6SShan-Chun Hung minItems: 1 31*db93caa6SShan-Chun Hung items: 32*db93caa6SShan-Chun Hung - const: default 33*db93caa6SShan-Chun Hung - const: state_uhs 34*db93caa6SShan-Chun Hung 35*db93caa6SShan-Chun Hung pinctrl-0: 36*db93caa6SShan-Chun Hung description: 37*db93caa6SShan-Chun Hung Should contain default/high speed pin ctrl. 38*db93caa6SShan-Chun Hung maxItems: 1 39*db93caa6SShan-Chun Hung 40*db93caa6SShan-Chun Hung pinctrl-1: 41*db93caa6SShan-Chun Hung description: 42*db93caa6SShan-Chun Hung Should contain uhs mode pin ctrl. 43*db93caa6SShan-Chun Hung maxItems: 1 44*db93caa6SShan-Chun Hung 45*db93caa6SShan-Chun Hung resets: 46*db93caa6SShan-Chun Hung maxItems: 1 47*db93caa6SShan-Chun Hung 48*db93caa6SShan-Chun Hung nuvoton,sys: 49*db93caa6SShan-Chun Hung $ref: /schemas/types.yaml#/definitions/phandle 50*db93caa6SShan-Chun Hung description: phandle to access GCR (Global Control Register) registers. 51*db93caa6SShan-Chun Hung 52*db93caa6SShan-Chun Hungrequired: 53*db93caa6SShan-Chun Hung - compatible 54*db93caa6SShan-Chun Hung - reg 55*db93caa6SShan-Chun Hung - interrupts 56*db93caa6SShan-Chun Hung - clocks 57*db93caa6SShan-Chun Hung - pinctrl-names 58*db93caa6SShan-Chun Hung - pinctrl-0 59*db93caa6SShan-Chun Hung - resets 60*db93caa6SShan-Chun Hung - nuvoton,sys 61*db93caa6SShan-Chun Hung 62*db93caa6SShan-Chun HungunevaluatedProperties: false 63*db93caa6SShan-Chun Hung 64*db93caa6SShan-Chun Hungexamples: 65*db93caa6SShan-Chun Hung - | 66*db93caa6SShan-Chun Hung #include <dt-bindings/interrupt-controller/arm-gic.h> 67*db93caa6SShan-Chun Hung #include <dt-bindings/clock/nuvoton,ma35d1-clk.h> 68*db93caa6SShan-Chun Hung #include <dt-bindings/reset/nuvoton,ma35d1-reset.h> 69*db93caa6SShan-Chun Hung 70*db93caa6SShan-Chun Hung soc { 71*db93caa6SShan-Chun Hung #address-cells = <2>; 72*db93caa6SShan-Chun Hung #size-cells = <2>; 73*db93caa6SShan-Chun Hung mmc@40190000 { 74*db93caa6SShan-Chun Hung compatible = "nuvoton,ma35d1-sdhci"; 75*db93caa6SShan-Chun Hung reg = <0x0 0x40190000 0x0 0x2000>; 76*db93caa6SShan-Chun Hung interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 77*db93caa6SShan-Chun Hung clocks = <&clk SDH1_GATE>; 78*db93caa6SShan-Chun Hung pinctrl-names = "default", "state_uhs"; 79*db93caa6SShan-Chun Hung pinctrl-0 = <&pinctrl_sdhci1>; 80*db93caa6SShan-Chun Hung pinctrl-1 = <&pinctrl_sdhci1_uhs>; 81*db93caa6SShan-Chun Hung resets = <&sys MA35D1_RESET_SDH1>; 82*db93caa6SShan-Chun Hung nuvoton,sys = <&sys>; 83*db93caa6SShan-Chun Hung vqmmc-supply = <&sdhci1_vqmmc_regulator>; 84*db93caa6SShan-Chun Hung bus-width = <8>; 85*db93caa6SShan-Chun Hung max-frequency = <200000000>; 86*db93caa6SShan-Chun Hung }; 87*db93caa6SShan-Chun Hung }; 88