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/linux/Documentation/devicetree/bindings/gpio/
H A Dti,keystone-dsp-gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Keystone 2 DSP GPIO controller
10 - Grygorii Strashko <grygorii.strashko@ti.com>
14 the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
15 This is one of the component used by the IPC mechanism used on Keystone SOCs.
17 For example TCI6638K2K SoC has 8 DSP GPIO controllers:
18 - 8 for C66x CorePacx CPUs 0-7
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H A Dgpio-davinci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controller for Davinci and keystone devices
10 - Keerthy <j-keerthy@ti.com>
15 - items:
16 - enum:
17 - ti,k2g-gpio
18 - ti,am654-gpio
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/linux/arch/arm/boot/dts/ti/keystone/
H A Dkeystone-k2hk.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Kepler/Hawking soc specific device tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
11 compatible = "ti,k2hk", "ti,keystone";
12 model = "Texas Instruments Keystone 2 Kepler/Hawking SoC";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a15";
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H A Dkeystone.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/gpio/gpio.h>
10 compatible = "ti,keystone";
11 model = "Texas Instruments Keystone 2 SoC";
12 #address-cells = <2>;
13 #size-cells = <2>;
14 interrupt-parent = <&gic>;
30 gic: interrupt-controller@2561000 {
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H A Dkeystone-k2g.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/keystone.h>
10 #include <dt-bindings/gpio/gpio.h>
13 compatible = "ti,k2g","ti,keystone";
15 #address-cells = <2>;
16 #size-cells = <2>;
17 interrupt-parent = <&gic>;
32 #address-cells = <1>;
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H A Dkeystone-k2l.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Lamarr SoC specific device tree
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
11 compatible = "ti,k2l", "ti,keystone";
12 model = "Texas Instruments Keystone 2 Lamarr SoC";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a15";
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H A Dkeystone-k2e.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Edison soc device tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/reset/ti-syscon.h>
11 compatible = "ti,k2e", "ti,keystone";
12 model = "Texas Instruments Keystone 2 Edison SoC";
15 #address-cells = <1>;
16 #size-cells = <0>;
18 interrupt-parent = <&gic>;
21 compatible = "arm,cortex-a15";
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H A Dkeystone-k2hk-evm.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Keystone 2 Kepler/Hawking EVM device tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
9 #include "keystone.dtsi"
10 #include "keystone-k2hk.dtsi"
13 compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone";
14 model = "Texas Instruments Keystone 2 Kepler/Hawking EVM";
16 reserved-memory {
17 #address-cells = <2>;
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H A Dkeystone-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for Keystone 2 clock tree
5 * Copyright (C) 2013-2017 Texas Instruments Incorporated - https://www.ti.com/
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #clock-cells = <0>;
15 compatible = "ti,keystone,pll-mux-clock";
18 bit-shift = <23>;
19 bit-mask = <1>;
20 clock-output-names = "mainmuxclk";
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H A Dkeystone-k2g-ice.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
7 /dts-v1/;
9 #include "keystone-k2g.dtsi"
10 #include <dt-bindings/net/ti-dp83867.h>
13 compatible = "ti,k2g-ice", "ti,k2g", "ti,keystone";
21 reserved-memory {
22 #address-cells = <2>;
23 #size-cells = <2>;
26 dsp_common_memory: dsp-common-memory@81f800000 {
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,keystone-rproc.txt1 TI Keystone DSP devices
4 The TI Keystone 2 family of SoCs usually have one or more (upto 8) TI DSP Core
5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
11 Keystone 2 SoCs is usually a TMS320C66x CorePac processor.
15 Each DSP Core sub-system is represented as a single DT node, and should also
22 --------------------
25 - compatible: Should be one of the following,
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
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/linux/Documentation/devicetree/bindings/spi/
H A Dspi-davinci.txt4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
/linux/drivers/usb/phy/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
32 tristate "Keystone USB PHY Driver"
36 Enable this to support Keystone USB phy. This driver provides
38 of the Keystone SOC.
42 depends on USB_GADGET || !USB_GADGET # if USB_GADGET=m, NOP can't be built-in
46 built-in with usb ip or which are autonomous and doesn't require any
73 The definition of internal PHY APIs are in the mach-omap2 layer.
76 tristate "GPIO based peripheral-only VBUS sensing 'transceiver'"
82 Provides simple GPIO VBUS sensing for controllers with an
84 optionally control of a D+ pullup GPIO as well as a VBUS
[all …]
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
5 obj-$(CONFIG_USB_PHY) += phy.o
6 obj-$(CONFIG_OF) += of.o
10 obj-$(CONFIG_AB8500_USB) += phy-ab8500-usb.o
11 obj-$(CONFIG_FSL_USB2_OTG) += phy-fsl-usb.o
12 obj-$(CONFIG_NOP_USB_XCEIV) += phy-generic.o
13 obj-$(CONFIG_TAHVO_USB) += phy-tahvo.o
14 obj-$(CONFIG_AM335X_CONTROL_USB) += phy-am335x-control.o
15 obj-$(CONFIG_AM335X_PHY_USB) += phy-am335x.o
16 obj-$(CONFIG_OMAP_OTG) += phy-omap-otg.o
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/linux/drivers/gpio/
H A Dgpio-syscon.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SYSCON GPIO driver
9 #include <linux/gpio/driver.h>
20 /* SYSCON driver is designed to use 32-bit wide registers */
25 * struct syscon_gpio_data - Configuration for the device.
31 * @dat_bit_offset: Offset (in bits) to the first GPIO bit.
33 * GPIO direction (Used with GPIO_SYSCON_FEAT_DIR flag).
61 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; in syscon_gpio_get()
63 ret = regmap_read(priv->syscon, in syscon_gpio_get()
76 offs = priv->dreg_offset + priv->data->dat_bit_offset + offset; in syscon_gpio_set()
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H A Dgpio-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * TI DaVinci GPIO Support
5 * Copyright (c) 2006-2007 David Brownell
9 #include <linux/gpio/driver.h>
43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
57 /* Serialize access to GPIO registers */
66 static inline u32 __gpio_mask(unsigned gpio) in __gpio_mask() argument
68 return 1 << (gpio % 32); in __gpio_mask()
73 /*--------------------------------------------------------------------------*/
75 /* board setup code *MUST* setup pinmux and enable the GPIO clock. */
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # GPIO infrastructure and drivers
10 bool "GPIO Support"
12 This enables GPIO support through the generic GPIO library.
14 one or more of the GPIO drivers below.
50 this symbol, but new drivers should use the generic gpio-regmap
54 bool "Debug GPIO calls"
57 Say Y here to add some extra checks and diagnostics to GPIO calls.
60 non-sleeping contexts. They can make bitbanged serial protocols
65 bool "/sys/class/gpio/... (sysfs interface)" if EXPERT
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/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-wakeup.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
9 dmsc: system-controller@44083000 {
10 compatible = "ti,am654-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
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H A Dk3-am64-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
15 compatible = "ti,am654-timer";
18 clock-names = "fck";
19 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>;
20 ti,timer-pwm;
25 compatible = "ti,am654-timer";
28 clock-names = "fck";
29 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>;
30 ti,timer-pwm;
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H A Dk3-am62-mcu.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
10 bootph-all;
11 compatible = "pinctrl-single";
13 #pinctrl-cells = <1>;
14 pinctrl-single,register-width = <32>;
15 pinctrl-single,function-mask = <0xffffffff>;
19 bootph-pre-ram;
20 compatible = "ti,j721e-esm";
23 ti,esm-pins = <0>, <1>, <2>, <85>;
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H A Dk3-am65-main.dtsi1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
5 * Copyright (C) 2016-2024 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy-am654-serdes.h>
11 compatible = "mmio-sram";
13 #address-cells = <1>;
14 #size-cells = <1>;
17 atf-sram@0 {
21 sysfw-sram@f0000 {
25 l3cache-sram@100000 {
30 gic500: interrupt-controller@1800000 {
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/linux/drivers/i2c/busses/
H A Di2c-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 * ----------------------------------------------------------------------------
12 * ----------------------------------------------------------------------------
20 #include <linux/gpio/consumer.h>
32 /* ----- global defines ----------------------------------------------- */
94 /* set SDA and SCL as GPIO */
97 /* set SCL as output when used as GPIO*/
99 /* set SDA as output when used as GPIO*/
102 /* read SCL GPIO level */
104 /* read SDA GPIO level */
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/linux/drivers/pci/controller/dwc/
H A Dpci-keystone.c1 // SPDX-License-Identifier: GPL-2.0
3 * PCIe host controller driver for Texas Instruments Keystone SoCs
5 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
8 * Author: Murali Karicheri <m-karicheri2@ti.com>
9 * Implementation based on pci-exynos.c and pcie-designware.c
14 #include <linux/gpio/consumer.h>
31 #include "pcie-designware.h"
59 #define PCIE_LEGACY_IRQ_ENABLE_SET(n) (0x188 + (0x10 * ((n) - 1)))
60 #define PCIE_LEGACY_IRQ_ENABLE_CLR(n) (0x18c + (0x10 * ((n) - 1)))
84 #define ERR_NONFATAL BIT(2) /* Non-fatal error */
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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dti,sci-intr.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lokesh Vutla <lokeshvutla@ti.com>
13 - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
22 +----------------------+
24 +-------+ | +------+ +-----+ |
25 | GPIO |----------->| | irq0 | | 0 | | Host IRQ
26 +-------+ | +------+ +-----+ | controller
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/linux/drivers/spi/
H A Dspi-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/consumer.h>
16 #include <linux/dma-mapping.h>
22 #include <linux/platform_data/spi-davinci.h>
136 if (dspi->rx) { in davinci_spi_rx_buf_u8()
137 u8 *rx = dspi->rx; in davinci_spi_rx_buf_u8()
139 dspi->rx = rx; in davinci_spi_rx_buf_u8()
145 if (dspi->rx) { in davinci_spi_rx_buf_u16()
146 u16 *rx = dspi->rx; in davinci_spi_rx_buf_u16()
148 dspi->rx = rx; in davinci_spi_rx_buf_u16()
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