xref: /linux/Documentation/devicetree/bindings/gpio/ti,keystone-dsp-gpio.yaml (revision fcb117e0758d1462128a50c5788555e03b48833b) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Keystone 2 DSP GPIO controller
8
9maintainers:
10  - Grygorii Strashko <grygorii.strashko@ti.com>
11
12description: |
13  HOST OS userland running on ARM can send interrupts to DSP cores using
14  the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core.
15  This is one of the component used by the IPC mechanism used on Keystone SOCs.
16
17  For example TCI6638K2K SoC has 8 DSP GPIO controllers:
18   - 8 for C66x CorePacx CPUs 0-7
19
20  Keystone 2 DSP GPIO controller has specific features:
21  - each GPIO can be configured only as output pin;
22  - setting GPIO value to 1 causes IRQ generation on target DSP core;
23  - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still
24    pending.
25
26properties:
27  compatible:
28    const: ti,keystone-dsp-gpio
29
30  reg:
31    maxItems: 1
32
33  gpio-controller: true
34
35  '#gpio-cells':
36    const: 2
37
38  gpio,syscon-dev:
39    description:
40      Phandle and offset of device's specific registers within the syscon state
41      control registers
42    $ref: /schemas/types.yaml#/definitions/phandle-array
43    items:
44      - items:
45          - description: phandle to syscon
46          - description: register offset within state control registers
47
48required:
49  - compatible
50  - reg
51  - gpio-controller
52  - '#gpio-cells'
53  - gpio,syscon-dev
54
55additionalProperties: false
56
57examples:
58  - |
59    gpio@240 {
60        compatible = "ti,keystone-dsp-gpio";
61        reg = <0x240 0x4>;
62        gpio-controller;
63        #gpio-cells = <2>;
64        gpio,syscon-dev = <&devctrl 0x240>;
65    };
66