1*aff0a170SRob Herring (Arm)# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*aff0a170SRob Herring (Arm)%YAML 1.2 3*aff0a170SRob Herring (Arm)--- 4*aff0a170SRob Herring (Arm)$id: http://devicetree.org/schemas/gpio/ti,keystone-dsp-gpio.yaml# 5*aff0a170SRob Herring (Arm)$schema: http://devicetree.org/meta-schemas/core.yaml# 6*aff0a170SRob Herring (Arm) 7*aff0a170SRob Herring (Arm)title: Keystone 2 DSP GPIO controller 8*aff0a170SRob Herring (Arm) 9*aff0a170SRob Herring (Arm)maintainers: 10*aff0a170SRob Herring (Arm) - Grygorii Strashko <grygorii.strashko@ti.com> 11*aff0a170SRob Herring (Arm) 12*aff0a170SRob Herring (Arm)description: | 13*aff0a170SRob Herring (Arm) HOST OS userland running on ARM can send interrupts to DSP cores using 14*aff0a170SRob Herring (Arm) the DSP GPIO controller IP. It provides 28 IRQ signals per each DSP core. 15*aff0a170SRob Herring (Arm) This is one of the component used by the IPC mechanism used on Keystone SOCs. 16*aff0a170SRob Herring (Arm) 17*aff0a170SRob Herring (Arm) For example TCI6638K2K SoC has 8 DSP GPIO controllers: 18*aff0a170SRob Herring (Arm) - 8 for C66x CorePacx CPUs 0-7 19*aff0a170SRob Herring (Arm) 20*aff0a170SRob Herring (Arm) Keystone 2 DSP GPIO controller has specific features: 21*aff0a170SRob Herring (Arm) - each GPIO can be configured only as output pin; 22*aff0a170SRob Herring (Arm) - setting GPIO value to 1 causes IRQ generation on target DSP core; 23*aff0a170SRob Herring (Arm) - reading pin value returns 0 - if IRQ was handled or 1 - IRQ is still 24*aff0a170SRob Herring (Arm) pending. 25*aff0a170SRob Herring (Arm) 26*aff0a170SRob Herring (Arm)properties: 27*aff0a170SRob Herring (Arm) compatible: 28*aff0a170SRob Herring (Arm) const: ti,keystone-dsp-gpio 29*aff0a170SRob Herring (Arm) 30*aff0a170SRob Herring (Arm) reg: 31*aff0a170SRob Herring (Arm) maxItems: 1 32*aff0a170SRob Herring (Arm) 33*aff0a170SRob Herring (Arm) gpio-controller: true 34*aff0a170SRob Herring (Arm) 35*aff0a170SRob Herring (Arm) '#gpio-cells': 36*aff0a170SRob Herring (Arm) const: 2 37*aff0a170SRob Herring (Arm) 38*aff0a170SRob Herring (Arm) gpio,syscon-dev: 39*aff0a170SRob Herring (Arm) description: 40*aff0a170SRob Herring (Arm) Phandle and offset of device's specific registers within the syscon state 41*aff0a170SRob Herring (Arm) control registers 42*aff0a170SRob Herring (Arm) $ref: /schemas/types.yaml#/definitions/phandle-array 43*aff0a170SRob Herring (Arm) items: 44*aff0a170SRob Herring (Arm) - items: 45*aff0a170SRob Herring (Arm) - description: phandle to syscon 46*aff0a170SRob Herring (Arm) - description: register offset within state control registers 47*aff0a170SRob Herring (Arm) 48*aff0a170SRob Herring (Arm)required: 49*aff0a170SRob Herring (Arm) - compatible 50*aff0a170SRob Herring (Arm) - reg 51*aff0a170SRob Herring (Arm) - gpio-controller 52*aff0a170SRob Herring (Arm) - '#gpio-cells' 53*aff0a170SRob Herring (Arm) - gpio,syscon-dev 54*aff0a170SRob Herring (Arm) 55*aff0a170SRob Herring (Arm)additionalProperties: false 56*aff0a170SRob Herring (Arm) 57*aff0a170SRob Herring (Arm)examples: 58*aff0a170SRob Herring (Arm) - | 59*aff0a170SRob Herring (Arm) gpio@240 { 60*aff0a170SRob Herring (Arm) compatible = "ti,keystone-dsp-gpio"; 61*aff0a170SRob Herring (Arm) reg = <0x240 0x4>; 62*aff0a170SRob Herring (Arm) gpio-controller; 63*aff0a170SRob Herring (Arm) #gpio-cells = <2>; 64*aff0a170SRob Herring (Arm) gpio,syscon-dev = <&devctrl 0x240>; 65*aff0a170SRob Herring (Arm) }; 66