1b8713af8SLokesh Vutla# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2b8713af8SLokesh Vutla%YAML 1.2 3b8713af8SLokesh Vutla--- 4b8713af8SLokesh Vutla$id: http://devicetree.org/schemas/interrupt-controller/ti,sci-intr.yaml# 5b8713af8SLokesh Vutla$schema: http://devicetree.org/meta-schemas/core.yaml# 6b8713af8SLokesh Vutla 7b8713af8SLokesh Vutlatitle: Texas Instruments K3 Interrupt Router 8b8713af8SLokesh Vutla 9b8713af8SLokesh Vutlamaintainers: 10b8713af8SLokesh Vutla - Lokesh Vutla <lokeshvutla@ti.com> 11b8713af8SLokesh Vutla 12b8713af8SLokesh VutlaallOf: 13b8713af8SLokesh Vutla - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml# 14b8713af8SLokesh Vutla 15b8713af8SLokesh Vutladescription: | 16b8713af8SLokesh Vutla The Interrupt Router (INTR) module provides a mechanism to mux M 17b8713af8SLokesh Vutla interrupt inputs to N interrupt outputs, where all M inputs are selectable 18b8713af8SLokesh Vutla to be driven per N output. An Interrupt Router can either handle edge 19b8713af8SLokesh Vutla triggered or level triggered interrupts and that is fixed in hardware. 20b8713af8SLokesh Vutla 21b8713af8SLokesh Vutla Interrupt Router 22b8713af8SLokesh Vutla +----------------------+ 23b8713af8SLokesh Vutla | Inputs Outputs | 24b8713af8SLokesh Vutla +-------+ | +------+ +-----+ | 25b8713af8SLokesh Vutla | GPIO |----------->| | irq0 | | 0 | | Host IRQ 26b8713af8SLokesh Vutla +-------+ | +------+ +-----+ | controller 27b8713af8SLokesh Vutla | . . | +-------+ 28b8713af8SLokesh Vutla +-------+ | . . |----->| IRQ | 29b8713af8SLokesh Vutla | INTA |----------->| . . | +-------+ 30b8713af8SLokesh Vutla +-------+ | . +-----+ | 31b8713af8SLokesh Vutla | +------+ | N | | 32b8713af8SLokesh Vutla | | irqM | +-----+ | 33b8713af8SLokesh Vutla | +------+ | 34b8713af8SLokesh Vutla | | 35b8713af8SLokesh Vutla +----------------------+ 36b8713af8SLokesh Vutla 37b8713af8SLokesh Vutla There is one register per output (MUXCNTL_N) that controls the selection. 38b8713af8SLokesh Vutla Configuration of these MUXCNTL_N registers is done by a system controller 39b8713af8SLokesh Vutla (like the Device Memory and Security Controller on K3 AM654 SoC). System 40b8713af8SLokesh Vutla controller will keep track of the used and unused registers within the Router. 41b8713af8SLokesh Vutla Driver should request the system controller to get the range of GIC IRQs 42b8713af8SLokesh Vutla assigned to the requesting hosts. It is the drivers responsibility to keep 43b8713af8SLokesh Vutla track of Host IRQs. 44b8713af8SLokesh Vutla 45b8713af8SLokesh Vutla Communication between the host processor running an OS and the system 46b8713af8SLokesh Vutla controller happens through a protocol called TI System Control Interface 47b8713af8SLokesh Vutla (TISCI protocol). 48b8713af8SLokesh Vutla 49b8713af8SLokesh Vutlaproperties: 50b8713af8SLokesh Vutla compatible: 51b8713af8SLokesh Vutla const: ti,sci-intr 52b8713af8SLokesh Vutla 53b8713af8SLokesh Vutla ti,intr-trigger-type: 54b8713af8SLokesh Vutla $ref: /schemas/types.yaml#/definitions/uint32 55b8713af8SLokesh Vutla enum: [1, 4] 56b8713af8SLokesh Vutla description: | 57b8713af8SLokesh Vutla Should be one of the following. 58b8713af8SLokesh Vutla 1 = If intr supports edge triggered interrupts. 59b8713af8SLokesh Vutla 4 = If intr supports level triggered interrupts. 60b8713af8SLokesh Vutla 61*daa0b6d0SApurva Nandan reg: 62*daa0b6d0SApurva Nandan maxItems: 1 63*daa0b6d0SApurva Nandan 64b8713af8SLokesh Vutla interrupt-controller: true 65b8713af8SLokesh Vutla 66b8713af8SLokesh Vutla '#interrupt-cells': 67b8713af8SLokesh Vutla const: 1 68b8713af8SLokesh Vutla description: | 69b8713af8SLokesh Vutla The 1st cell should contain interrupt router input hw number. 70b8713af8SLokesh Vutla 71b8713af8SLokesh Vutla ti,interrupt-ranges: 72b8713af8SLokesh Vutla $ref: /schemas/types.yaml#/definitions/uint32-matrix 73b8713af8SLokesh Vutla description: | 74b8713af8SLokesh Vutla Interrupt ranges that converts the INTR output hw irq numbers 75b8713af8SLokesh Vutla to parents's input interrupt numbers. 76b8713af8SLokesh Vutla items: 77b8713af8SLokesh Vutla items: 78b8713af8SLokesh Vutla - description: | 79b8713af8SLokesh Vutla "output_irq" specifies the base for intr output irq 80b8713af8SLokesh Vutla - description: | 81b8713af8SLokesh Vutla "parent's input irq" specifies the base for parent irq 82b8713af8SLokesh Vutla - description: | 83b8713af8SLokesh Vutla "limit" specifies the limit for translation 84b8713af8SLokesh Vutla 85b8713af8SLokesh Vutlarequired: 86b8713af8SLokesh Vutla - compatible 87b8713af8SLokesh Vutla - ti,intr-trigger-type 88b8713af8SLokesh Vutla - interrupt-controller 89b8713af8SLokesh Vutla - '#interrupt-cells' 90b8713af8SLokesh Vutla - ti,sci 91b8713af8SLokesh Vutla - ti,sci-dev-id 92b8713af8SLokesh Vutla - ti,interrupt-ranges 93b8713af8SLokesh Vutla 94f84e2c5cSRob HerringunevaluatedProperties: false 95f84e2c5cSRob Herring 96b8713af8SLokesh Vutlaexamples: 97b8713af8SLokesh Vutla - | 98b8713af8SLokesh Vutla main_gpio_intr: interrupt-controller0 { 99b8713af8SLokesh Vutla compatible = "ti,sci-intr"; 100b8713af8SLokesh Vutla ti,intr-trigger-type = <1>; 101b8713af8SLokesh Vutla interrupt-controller; 102b8713af8SLokesh Vutla interrupt-parent = <&gic500>; 103b8713af8SLokesh Vutla #interrupt-cells = <1>; 104b8713af8SLokesh Vutla ti,sci = <&dmsc>; 105b8713af8SLokesh Vutla ti,sci-dev-id = <131>; 106b8713af8SLokesh Vutla ti,interrupt-ranges = <0 360 32>; 107b8713af8SLokesh Vutla }; 108