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/linux/drivers/phy/starfive/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 tristate "StarFive JH7110 D-PHY RX support"
14 Choose this option if you have a StarFive D-PHY in your
16 phy-jh7110-dphy-rx.ko.
19 tristate "StarFive JH7110 D-PHY TX Support"
24 Choose this option if you have a StarFive D-PHY TX in your
26 phy-jh7110-dphy-tx.ko.
29 tristate "Starfive JH7110 PCIE 2.0/USB 3.0 PHY support"
34 or used as USB 3.0 PHY.
36 phy-jh7110-pcie.ko.
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H A Dphy-jh7110-usb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 USB 2.0 PHY driver
18 #include <linux/usb/of.h>
40 /* Host mode enable the LS speed keep-alive signal */ in usb2_set_ls_keepalive()
41 val = readl(phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
47 writel(val, phy->regs + USB_LS_KEEPALIVE_OFF); in usb2_set_ls_keepalive()
61 return -EINVAL; in usb2_phy_set_mode()
64 if (mode != phy->mode) { in usb2_phy_set_mode()
65 dev_dbg(&_phy->dev, "Changing phy to %d\n", mode); in usb2_phy_set_mode()
66 phy->mode = mode; in usb2_phy_set_mode()
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H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_RX) += phy-jh7110-dphy-rx.o
3 obj-$(CONFIG_PHY_STARFIVE_JH7110_DPHY_TX) += phy-jh7110-dphy-tx.o
4 obj-$(CONFIG_PHY_STARFIVE_JH7110_PCIE) += phy-jh7110-pcie.o
5 obj-$(CONFIG_PHY_STARFIVE_JH7110_USB) += phy-jh7110-usb.o
H A Dphy-jh7110-pcie.c1 // SPDX-License-Identifier: GPL-2.0+
3 * StarFive JH7110 PCIe 2.0 PHY driver
49 if (!data->stg_syscon || !data->sys_syscon) { in phy_usb3_mode_set()
50 dev_err(&data->phy->dev, "doesn't support usb3 mode\n"); in phy_usb3_mode_set()
51 return -EINVAL; in phy_usb3_mode_set()
54 regmap_update_bits(data->stg_syscon, data->stg_pcie_mode, in phy_usb3_mode_set()
56 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
58 regmap_update_bits(data->stg_syscon, data->stg_pcie_usb, in phy_usb3_mode_set()
61 /* Connect usb 3.0 phy mode */ in phy_usb3_mode_set()
62 regmap_update_bits(data->sys_syscon, data->sys_phy_connect, in phy_usb3_mode_set()
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/linux/Documentation/devicetree/bindings/phy/
H A Dstarfive,jh7110-usb-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 USB 2.0 PHY
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb-phy
19 "#phy-cells":
24 - description: PHY 125m
25 - description: app 125m
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H A Dstarfive,jh7110-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/starfive,jh7110-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 PCIe 2.0 PHY
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-pcie-phy
19 "#phy-cells":
22 starfive,sys-syscon:
23 $ref: /schemas/types.yaml#/definitions/phandle-array
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/linux/Documentation/devicetree/bindings/usb/
H A Dstarfive,jh7110-usb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb
18 starfive,stg-syscon:
19 $ref: /schemas/types.yaml#/definitions/phandle-array
21 - items:
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/linux/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-stgcrg.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 System-Top-Group Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-stgcrg
21 - description: Main Oscillator (24 MHz)
22 - description: HIFI4 core
23 - description: STG AXI/AHB
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/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 #include <dt-bindings/thermal/thermal.h>
14 compatible = "starfive,jh7110";
15 #address-cells = <2>;
16 #size-cells = <2>;
19 #address-cells = <1>;
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/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-stg.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 System-Top-Group Clock Driver
9 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/starfive,jh7110-crg.h>
15 #include "clk-starfive-jh7110.h"
32 /* usb */
40 /* pci-e */
81 unsigned int idx = clkspec->args[0]; in jh7110_stgclk_get()
84 return &priv->reg[idx].hw; in jh7110_stgclk_get()
86 return ERR_PTR(-EINVAL); in jh7110_stgclk_get()
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H A Dclk-starfive-jh7110-pll.c1 // SPDX-License-Identifier: GPL-2.0
3 * StarFive JH7110 PLL Clock Generator Driver
8 * This driver is about to register JH7110 PLL clock generator and support ops.
9 * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
17 * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
22 #include <linux/clk-provider.h>
30 #include <dt-bindings/clock/starfive,jh7110-crg.h>
158 * PLL0 frequency should be multiple of 125MHz (USB frequency).
275 return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]); in jh7110_pll_priv_from()
284 regmap_read(regmap, info->offsets.pd, &val); in jh7110_pll_regvals_get()
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/linux/drivers/usb/cdns3/
H A DKconfig2 tristate "Cadence USB Support"
3 depends on USB_SUPPORT && (USB || USB_GADGET) && HAS_DMA
8 dual-role controller.
9 It supports: dual-role switch, Host-only, and Peripheral-only.
17 tristate "Cadence USB3 Dual-Role Controller"
20 Say Y here if your system has a Cadence USB3 dual-role controller.
21 It supports: dual-role switch, Host-only, and Peripheral-only.
34 Cadence USBSS-DEV driver.
41 depends on USB=y || USB=USB_CDNS3
51 tristate "Cadence USB3 support on PCIe-based platforms"
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/linux/drivers/mmc/host/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
94 implements a hardware byte swapper using a 32-bit datum.
106 support UHS2-capable devices.
133 disabled, it will steal the MMC cards away - rendering them
505 MOXA provides one multi-functional card reader which can
506 be found on some embedded hardware such as UC-7112-LX.
557 of Alcor Micro PCI-E card reader
701 tristate "DMA for SDHI SD/SDIO controllers using SYS-DMAC"
706 using SYS-DMAC via DMA Engine. This supports the controllers
710 tristate "DMA for SDHI SD/SDIO controllers using on-chip bus mastering"
[all …]
/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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/linux/drivers/watchdog/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
16 on-line as fast as possible after a lock-up. There's both a watchdog
21 <file:Documentation/watchdog/watchdog-api.rst> in the kernel source.
51 bool "Update boot-enabled watchdog until userspace takes over"
77 bool "Enable watchdog hrtimer-based pretimeouts"
198 tristate "ChromeOS EC-based watchdog"
252 tristate "Watchdog device controlled through GPIO-line"
257 controlled through GPIO-line.
280 will be called lenovo-se10-wdt.
394 module will be called mlx-wdt.
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