Lines Matching +full:jh7110 +full:- +full:usb

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/starfive,jh7110-usb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 wrapper module for the Cadence USBSS-DRD controller
10 - Minda Chen <minda.chen@starfivetech.com>
14 const: starfive,jh7110-usb
18 starfive,stg-syscon:
19 $ref: /schemas/types.yaml#/definitions/phandle-array
21 - items:
22 - description: phandle to System Register Controller stg_syscon node.
23 - description: dr mode register offset of STG_SYSCONSAIF__SYSCFG register for USB.
26 of STG_SYSCONSAIF__SYSCFG register for USB.
31 "#address-cells":
34 "#size-cells":
39 - description: link power management clock
40 - description: standby clock
41 - description: APB clock
42 - description: AXI clock
43 - description: UTMI APB clock
45 clock-names:
47 - const: lpm
48 - const: stb
49 - const: apb
50 - const: axi
51 - const: utmi_apb
55 - description: Power up reset
56 - description: APB clock reset
57 - description: AXI clock reset
58 - description: UTMI APB clock reset
60 reset-names:
62 - const: pwrup
63 - const: apb
64 - const: axi
65 - const: utmi_apb
68 "^usb@[0-9a-f]+$":
73 - compatible
74 - ranges
75 - starfive,stg-syscon
76 - '#address-cells'
77 - '#size-cells'
78 - dr_mode
79 - clocks
80 - resets
85 - |
86 usb@10100000 {
87 compatible = "starfive,jh7110-usb";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 starfive,stg-syscon = <&stg_syscon 0x4>;
97 clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
102 reset-names = "pwrup", "apb", "axi", "utmi_apb";
105 usb@0 {
110 reg-names = "otg", "xhci", "dev";
112 interrupt-names = "host", "peripheral", "otg";
113 maximum-speed = "super-speed";