1 // SPDX-License-Identifier: GPL-2.0
3  * StarFive JH7110 PLL Clock Generator Driver
8  * This driver is about to register JH7110 PLL clock generator and support ops.
9  * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
17  * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
22 #include <linux/clk-provider.h>
30 #include <dt-bindings/clock/starfive,jh7110-crg.h>
158  * PLL0 frequency should be multiple of 125MHz (USB frequency).
275 	return container_of(pll, struct jh7110_pll_priv, pll[pll->idx]);  in jh7110_pll_priv_from()
284 	regmap_read(regmap, info->offsets.pd, &val);  in jh7110_pll_regvals_get()
285 	ret->dacpd = (val & info->masks.dacpd) >> info->shifts.dacpd;  in jh7110_pll_regvals_get()
286 	ret->dsmpd = (val & info->masks.dsmpd) >> info->shifts.dsmpd;  in jh7110_pll_regvals_get()
288 	regmap_read(regmap, info->offsets.fbdiv, &val);  in jh7110_pll_regvals_get()
289 	ret->fbdiv = (val & info->masks.fbdiv) >> info->shifts.fbdiv;  in jh7110_pll_regvals_get()
291 	regmap_read(regmap, info->offsets.frac, &val);  in jh7110_pll_regvals_get()
292 	ret->frac = (val & JH7110_PLL_FRAC_MASK) >> JH7110_PLL_FRAC_SHIFT;  in jh7110_pll_regvals_get()
293 	ret->postdiv1 = (val & JH7110_PLL_POSTDIV1_MASK) >> JH7110_PLL_POSTDIV1_SHIFT;  in jh7110_pll_regvals_get()
295 	regmap_read(regmap, info->offsets.prediv, &val);  in jh7110_pll_regvals_get()
296 	ret->prediv = (val & JH7110_PLL_PREDIV_MASK) >> JH7110_PLL_PREDIV_SHIFT;  in jh7110_pll_regvals_get()
306 	jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);  in jh7110_pll_recalc_rate()
331 	const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];  in jh7110_pll_determine_rate()
332 	const struct jh7110_pll_preset *selected = &info->presets[0];  in jh7110_pll_determine_rate()
336 	if (req->best_parent_rate != JH7110_PLL_OSC_RATE) {  in jh7110_pll_determine_rate()
337 		req->rate = jh7110_pll_recalc_rate(hw, req->best_parent_rate);  in jh7110_pll_determine_rate()
342 	for (idx = 1; idx < info->npresets; idx++) {  in jh7110_pll_determine_rate()
343 		const struct jh7110_pll_preset *val = &info->presets[idx];  in jh7110_pll_determine_rate()
345 		if (req->rate < val->freq)  in jh7110_pll_determine_rate()
351 	req->rate = selected->freq;  in jh7110_pll_determine_rate()
360 	const struct jh7110_pll_info *info = &jh7110_plls[pll->idx];  in jh7110_pll_set_rate()
366 		return -EINVAL;  in jh7110_pll_set_rate()
368 	for (idx = 0, val = &info->presets[0]; idx < info->npresets; idx++, val++) {  in jh7110_pll_set_rate()
369 		if (val->freq == rate)  in jh7110_pll_set_rate()
372 	return -EINVAL;  in jh7110_pll_set_rate()
375 	if (val->mode == JH7110_PLL_MODE_FRACTION)  in jh7110_pll_set_rate()
376 		regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_FRAC_MASK,  in jh7110_pll_set_rate()
377 				   val->frac << JH7110_PLL_FRAC_SHIFT);  in jh7110_pll_set_rate()
379 	regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dacpd,  in jh7110_pll_set_rate()
380 			   (u32)val->mode << info->shifts.dacpd);  in jh7110_pll_set_rate()
381 	regmap_update_bits(priv->regmap, info->offsets.pd, info->masks.dsmpd,  in jh7110_pll_set_rate()
382 			   (u32)val->mode << info->shifts.dsmpd);  in jh7110_pll_set_rate()
383 	regmap_update_bits(priv->regmap, info->offsets.prediv, JH7110_PLL_PREDIV_MASK,  in jh7110_pll_set_rate()
384 			   (u32)val->prediv << JH7110_PLL_PREDIV_SHIFT);  in jh7110_pll_set_rate()
385 	regmap_update_bits(priv->regmap, info->offsets.fbdiv, info->masks.fbdiv,  in jh7110_pll_set_rate()
386 			   val->fbdiv << info->shifts.fbdiv);  in jh7110_pll_set_rate()
387 	regmap_update_bits(priv->regmap, info->offsets.frac, JH7110_PLL_POSTDIV1_MASK,  in jh7110_pll_set_rate()
388 			   (u32)val->postdiv1 << JH7110_PLL_POSTDIV1_SHIFT);  in jh7110_pll_set_rate()
396 	struct jh7110_pll_data *pll = s->private;  in jh7110_pll_registers_read()
400 	jh7110_pll_regvals_get(priv->regmap, &jh7110_plls[pll->idx], &val);  in jh7110_pll_registers_read()
416 	return single_open(f, jh7110_pll_registers_read, inode->i_private);  in jh7110_pll_registers_open()
448 	unsigned int idx = clkspec->args[0];  in jh7110_pll_get()
451 		return &priv->pll[idx].hw;  in jh7110_pll_get()
453 	return ERR_PTR(-EINVAL);  in jh7110_pll_get()
462 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);  in jh7110_pll_probe()
464 		return -ENOMEM;  in jh7110_pll_probe()
466 	priv->dev = &pdev->dev;  in jh7110_pll_probe()
467 	priv->regmap = syscon_node_to_regmap(priv->dev->of_node->parent);  in jh7110_pll_probe()
468 	if (IS_ERR(priv->regmap))  in jh7110_pll_probe()
469 		return PTR_ERR(priv->regmap);  in jh7110_pll_probe()
482 		struct jh7110_pll_data *pll = &priv->pll[idx];  in jh7110_pll_probe()
484 		pll->hw.init = &init;  in jh7110_pll_probe()
485 		pll->idx = idx;  in jh7110_pll_probe()
487 		ret = devm_clk_hw_register(&pdev->dev, &pll->hw);  in jh7110_pll_probe()
492 	return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv);  in jh7110_pll_probe()
496 	{ .compatible = "starfive,jh7110-pll" },
503 		.name = "clk-starfive-jh7110-pll",