Lines Matching +full:jh7110 +full:- +full:usb

1 // SPDX-License-Identifier: GPL-2.0
3  * StarFive JH7110 System-Top-Group Clock Driver
9 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/starfive,jh7110-crg.h>
15 #include "clk-starfive-jh7110.h"
32 	/* usb */
40 	/* pci-e */
81 	unsigned int idx = clkspec->args[0];  in jh7110_stgclk_get()
84 		return &priv->reg[idx].hw;  in jh7110_stgclk_get()
86 	return ERR_PTR(-EINVAL);  in jh7110_stgclk_get()
95 	priv = devm_kzalloc(&pdev->dev, struct_size(priv, reg, JH7110_STGCLK_END),  in jh7110_stgcrg_probe()
98 		return -ENOMEM;  in jh7110_stgcrg_probe()
100 	spin_lock_init(&priv->rmw_lock);  in jh7110_stgcrg_probe()
101 	priv->dev = &pdev->dev;  in jh7110_stgcrg_probe()
102 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in jh7110_stgcrg_probe()
103 	if (IS_ERR(priv->base))  in jh7110_stgcrg_probe()
104 		return PTR_ERR(priv->base);  in jh7110_stgcrg_probe()
117 		struct jh71x0_clk *clk = &priv->reg[idx];  in jh7110_stgcrg_probe()
118 		const char *fw_name[JH7110_STGCLK_EXT_END - JH7110_STGCLK_END] = {  in jh7110_stgcrg_probe()
134 				parents[i].hw = &priv->reg[pidx].hw;  in jh7110_stgcrg_probe()
136 				parents[i].fw_name = fw_name[pidx - JH7110_STGCLK_END];  in jh7110_stgcrg_probe()
139 		clk->hw.init = &init;  in jh7110_stgcrg_probe()
140 		clk->idx = idx;  in jh7110_stgcrg_probe()
141 		clk->max_div = max & JH71X0_CLK_DIV_MASK;  in jh7110_stgcrg_probe()
143 		ret = devm_clk_hw_register(&pdev->dev, &clk->hw);  in jh7110_stgcrg_probe()
148 	ret = devm_of_clk_add_hw_provider(&pdev->dev, jh7110_stgclk_get, priv);  in jh7110_stgcrg_probe()
152 	return jh7110_reset_controller_register(priv, "rst-stg", 2);  in jh7110_stgcrg_probe()
156 	{ .compatible = "starfive,jh7110-stgcrg" },
164 		.name = "clk-starfive-jh7110-stg",
172 MODULE_DESCRIPTION("StarFive JH7110 System-Top-Group clock driver");