Lines Matching +full:jh7110 +full:- +full:usb
1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/clock/starfive,jh7110-stgcrg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: StarFive JH7110 System-Top-Group Clock and Reset Generator
10 - Xingyu Wu <xingyu.wu@starfivetech.com>
14 const: starfive,jh7110-stgcrg
21 - description: Main Oscillator (24 MHz)
22 - description: HIFI4 core
23 - description: STG AXI/AHB
24 - description: USB (125 MHz)
25 - description: CPU Bus
26 - description: HIFI4 Axi
27 - description: NOC STG Bus
28 - description: APB Bus
30 clock-names:
32 - const: osc
33 - const: hifi4_core
34 - const: stg_axiahb
35 - const: usb_125m
36 - const: cpu_bus
37 - const: hifi4_axi
38 - const: nocstg_bus
39 - const: apb_bus
41 '#clock-cells':
44 See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
46 '#reset-cells':
49 See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
52 - compatible
53 - reg
54 - clocks
55 - clock-names
56 - '#clock-cells'
57 - '#reset-cells'
62 - |
63 #include <dt-bindings/clock/starfive,jh7110-crg.h>
65 stgcrg: clock-controller@10230000 {
66 compatible = "starfive,jh7110-stgcrg";
76 clock-names = "osc", "hifi4_core",
80 #clock-cells = <1>;
81 #reset-cells = <1>;