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/linux/Documentation/arch/riscv/
H A Dhwprobe.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
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H A Duabi.rst1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Linux User ABI
6 ISA string ordering in /proc/cpuinfo
7 ------------------------------------
9 The canonical order of ISA extension names in the ISA string is defined in
14 #. Single-letter extensions come first, in canonical order.
17 #. All multi-letter extensions will be separated from other extensions by an
20 #. Additional standard extensions (starting with 'Z') will be sorted after
21 single-letter extensions and before any higher-privileged extensions.
23 #. For additional standard extensions, the first letter following the 'Z'
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/linux/arch/riscv/kernel/
H A Dcpufeature.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <asm/text-patching.h>
32 #define NUM_ALPHA_EXTS ('z' - 'a' + 1)
40 /* Host ISA bitmap */
43 /* Per-cpu ISA extensions. */
49 * riscv_isa_extension_base() - Get base extension word
51 * @isa_bitmap: ISA bitmap to use
54 * NOTE: If isa_bitmap is NULL then Host ISA bitmap will be used.
63 * __riscv_isa_extension_available() - Check whether given extension
66 * @isa_bitmap: ISA bitmap to use
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H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0-only
27 * Returns the hart ID of the given device tree node, or -ENODEV if the node
28 * isn't an enabled and valid RISC-V hart node.
37 return -ENODEV; in riscv_of_processor_hartid()
45 return -ENODEV; in riscv_of_processor_hartid()
52 const char *isa; in riscv_early_of_processor_hartid() local
56 return -ENODEV; in riscv_early_of_processor_hartid()
62 return -ENODEV; in riscv_early_of_processor_hartid()
67 return -ENODEV; in riscv_early_of_processor_hartid()
70 if (of_property_read_string(node, "riscv,isa-base", &isa)) in riscv_early_of_processor_hartid()
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H A Dsys_hwprobe.c1 // SPDX-License-Identifier: GPL-2.0-only
27 u64 id = -1ULL; in hwprobe_arch_id()
34 switch (pair->key) { in hwprobe_arch_id()
52 * If there's a mismatch for the given set, return -1 in the in hwprobe_arch_id()
56 id = -1ULL; in hwprobe_arch_id()
61 pair->value = id; in hwprobe_arch_id()
70 pair->value = 0; in hwprobe_isa_ext0()
72 pair->value |= RISCV_HWPROBE_IMA_FD; in hwprobe_isa_ext0()
75 pair->value |= RISCV_HWPROBE_IMA_C; in hwprobe_isa_ext0()
78 pair->value |= RISCV_HWPROBE_IMA_V; in hwprobe_isa_ext0()
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/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2044-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 #address-cells = <2>;
8 #size-cells = <2>;
11 #address-cells = <1>;
12 #size-cells = <0>;
13 timebase-frequency = <50000000>;
18 i-cache-block-size = <64>;
19 i-cache-size = <65536>;
20 i-cache-sets = <512>;
21 d-cache-block-size = <64>;
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H A Dcv180x-cpus.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
9 #address-cells = <1>;
10 #size-cells = <0>;
11 timebase-frequency = <25000000>;
17 d-cache-block-size = <64>;
18 d-cache-sets = <512>;
19 d-cache-size = <65536>;
20 i-cache-block-size = <64>;
21 i-cache-sets = <128>;
22 i-cache-size = <32768>;
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/linux/arch/riscv/boot/dts/andes/
H A Dqilai.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/irq.h>
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <1>;
16 #size-cells = <0>;
17 timebase-frequency = <62500000>;
23 riscv,isa-base = "rv64i";
24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
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/linux/arch/riscv/boot/dts/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
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H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu740-c000", "sifive,fu740";
23 #address-cells = <1>;
24 #size-cells = <0>;
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
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/linux/arch/riscv/kernel/pi/
H A Dfdt_early.c1 // SPDX-License-Identifier: GPL-2.0-only
20 prop = fdt_getprop_w((void *)dtb_pa, node, "kaslr-seed", &len); in get_kaslr_seed()
30 * fdt_device_is_available - check if a device is available for use
79 * isa_string_contains - check if isa string contains an extension
81 * @isa_str: isa string to search
84 * Returns true if the extension is in the given isa string,
98 /* Search for single chars between rv32/64 and multi-letter extensions */ in isa_string_contains()
106 /* Skip to start of multi-letter extensions */ in isa_string_contains()
115 /* Multi-letter extensions must be split from other multi-letter in isa_string_contains()
116 * extensions with an "_", the end of a multi-letter extension will in isa_string_contains()
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/linux/arch/riscv/include/asm/
H A Dcpufeature.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright 2022-2024 Rivos, Inc
13 #include <linux/percpu-defs.h>
16 #include <asm/cpufeature-macros.h>
29 DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
34 /* Per-cpu ISA extensions. */
63 /* Used to declare extensions that are a superset of other extensions (Zvbb for instance) */
139 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); in riscv_cpu_has_extension_likely()
150 return __riscv_isa_extension_available(hart_isa[cpu].isa, ext); in riscv_cpu_has_extension_unlikely()
H A Dhwcap.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #define RISCV_ISA_EXT_a ('a' - 'a')
14 #define RISCV_ISA_EXT_c ('c' - 'a')
15 #define RISCV_ISA_EXT_d ('d' - 'a')
16 #define RISCV_ISA_EXT_f ('f' - 'a')
17 #define RISCV_ISA_EXT_h ('h' - 'a')
18 #define RISCV_ISA_EXT_i ('i' - 'a')
19 #define RISCV_ISA_EXT_m ('m' - 'a')
20 #define RISCV_ISA_EXT_q ('q' - 'a')
21 #define RISCV_ISA_EXT_v ('v' - 'a')
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H A Delf.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
37 #define elf_check_arch(x) (((x)->e_machine == EM_RISCV) && \
38 ((x)->e_ident[EI_CLASS] == ELF_CLASS))
57 0x7ff >> (PAGE_SHIFT - 12) : \
58 0x3ffff >> (PAGE_SHIFT - 12))
62 * Provides information on the availiable set of ISA extensions to userspace,
63 * via a bitmap that coorespends to each single-letter ISA extension. This is
71 (_r)->a1 = _exec_map_addr; \
72 (_r)->a2 = _interp_map_addr; \
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H A Dvendor_extensions.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 DECLARE_BITMAP(isa, RISCV_ISA_VENDOR_EXT_MAX);
36 * The alternatives need some way of distinguishing between vendor extensions
42 #define VENDOR_EXT_ALL_CPUS -1
/linux/arch/riscv/boot/dts/microchip/
H A Dmpfs.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
4 /dts-v1/;
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
8 #address-cells = <2>;
9 #size-cells = <2>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 timebase-frequency = <1000000>;
21 i-cache-block-size = <64>;
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/linux/arch/arm/crypto/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
6 tristate "Hash functions: GHASH (PMULL/NEON/ARMv8 Crypto Extensions)"
14 GCM GHASH function (NIST SP800-38D)
17 - PMULL (Polynomial Multiply Long) instructions
18 - NEON (Advanced SIMD) extensions
19 - ARMv8 Crypto Extensions
23 that is part of the ARMv8 Crypto Extensions, or a slower variant that
24 uses the vmull.p8 instruction that is part of the basic NEON ISA.
34 - NEON (Advanced SIMD) extensions
44 - NEON (Advanced SIMD) extensions
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/linux/arch/riscv/kernel/vendor_extensions/
H A Dthead.c1 // SPDX-License-Identifier: GPL-2.0-only
11 /* All T-Head vendor extensions supported in Linux */
26 …t(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap[cpu].isa); in disable_xtheadvector()
28 …r_bit(RISCV_ISA_VENDOR_EXT_XTHEADVECTOR, riscv_isa_vendor_ext_list_thead.all_harts_isa_bitmap.isa); in disable_xtheadvector()
/linux/arch/powerpc/platforms/
H A DKconfig.cputype1 # SPDX-License-Identifier: GPL-2.0
7 bool "64-bit kernel"
10 This option selects whether a 32-bit or a 64-bit kernel
267 default "-mtune=power10" if $(cc-option,-mtune=power10)
268 default "-mtune=power9" if $(cc-option,-mtune=power9)
269 default "-mtune=power8" if $(cc-option,-mtune=power8)
346 This option enables kernel support for larger than 32-bit physical
351 is platform-dependent.
360 This option enables kernel support for the Altivec extensions to the
367 any affect on a non-altivec cpu (it does, however add code to the
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/linux/arch/riscv/boot/dts/allwinner/
H A Dsun20i-d1s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
6 #include "sunxi-d1s-t113.dtsi"
10 timebase-frequency = <24000000>;
11 #address-cells = <1>;
12 #size-cells = <0>;
19 d-cache-block-size = <64>;
20 d-cache-sets = <256>;
21 d-cache-size = <32768>;
22 i-cache-block-size = <64>;
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/linux/arch/riscv/include/asm/vendor_extensions/
H A Dvendor_hwprobe.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 if (__riscv_isa_extension_available(isainfo->isa, RISCV_ISA_VENDOR_EXT_##ext)) \
14 pair->value |= RISCV_HWPROBE_VENDOR_EXT_##ext; \
20 * Loop through and record extensions that 1) anyone has, and 2) anyone
23 * _extension_checks is an arbitrary C block to set the values of pair->value
34 (pair)->value &= ~missing; \
/linux/arch/riscv/boot/dts/renesas/
H A Dr9a07g043f.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/interrupt-controller/irq.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
18 timebase-frequency = <12000000>;
23 #cooling-cells = <2>;
26 riscv,isa = "rv64imafdc";
27 riscv,isa-base = "rv64i";
28 riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
31 mmu-type = "riscv,sv39";
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/linux/arch/mips/include/asm/
H A Dcpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
18 +----------------+----------------+----------------+----------------+
20 +----------------+----------------+----------------+----------------+
24 that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
92 #define PRID_IMP_LOONGSON_32 0x4200 /* Loongson-1 */
95 #define PRID_IMP_LOONGSON_64R 0x6100 /* Reduced Loongson-2 */
96 #define PRID_IMP_LOONGSON_64C 0x6300 /* Classic Loongson-2 and Loongson-3 */
97 #define PRID_IMP_LOONGSON_64G 0xc000 /* Generic Loongson-2 and Loongson-3 */
189 #define PRID_IMP_XBURST_REV1 0x0200 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
190 #define PRID_IMP_XBURST_REV2 0x0100 /* XBurst®1 with MXU2.0 SIMD ISA */
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/linux/arch/arc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
90 source "arch/arc/plat-tb10x/Kconfig"
91 source "arch/arc/plat-axs10x/Kconfig"
92 source "arch/arc/plat-hsdk/Kconfig"
101 bool "ARCompact ISA"
104 The original ARC ISA of ARC600/700 cores
107 bool "ARC ISA v2"
110 ISA for the Next Generation ARC-HS cores
128 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
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/linux/arch/x86/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
4 bool "64-bit kernel" if "$(ARCH)" = "x86"
7 Say yes to build a 64-bit kernel - formerly known as x86_64
8 Say no to build a 32-bit kernel - formerly known as i386
13 # Options that are inherently 32-bit kernel only:
26 # Options that are inherently 64-bit kernel only:
56 # ported to 32-bit as well. )
158 # Word-size accesses may read uninitialized data past the trailing \0
342 default "elf32-i386" if X86_32
343 default "elf64-x86-64" if X86_64
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