xref: /linux/arch/riscv/boot/dts/sifive/fu540-c000.dtsi (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2018-2019 SiFive, Inc */
3
4/dts-v1/;
5
6#include <dt-bindings/clock/sifive-fu540-prci.h>
7
8/ {
9	#address-cells = <2>;
10	#size-cells = <2>;
11	compatible = "sifive,fu540-c000", "sifive,fu540";
12
13	aliases {
14		serial0 = &uart0;
15		serial1 = &uart1;
16		ethernet0 = &eth0;
17	};
18
19	chosen {
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25		cpu0: cpu@0 {
26			compatible = "sifive,e51", "sifive,rocket0", "riscv";
27			device_type = "cpu";
28			i-cache-block-size = <64>;
29			i-cache-sets = <128>;
30			i-cache-size = <16384>;
31			reg = <0>;
32			riscv,isa = "rv64imac";
33			riscv,isa-base = "rv64i";
34			riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
35					       "zihpm";
36			status = "disabled";
37			cpu0_intc: interrupt-controller {
38				#interrupt-cells = <1>;
39				compatible = "riscv,cpu-intc";
40				interrupt-controller;
41			};
42		};
43		cpu1: cpu@1 {
44			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
45			d-cache-block-size = <64>;
46			d-cache-sets = <64>;
47			d-cache-size = <32768>;
48			d-tlb-sets = <1>;
49			d-tlb-size = <32>;
50			device_type = "cpu";
51			i-cache-block-size = <64>;
52			i-cache-sets = <64>;
53			i-cache-size = <32768>;
54			i-tlb-sets = <1>;
55			i-tlb-size = <32>;
56			mmu-type = "riscv,sv39";
57			reg = <1>;
58			riscv,isa = "rv64imafdc";
59			riscv,isa-base = "rv64i";
60			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
61					       "zifencei", "zihpm";
62			tlb-split;
63			next-level-cache = <&l2cache>;
64			cpu1_intc: interrupt-controller {
65				#interrupt-cells = <1>;
66				compatible = "riscv,cpu-intc";
67				interrupt-controller;
68			};
69		};
70		cpu2: cpu@2 {
71			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
72			d-cache-block-size = <64>;
73			d-cache-sets = <64>;
74			d-cache-size = <32768>;
75			d-tlb-sets = <1>;
76			d-tlb-size = <32>;
77			device_type = "cpu";
78			i-cache-block-size = <64>;
79			i-cache-sets = <64>;
80			i-cache-size = <32768>;
81			i-tlb-sets = <1>;
82			i-tlb-size = <32>;
83			mmu-type = "riscv,sv39";
84			reg = <2>;
85			riscv,isa = "rv64imafdc";
86			riscv,isa-base = "rv64i";
87			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
88					       "zifencei", "zihpm";
89			tlb-split;
90			next-level-cache = <&l2cache>;
91			cpu2_intc: interrupt-controller {
92				#interrupt-cells = <1>;
93				compatible = "riscv,cpu-intc";
94				interrupt-controller;
95			};
96		};
97		cpu3: cpu@3 {
98			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
99			d-cache-block-size = <64>;
100			d-cache-sets = <64>;
101			d-cache-size = <32768>;
102			d-tlb-sets = <1>;
103			d-tlb-size = <32>;
104			device_type = "cpu";
105			i-cache-block-size = <64>;
106			i-cache-sets = <64>;
107			i-cache-size = <32768>;
108			i-tlb-sets = <1>;
109			i-tlb-size = <32>;
110			mmu-type = "riscv,sv39";
111			reg = <3>;
112			riscv,isa = "rv64imafdc";
113			riscv,isa-base = "rv64i";
114			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
115					       "zifencei", "zihpm";
116			tlb-split;
117			next-level-cache = <&l2cache>;
118			cpu3_intc: interrupt-controller {
119				#interrupt-cells = <1>;
120				compatible = "riscv,cpu-intc";
121				interrupt-controller;
122			};
123		};
124		cpu4: cpu@4 {
125			compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
126			d-cache-block-size = <64>;
127			d-cache-sets = <64>;
128			d-cache-size = <32768>;
129			d-tlb-sets = <1>;
130			d-tlb-size = <32>;
131			device_type = "cpu";
132			i-cache-block-size = <64>;
133			i-cache-sets = <64>;
134			i-cache-size = <32768>;
135			i-tlb-sets = <1>;
136			i-tlb-size = <32>;
137			mmu-type = "riscv,sv39";
138			reg = <4>;
139			riscv,isa = "rv64imafdc";
140			riscv,isa-base = "rv64i";
141			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
142					       "zifencei", "zihpm";
143			tlb-split;
144			next-level-cache = <&l2cache>;
145			cpu4_intc: interrupt-controller {
146				#interrupt-cells = <1>;
147				compatible = "riscv,cpu-intc";
148				interrupt-controller;
149			};
150		};
151
152		cpu-map {
153			cluster0 {
154				core0 {
155					cpu = <&cpu0>;
156				};
157
158				core1 {
159					cpu = <&cpu1>;
160				};
161
162				core2 {
163					cpu = <&cpu2>;
164				};
165
166				core3 {
167					cpu = <&cpu3>;
168				};
169
170				core4 {
171					cpu = <&cpu4>;
172				};
173			};
174		};
175	};
176	soc {
177		#address-cells = <2>;
178		#size-cells = <2>;
179		compatible = "simple-bus";
180		ranges;
181		plic0: interrupt-controller@c000000 {
182			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
183			reg = <0x0 0xc000000 0x0 0x4000000>;
184			#address-cells = <0>;
185			#interrupt-cells = <1>;
186			interrupt-controller;
187			interrupts-extended =
188				<&cpu0_intc 0xffffffff>,
189				<&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
190				<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
191				<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
192				<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
193			riscv,ndev = <53>;
194		};
195		prci: clock-controller@10000000 {
196			compatible = "sifive,fu540-c000-prci";
197			reg = <0x0 0x10000000 0x0 0x1000>;
198			clocks = <&hfclk>, <&rtcclk>;
199			#clock-cells = <1>;
200		};
201		uart0: serial@10010000 {
202			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
203			reg = <0x0 0x10010000 0x0 0x1000>;
204			interrupt-parent = <&plic0>;
205			interrupts = <4>;
206			clocks = <&prci FU540_PRCI_CLK_TLCLK>;
207			status = "disabled";
208		};
209		dma: dma-controller@3000000 {
210			compatible = "sifive,fu540-c000-pdma", "sifive,pdma0";
211			reg = <0x0 0x3000000 0x0 0x8000>;
212			interrupt-parent = <&plic0>;
213			interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
214				     <30>;
215			dma-channels = <4>;
216			#dma-cells = <1>;
217		};
218		uart1: serial@10011000 {
219			compatible = "sifive,fu540-c000-uart", "sifive,uart0";
220			reg = <0x0 0x10011000 0x0 0x1000>;
221			interrupt-parent = <&plic0>;
222			interrupts = <5>;
223			clocks = <&prci FU540_PRCI_CLK_TLCLK>;
224			status = "disabled";
225		};
226		i2c0: i2c@10030000 {
227			compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
228			reg = <0x0 0x10030000 0x0 0x1000>;
229			interrupt-parent = <&plic0>;
230			interrupts = <50>;
231			clocks = <&prci FU540_PRCI_CLK_TLCLK>;
232			reg-shift = <2>;
233			reg-io-width = <1>;
234			#address-cells = <1>;
235			#size-cells = <0>;
236			status = "disabled";
237		};
238		qspi0: spi@10040000 {
239			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
240			reg = <0x0 0x10040000 0x0 0x1000>,
241			      <0x0 0x20000000 0x0 0x10000000>;
242			interrupt-parent = <&plic0>;
243			interrupts = <51>;
244			clocks = <&prci FU540_PRCI_CLK_TLCLK>;
245			#address-cells = <1>;
246			#size-cells = <0>;
247			status = "disabled";
248		};
249		qspi1: spi@10041000 {
250			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
251			reg = <0x0 0x10041000 0x0 0x1000>,
252			      <0x0 0x30000000 0x0 0x10000000>;
253			interrupt-parent = <&plic0>;
254			interrupts = <52>;
255			clocks = <&prci FU540_PRCI_CLK_TLCLK>;
256			#address-cells = <1>;
257			#size-cells = <0>;
258			status = "disabled";
259		};
260		qspi2: spi@10050000 {
261			compatible = "sifive,fu540-c000-spi", "sifive,spi0";
262			reg = <0x0 0x10050000 0x0 0x1000>;
263			interrupt-parent = <&plic0>;
264			interrupts = <6>;
265			clocks = <&prci FU540_PRCI_CLK_TLCLK>;
266			#address-cells = <1>;
267			#size-cells = <0>;
268			status = "disabled";
269		};
270		eth0: ethernet@10090000 {
271			compatible = "sifive,fu540-c000-gem";
272			interrupt-parent = <&plic0>;
273			interrupts = <53>;
274			reg = <0x0 0x10090000 0x0 0x2000>,
275			      <0x0 0x100a0000 0x0 0x1000>;
276			local-mac-address = [00 00 00 00 00 00];
277			clock-names = "pclk", "hclk";
278			clocks = <&prci FU540_PRCI_CLK_GEMGXLPLL>,
279				 <&prci FU540_PRCI_CLK_GEMGXLPLL>;
280			#address-cells = <1>;
281			#size-cells = <0>;
282			status = "disabled";
283		};
284		pwm0: pwm@10020000 {
285			compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
286			reg = <0x0 0x10020000 0x0 0x1000>;
287			interrupt-parent = <&plic0>;
288			interrupts = <42>, <43>, <44>, <45>;
289			clocks = <&prci FU540_PRCI_CLK_TLCLK>;
290			#pwm-cells = <3>;
291			status = "disabled";
292		};
293		pwm1: pwm@10021000 {
294			compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
295			reg = <0x0 0x10021000 0x0 0x1000>;
296			interrupt-parent = <&plic0>;
297			interrupts = <46>, <47>, <48>, <49>;
298			clocks = <&prci FU540_PRCI_CLK_TLCLK>;
299			#pwm-cells = <3>;
300			status = "disabled";
301		};
302		l2cache: cache-controller@2010000 {
303			compatible = "sifive,fu540-c000-ccache", "cache";
304			cache-block-size = <64>;
305			cache-level = <2>;
306			cache-sets = <1024>;
307			cache-size = <2097152>;
308			cache-unified;
309			interrupt-parent = <&plic0>;
310			interrupts = <1>, <2>, <3>;
311			reg = <0x0 0x2010000 0x0 0x1000>;
312		};
313		gpio: gpio@10060000 {
314			compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
315			interrupt-parent = <&plic0>;
316			interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
317				     <14>, <15>, <16>, <17>, <18>, <19>, <20>,
318				     <21>, <22>;
319			reg = <0x0 0x10060000 0x0 0x1000>;
320			gpio-controller;
321			#gpio-cells = <2>;
322			interrupt-controller;
323			#interrupt-cells = <2>;
324			clocks = <&prci FU540_PRCI_CLK_TLCLK>;
325			status = "disabled";
326		};
327	};
328};
329