1 // SPDX-License-Identifier: GPL-2.0-only
27  * Returns the hart ID of the given device tree node, or -ENODEV if the node
28  * isn't an enabled and valid RISC-V hart node.
37 		return -ENODEV;  in riscv_of_processor_hartid()
45 		return -ENODEV;  in riscv_of_processor_hartid()
52 	const char *isa;  in riscv_early_of_processor_hartid()  local
56 		return -ENODEV;  in riscv_early_of_processor_hartid()
62 		return -ENODEV;  in riscv_early_of_processor_hartid()
67 		return -ENODEV;  in riscv_early_of_processor_hartid()
70 	if (of_property_read_string(node, "riscv,isa-base", &isa))  in riscv_early_of_processor_hartid()
73 	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) {  in riscv_early_of_processor_hartid()
75 		return -ENODEV;  in riscv_early_of_processor_hartid()
78 	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) {  in riscv_early_of_processor_hartid()
80 		return -ENODEV;  in riscv_early_of_processor_hartid()
83 	if (!of_property_present(node, "riscv,isa-extensions"))  in riscv_early_of_processor_hartid()
84 		return -ENODEV;  in riscv_early_of_processor_hartid()
86 	if (of_property_match_string(node, "riscv,isa-extensions", "i") < 0 ||  in riscv_early_of_processor_hartid()
87 	    of_property_match_string(node, "riscv,isa-extensions", "m") < 0 ||  in riscv_early_of_processor_hartid()
88 	    of_property_match_string(node, "riscv,isa-extensions", "a") < 0) {  in riscv_early_of_processor_hartid()
90 		return -ENODEV;  in riscv_early_of_processor_hartid()
97 		pr_warn("CPU with hartid=%lu is invalid: this kernel does not parse \"riscv,isa\"",  in riscv_early_of_processor_hartid()
99 		return -ENODEV;  in riscv_early_of_processor_hartid()
102 	if (of_property_read_string(node, "riscv,isa", &isa)) {  in riscv_early_of_processor_hartid()
103 		pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n",  in riscv_early_of_processor_hartid()
105 		return -ENODEV;  in riscv_early_of_processor_hartid()
108 	if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) {  in riscv_early_of_processor_hartid()
110 		return -ENODEV;  in riscv_early_of_processor_hartid()
113 	if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) {  in riscv_early_of_processor_hartid()
115 		return -ENODEV;  in riscv_early_of_processor_hartid()
125  * RISC-V core (HART) node and extract the cpuid from it.
129 	for (; node; node = node->parent) {  in riscv_of_parent_hartid()
134 				return -ENODEV;  in riscv_of_parent_hartid()
140 	return -1;  in riscv_of_parent_hartid()
148 	ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();  in riscv_get_marchid()
150 	ci->marchid = csr_read(CSR_MARCHID);  in riscv_get_marchid()
152 	ci->marchid = 0;  in riscv_get_marchid()
154 	return ci->marchid;  in riscv_get_marchid()
162 	ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();  in riscv_get_mvendorid()
164 	ci->mvendorid = csr_read(CSR_MVENDORID);  in riscv_get_mvendorid()
166 	ci->mvendorid = 0;  in riscv_get_mvendorid()
168 	return ci->mvendorid;  in riscv_get_mvendorid()
177 	return ci->mvendorid;  in riscv_cached_mvendorid()
185 	return ci->marchid;  in riscv_cached_marchid()
193 	return ci->mimpid;  in riscv_cached_mimpid()
202 	if (!ci->mvendorid)  in riscv_cpuinfo_starting()
203 		ci->mvendorid = sbi_spec_is_0_1() ? 0 : sbi_get_mvendorid();  in riscv_cpuinfo_starting()
204 	if (!ci->marchid)  in riscv_cpuinfo_starting()
205 		ci->marchid = sbi_spec_is_0_1() ? 0 : sbi_get_marchid();  in riscv_cpuinfo_starting()
206 	ci->mimpid = sbi_spec_is_0_1() ? 0 : sbi_get_mimpid();  in riscv_cpuinfo_starting()
208 	if (!ci->mvendorid)  in riscv_cpuinfo_starting()
209 		ci->mvendorid = csr_read(CSR_MVENDORID);  in riscv_cpuinfo_starting()
210 	if (!ci->marchid)  in riscv_cpuinfo_starting()
211 		ci->marchid = csr_read(CSR_MARCHID);  in riscv_cpuinfo_starting()
212 	ci->mimpid = csr_read(CSR_MIMPID);  in riscv_cpuinfo_starting()
214 	ci->mvendorid = 0;  in riscv_cpuinfo_starting()
215 	ci->marchid = 0;  in riscv_cpuinfo_starting()
216 	ci->mimpid = 0;  in riscv_cpuinfo_starting()
239 #define ALL_CPUS -1
249 		ext_data = riscv_isa_vendor_ext_list[i]->ext_data;  in print_vendor_isa()
252 			vendor_bitmap = &ext_list->all_harts_isa_bitmap;  in print_vendor_isa()
254 			vendor_bitmap = &ext_list->per_hart_isa_bitmap[cpu];  in print_vendor_isa()
256 		for (int j = 0; j < ext_list->ext_data_count; j++) {  in print_vendor_isa()
257 			if (!__riscv_isa_extension_available(vendor_bitmap->isa, ext_data[j].id))  in print_vendor_isa()
277 		/* Only multi-letter extensions are split by underscores */  in print_isa()
315 	*pos = cpumask_next(*pos - 1, cpu_online_mask);  in c_start()
333 	unsigned long cpu_id = (unsigned long)v - 1;  in c_show()
342 	 * For historical raisins, the isa: line is limited to the lowest common  in c_show()
343 	 * denominator of extensions supported across all harts. A true list of  in c_show()
344 	 * extensions supported on this hart is printed later in the hart isa:  in c_show()
347 	seq_puts(m, "isa\t\t: ");  in c_show()
361 	seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid);  in c_show()
362 	seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid);  in c_show()
363 	seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid);  in c_show()
366 	 * Print the ISA extensions specific to this hart, which may show  in c_show()
367 	 * additional extensions not present across all harts.  in c_show()
369 	seq_puts(m, "hart isa\t: ");  in c_show()
370 	print_isa(m, hart_isa[cpu_id].isa, cpu_id);  in c_show()