1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2025 Andes Technology Corporation. All rights reserved. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/interrupt-controller/irq.h> 9 10/ { 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 timebase-frequency = <62500000>; 18 19 cpu0: cpu@0 { 20 compatible = "andestech,ax45mp", "riscv"; 21 device_type = "cpu"; 22 reg = <0>; 23 riscv,isa-base = "rv64i"; 24 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 25 "zicntr", "zicsr", "zifencei", 26 "zihpm", "xandespmu"; 27 mmu-type = "riscv,sv39"; 28 clock-frequency = <100000000>; 29 i-cache-size = <0x8000>; 30 i-cache-sets = <256>; 31 i-cache-line-size = <64>; 32 d-cache-size = <0x8000>; 33 d-cache-sets = <128>; 34 d-cache-line-size = <64>; 35 next-level-cache = <&l2_cache>; 36 37 cpu0_intc: interrupt-controller { 38 compatible = "andestech,cpu-intc", "riscv,cpu-intc"; 39 #interrupt-cells = <1>; 40 interrupt-controller; 41 }; 42 }; 43 44 cpu1: cpu@1 { 45 compatible = "andestech,ax45mp", "riscv"; 46 device_type = "cpu"; 47 reg = <1>; 48 riscv,isa-base = "rv64i"; 49 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 50 "zicntr", "zicsr", "zifencei", 51 "zihpm", "xandespmu"; 52 mmu-type = "riscv,sv39"; 53 clock-frequency = <100000000>; 54 i-cache-size = <0x8000>; 55 i-cache-sets = <256>; 56 i-cache-line-size = <64>; 57 d-cache-size = <0x8000>; 58 d-cache-sets = <128>; 59 d-cache-line-size = <64>; 60 next-level-cache = <&l2_cache>; 61 62 cpu1_intc: interrupt-controller { 63 compatible = "andestech,cpu-intc", 64 "riscv,cpu-intc"; 65 #interrupt-cells = <1>; 66 interrupt-controller; 67 }; 68 }; 69 70 cpu2: cpu@2 { 71 compatible = "andestech,ax45mp", "riscv"; 72 device_type = "cpu"; 73 reg = <2>; 74 riscv,isa-base = "rv64i"; 75 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 76 "zicntr", "zicsr", "zifencei", 77 "zihpm", "xandespmu"; 78 mmu-type = "riscv,sv39"; 79 clock-frequency = <100000000>; 80 i-cache-size = <0x8000>; 81 i-cache-sets = <256>; 82 i-cache-line-size = <64>; 83 d-cache-size = <0x8000>; 84 d-cache-sets = <128>; 85 d-cache-line-size = <64>; 86 next-level-cache = <&l2_cache>; 87 88 cpu2_intc: interrupt-controller { 89 compatible = "andestech,cpu-intc", 90 "riscv,cpu-intc"; 91 #interrupt-cells = <1>; 92 interrupt-controller; 93 }; 94 }; 95 96 cpu3: cpu@3 { 97 compatible = "andestech,ax45mp", "riscv"; 98 device_type = "cpu"; 99 reg = <3>; 100 riscv,isa-base = "rv64i"; 101 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", 102 "zicntr", "zicsr", "zifencei", 103 "zihpm", "xandespmu"; 104 mmu-type = "riscv,sv39"; 105 clock-frequency = <100000000>; 106 i-cache-size = <0x8000>; 107 i-cache-sets = <256>; 108 i-cache-line-size = <64>; 109 d-cache-size = <0x8000>; 110 d-cache-sets = <128>; 111 d-cache-line-size = <64>; 112 next-level-cache = <&l2_cache>; 113 114 cpu3_intc: interrupt-controller { 115 compatible = "andestech,cpu-intc", 116 "riscv,cpu-intc"; 117 #interrupt-cells = <1>; 118 interrupt-controller; 119 }; 120 }; 121 }; 122 123 soc { 124 compatible = "simple-bus"; 125 ranges; 126 interrupt-parent = <&plic>; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 130 plmt: timer@100000 { 131 compatible = "andestech,qilai-plmt", "andestech,plmt0"; 132 reg = <0x0 0x00100000 0x0 0x100000>; 133 interrupts-extended = <&cpu0_intc 7>, 134 <&cpu1_intc 7>, 135 <&cpu2_intc 7>, 136 <&cpu3_intc 7>; 137 }; 138 139 l2_cache: cache-controller@200000 { 140 compatible = "andestech,qilai-ax45mp-cache", 141 "andestech,ax45mp-cache", "cache"; 142 reg = <0x0 0x00200000 0x0 0x100000>; 143 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 144 cache-line-size = <64>; 145 cache-level = <2>; 146 cache-sets = <2048>; 147 cache-size = <0x200000>; 148 cache-unified; 149 }; 150 151 plic_sw: interrupt-controller@400000 { 152 compatible = "andestech,qilai-plicsw", 153 "andestech,plicsw"; 154 reg = <0x0 0x00400000 0x0 0x400000>; 155 interrupts-extended = <&cpu0_intc 3>, 156 <&cpu1_intc 3>, 157 <&cpu2_intc 3>, 158 <&cpu3_intc 3>; 159 }; 160 161 plic: interrupt-controller@2000000 { 162 compatible = "andestech,qilai-plic", 163 "andestech,nceplic100"; 164 reg = <0x0 0x02000000 0x0 0x2000000>; 165 #address-cells = <0>; 166 #interrupt-cells = <2>; 167 interrupt-controller; 168 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 169 <&cpu1_intc 11>, <&cpu1_intc 9>, 170 <&cpu2_intc 11>, <&cpu2_intc 9>, 171 <&cpu3_intc 11>, <&cpu3_intc 9>; 172 riscv,ndev = <71>; 173 }; 174 175 uart0: serial@30300000 { 176 compatible = "andestech,uart16550", "ns16550a"; 177 reg = <0x0 0x30300000 0x0 0x100000>; 178 interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; 179 clock-frequency = <50000000>; 180 reg-offset = <32>; 181 reg-shift = <2>; 182 reg-io-width = <4>; 183 no-loopback-test; 184 }; 185 }; 186}; 187