1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// Copyright 2025 Tenstorrent AI ULC 3/dts-v1/; 4 5/ { 6 compatible = "tenstorrent,blackhole"; 7 #address-cells = <2>; 8 #size-cells = <2>; 9 10 cpus { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 timebase-frequency = <50000000>; 14 15 cpu@0 { 16 compatible = "sifive,x280", "sifive,rocket0", "riscv"; 17 device_type = "cpu"; 18 reg = <0>; 19 mmu-type = "riscv,sv57"; 20 riscv,isa-base = "rv64i"; 21 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", 22 "zifencei", "zfh", "zba", "zbb", "sscofpmf"; 23 24 cpu0_intc: interrupt-controller { 25 compatible = "riscv,cpu-intc"; 26 #interrupt-cells = <1>; 27 interrupt-controller; 28 }; 29 }; 30 31 cpu@1 { 32 compatible = "sifive,x280", "sifive,rocket0", "riscv"; 33 device_type = "cpu"; 34 reg = <1>; 35 mmu-type = "riscv,sv57"; 36 riscv,isa-base = "rv64i"; 37 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", 38 "zifencei", "zfh", "zba", "zbb", "sscofpmf"; 39 40 cpu1_intc: interrupt-controller { 41 compatible = "riscv,cpu-intc"; 42 #interrupt-cells = <1>; 43 interrupt-controller; 44 }; 45 }; 46 47 cpu@2 { 48 compatible = "sifive,x280", "sifive,rocket0", "riscv"; 49 device_type = "cpu"; 50 reg = <2>; 51 mmu-type = "riscv,sv57"; 52 riscv,isa-base = "rv64i"; 53 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", 54 "zifencei", "zfh", "zba", "zbb", "sscofpmf"; 55 56 cpu2_intc: interrupt-controller { 57 compatible = "riscv,cpu-intc"; 58 #interrupt-cells = <1>; 59 interrupt-controller; 60 }; 61 }; 62 63 cpu@3 { 64 compatible = "sifive,x280", "sifive,rocket0", "riscv"; 65 device_type = "cpu"; 66 reg = <3>; 67 mmu-type = "riscv,sv57"; 68 riscv,isa-base = "rv64i"; 69 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "v", "zicsr", 70 "zifencei", "zfh", "zba", "zbb", "sscofpmf"; 71 72 cpu3_intc: interrupt-controller { 73 compatible = "riscv,cpu-intc"; 74 #interrupt-cells = <1>; 75 interrupt-controller; 76 }; 77 }; 78 }; 79 80 soc { 81 #address-cells = <2>; 82 #size-cells = <2>; 83 compatible = "simple-bus"; 84 ranges; 85 86 clint0: timer@2000000 { 87 compatible = "tenstorrent,blackhole-clint", "sifive,clint0"; 88 reg = <0x0 0x2000000 0x0 0x10000>; 89 interrupts-extended = <&cpu0_intc 0x3>, <&cpu0_intc 0x7>, 90 <&cpu1_intc 0x3>, <&cpu1_intc 0x7>, 91 <&cpu2_intc 0x3>, <&cpu2_intc 0x7>, 92 <&cpu3_intc 0x3>, <&cpu3_intc 0x7>; 93 }; 94 95 plic0: interrupt-controller@c000000 { 96 compatible = "tenstorrent,blackhole-plic", "sifive,plic-1.0.0"; 97 reg = <0x0 0x0c000000 0x0 0x04000000>; 98 interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>, 99 <&cpu1_intc 11>, <&cpu1_intc 9>, 100 <&cpu2_intc 11>, <&cpu2_intc 9>, 101 <&cpu3_intc 11>, <&cpu3_intc 9>; 102 interrupt-controller; 103 #interrupt-cells = <1>; 104 #address-cells = <0>; 105 riscv,ndev = <128>; 106 }; 107 }; 108}; 109