Lines Matching +full:isa +full:- +full:extensions
1 # SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 ---
4 $id: http://devicetree.org/schemas/riscv/extensions.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: RISC-V ISA extensions
10 - Paul Walmsley <paul.walmsley@sifive.com>
11 - Palmer Dabbelt <palmer@sifive.com>
12 - Conor Dooley <conor@kernel.org>
15 RISC-V has a large number of extensions, some of which are "standard"
16 extensions, meaning they are ratified by RISC-V International, and others
17 are "vendor" extensions.
23 The properties for standard extensions therefore map to their originally
24 ratified states, with the exception of the I, Zicntr & Zihpm extensions.
34 riscv,isa:
36 Identifies the specific RISC-V instruction set architecture
37 supported by the hart. These are documented in the RISC-V
38 User-Level ISA document, available from
41 Due to revisions of the ISA specification, some deviations
43 Notably, riscv,isa was defined prior to the creation of the
44 Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i"
47 While the isa strings in ISA specification are case
48 insensitive, letters in the riscv,isa string must be all
51 pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$
54 riscv,isa-base:
56 The base ISA implemented by this hart, as described by the 20191213
57 version of the unprivileged ISA specification.
59 - rv32i
60 - rv64i
62 riscv,isa-extensions:
63 $ref: /schemas/types.yaml#/definitions/string-array
65 description: Extensions supported by the hart.
68 # single letter extensions, in canonical order
69 - const: i
72 version of the unprivileged ISA specification.
75 the Zicntr and Zihpm extensions after the ratification of the
78 - const: m
81 ratified in the 20191213 version of the unprivileged ISA
84 - const: a
87 20191213 version of the unprivileged ISA specification.
89 - const: f
91 The standard F extension for single-precision floating point, as
92 ratified in the 20191213 version of the unprivileged ISA
95 - const: d
97 The standard D extension for double-precision floating-point, as
98 ratified in the 20191213 version of the unprivileged ISA
101 - const: q
103 The standard Q extension for quad-precision floating-point, as
104 ratified in the 20191213 version of the unprivileged ISA
107 - const: c
110 the 20191213 version of the unprivileged ISA specification.
112 - const: v
115 in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f
116 encoding") of the riscv-v-spec.
118 - const: h
121 version of the privileged ISA specification.
123 # multi-letter extensions, sorted alphanumerically
124 - const: smaia
126 The standard Smaia supervisor-level extension for the advanced
127 interrupt architecture for machine-mode-visible csr and behavioural
129 request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
131 - const: smstateen
134 added by other RISC-V extensions in H/S/VS/U/VU modes and as
135 ratified at commit a28bfae (Ratified (#7)) of riscv-state-enable.
137 - const: ssaia
139 The standard Ssaia supervisor-level extension for the advanced
140 interrupt architecture for supervisor-mode-visible csr and
142 ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia.
144 - const: sscofpmf
146 The standard Sscofpmf supervisor-level extension for count overflow
147 and mode-based filtering as ratified at commit 01d1df0 ("Add ability
148 to manually trigger workflow. (#2)") of riscv-count-overflow.
150 - const: sstc
152 The standard Sstc supervisor-level extension for time compare as
154 workflow. (#2)") of riscv-time-compare.
156 - const: svinval
158 The standard Svinval supervisor-level extension for fine-grained
159 address-translation cache invalidation as ratified in the 20191213
160 version of the privileged ISA specification.
162 - const: svnapot
164 The standard Svnapot supervisor-level extensions for napot
166 privileged ISA specification.
168 - const: svpbmt
170 The standard Svpbmt supervisor-level extensions for page-based
172 ISA specification.
174 - const: svvptc
176 The standard Svvptc supervisor-level extension for
177 address-translation cache behaviour with respect to invalid entries
179 riscv-svvptc.
181 - const: zacas
183 The Zacas extension for Atomic Compare-and-Swap (CAS) instructions
185 ratified") of the riscv-zacas.
187 - const: zawrs
189 The Zawrs extension for entering a low-power state or for trapping
192 riscv/zawrs") of riscv-isa-manual.
194 - const: zba
196 The standard Zba bit-manipulation extension for address generation
198 request #158 from hirooih/clmul-fix-loop-end-condition") of
199 riscv-bitmanip.
201 - const: zbb
203 The standard Zbb bit-manipulation extension for basic bit-manipulation
205 hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
207 - const: zbc
209 The standard Zbc bit-manipulation extension for carry-less
211 #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
213 - const: zbkb
216 in version 1.0 of RISC-V Cryptography Extensions Volume I
219 - const: zbkc
221 The standard Zbkc carry-less multiply instructions as ratified
222 in version 1.0 of RISC-V Cryptography Extensions Volume I
225 - const: zbkx
228 in version 1.0 of RISC-V Cryptography Extensions Volume I
231 - const: zbs
233 The standard Zbs bit-manipulation extension for single-bit
235 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip.
237 - const: zca
239 The Zca extension part of Zc* standard extensions for code size
241 RV64 as it contains no instructions") of riscv-code-size-reduction,
242 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
245 - const: zcb
247 The Zcb extension part of Zc* standard extensions for code size
249 RV64 as it contains no instructions") of riscv-code-size-reduction,
250 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
253 - const: zcd
255 The Zcd extension part of Zc* standard extensions for code size
257 RV64 as it contains no instructions") of riscv-code-size-reduction,
258 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
261 - const: zcf
263 The Zcf extension part of Zc* standard extensions for code size
265 RV64 as it contains no instructions") of riscv-code-size-reduction,
266 merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
269 - const: zcmop
272 c732a4f39a4 ("Zcmop is ratified/1.0") of the riscv-isa-manual.
274 - const: zfa
278 riscv-isa-manual.
280 - const: zfh
282 The standard Zfh extension for 16-bit half-precision binary
283 floating-point instructions, as ratified in commit 64074bc ("Update
284 version numbers for Zfh/Zfinx") of riscv-isa-manual.
286 - const: zfhmin
289 16-bit half-precision binary floating-point instructions, as ratified
291 riscv-isa-manual.
293 - const: zk
296 in version 1.0 of RISC-V Cryptography Extensions Volume I
299 - const: zkn
301 The standard Zkn NIST algorithm suite extensions as ratified in
302 version 1.0 of RISC-V Cryptography Extensions Volume I
305 - const: zknd
308 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
311 - const: zkne
314 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
317 - const: zknh
320 ratified in version 1.0 of RISC-V Cryptography Extensions Volume I
323 - const: zkr
326 1.0 of RISC-V Cryptography Extensions Volume I specification.
329 device-tree has been provided.
331 - const: zks
333 The standard Zks ShangMi algorithm suite extensions as ratified in
334 version 1.0 of RISC-V Cryptography Extensions Volume I
337 - const: zksed
340 as ratified in version 1.0 of RISC-V Cryptography Extensions
343 - const: zksh
346 as ratified in version 1.0 of RISC-V Cryptography Extensions
349 - const: zkt
352 in version 1.0 of RISC-V Cryptography Extensions Volume I
355 - const: zicbom
358 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
360 - const: zicbop
362 The standard Zicbop extension for cache-block prefetch instructions
363 as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
364 riscv-CMOs.
366 - const: zicboz
368 The standard Zicboz extension for cache-block zeroing as ratified
369 in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
371 - const: zicntr
374 ratified in the 20191213 version of the unprivileged ISA
377 - const: zicond
380 conditional-select/move operations as ratified in commit 95cf1f9
381 ("Add changes requested by Ved during signoff") of riscv-zicond.
383 - const: zicsr
387 unprivileged ISA specification.
390 special case read-only CSRs, that were moved into the Zicntr and
391 Zihpm extensions after the ratification of the 20191213 version of
394 - const: zifencei
396 The standard Zifencei extension for instruction-fetch fence, as
397 ratified in the 20191213 version of the unprivileged ISA
400 - const: zihintpause
403 commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
405 - const: zihintntl
407 The standard Zihintntl extension for non-temporal locality hints, as
409 riscv-isa-manual.
411 - const: zihpm
414 ratified in the 20191213 version of the unprivileged ISA
417 - const: zimop
420 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
422 - const: ztso
426 riscv-isa-manual.
428 - const: zvbb
430 The standard Zvbb extension for vectored basic bit-manipulation
432 riscv-crypto-spec-vector.adoc") of riscv-crypto.
434 - const: zvbc
438 riscv-crypto-spec-vector.adoc") of riscv-crypto.
440 - const: zve32f
443 in commit 6f702a2 ("Vector extensions are now ratified") of
444 riscv-v-spec.
446 - const: zve32x
449 in commit 6f702a2 ("Vector extensions are now ratified") of
450 riscv-v-spec.
452 - const: zve64d
455 in commit 6f702a2 ("Vector extensions are now ratified") of
456 riscv-v-spec.
458 - const: zve64f
461 in commit 6f702a2 ("Vector extensions are now ratified") of
462 riscv-v-spec.
464 - const: zve64x
467 in commit 6f702a2 ("Vector extensions are now ratified") of
468 riscv-v-spec.
470 - const: zvfh
472 The standard Zvfh extension for vectored half-precision
473 floating-point instructions, as ratified in commit e2ccd05
474 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
476 - const: zvfhmin
478 The standard Zvfhmin extension for vectored minimal half-precision
479 floating-point instructions, as ratified in commit e2ccd05
480 ("Remove draft warnings from Zvfh[min]") of riscv-v-spec.
482 - const: zvkb
484 The standard Zvkb extension for vector cryptography bit-manipulation
486 riscv-crypto-spec-vector.adoc") of riscv-crypto.
488 - const: zvkg
491 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
492 of riscv-crypto.
494 - const: zvkn
497 ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc")
498 of riscv-crypto.
500 - const: zvknc
504 riscv-crypto-spec-vector.adoc") of riscv-crypto.
506 - const: zvkned
510 riscv-crypto-spec-vector.adoc") of riscv-crypto.
512 - const: zvkng
516 riscv-crypto-spec-vector.adoc") of riscv-crypto.
518 - const: zvknha
520 The standard Zvknha extension for NIST suite: vector SHA-2 secure,
521 hash (SHA-256 only) instructions, as ratified in commit
522 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
524 - const: zvknhb
526 The standard Zvknhb extension for NIST suite: vector SHA-2 secure,
527 hash (SHA-256 and SHA-512) instructions, as ratified in commit
528 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
530 - const: zvks
534 riscv-crypto-spec-vector.adoc") of riscv-crypto.
536 - const: zvksc
540 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto.
542 - const: zvksed
546 riscv-crypto-spec-vector.adoc") of riscv-crypto.
548 - const: zvksh
552 riscv-crypto-spec-vector.adoc") of riscv-crypto.
554 - const: zvksg
558 riscv-crypto-spec-vector.adoc") of riscv-crypto.
560 - const: zvkt
562 The standard Zvkt extension for vector data-independent execution
564 riscv-crypto-spec-vector.adoc") of riscv-crypto.
566 - const: xandespmu
571 https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
575 - if:
582 - if:
587 - contains:
589 - contains:
592 - if:
597 - contains:
599 - contains:
602 - if:
611 - if:
613 riscv,isa-extensions:
616 riscv,isa-base:
621 riscv,isa-extensions: