| /freebsd/sys/dev/ath/ |
| H A D | if_ath_tx_edma.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
44 * by the driver - eg, calls to ath_hal_gettsf32().
129 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
130 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
153 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_TX_FIFO_PUSH, in ath_tx_alq_edma_push()
160 * XXX TODO: push an aggregate as a single FIFO slot, even though
161 * it may not meet the TXOP for say, DBA-gated traffic in TDMA mode.
163 * The TX completion code handles a TX FIFO slot having multiple frames,
182 "%s: called; TXQ=%d, fifo.depth=%d, axq_q empty=%d\n", in ath_tx_edma_push_staging_list()
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| H A D | if_ath_rx_edma.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
44 * by the driver - eg, calls to ath_hal_gettsf32().
129 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
130 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
137 * + Make sure the FIFO is correctly flushed and reinitialised
139 * + Verify multi-descriptor frames work!
146 * XXX shuffle the function orders so these pre-declarations aren't
161 struct ath_hal *ah = sc->sc_ah; in ath_edma_stoprecv()
175 sc->sc_rx_stopped = 1; in ath_edma_stoprecv()
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| /freebsd/sys/contrib/device-tree/Bindings/dma/stm32/ |
| H A D | st,stm32-dma3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/stm32/st,stm32-dma3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 depending on its hardware configuration.
14 Its hardware configuration registers allow to dynamically expose its features.
22 described in "#dma-cells" property description below, using a three-cell
26 - Amelie Delaunay <amelie.delaunay@foss.st.com>
29 - $ref: /schemas/dma/dma-controller.yaml#
33 const: st,stm32mp25-dma3
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| /freebsd/sys/dev/uart/ |
| H A D | uart_if.m | 1 #-
36 # The UART hardware interface. The core UART code is hardware independent.
37 # The details of the hardware are abstracted by the UART hardware interface.
52 # attach() - attach hardware.
55 # high-level (ie tty) initialization has been done yet.
56 # The intend of this method is to setup the hardware for normal operation.
61 # detach() - detach hardware.
63 # is the first action performed, so even the high-level (ie tty) interface
65 # The intend of this method is to disable the hardware.
70 # flush() - flush FIFOs.
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| H A D | uart_dev_imx.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
62 * slack before over/underrun might seem excessive, the hardware can run at
64 * to get into the interrupt handler and service the fifo.
71 * Low-level UART interface.
98 msg, bas->bsh,
123 * Get the baud rate the hardware is programmed for, then search the in imx_uart_getbaud()
125 * actual rate the hardware is programmed for. It's more comforting to in imx_uart_getbaud()
129 * don't know what u-boot might have set up. in imx_uart_getbaud()
133 rate = bas->rclk / predivs[i]; in imx_uart_getbaud()
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| H A D | uart_dev_pl011.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
74 #define FR_RXFE (1 << 4) /* Receive FIFO/reg empty */
75 #define FR_TXFF (1 << 5) /* Transmit FIFO/reg full */
76 #define FR_RXFF (1 << 6) /* Receive FIFO/reg full */
77 #define FR_TXFE (1 << 7) /* Transmit FIFO/reg empty */
89 #define LCR_H_FEN (1 << 4) /* FIFO mode enable */
99 #define UART_IFLS 0x0d /* FIFO level select register */
130 * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes
132 * RX we set the size to the full hardware capacity so that the uart core
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| /freebsd/sys/dev/mmc/host/ |
| H A D | dwmmc_reg.h | 1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
39 #define SDMMC_CTRL_FIFO_RESET (1 << 1) /* Reset FIFO */
46 #define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */
56 #define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */
58 #define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */
59 #define SDMMC_INTMASK_HLE (1 << 12) /* Hardware locked write err */
60 #define SDMMC_INTMASK_FRUN (1 << 11) /* FIFO underrun/overrun err */
66 #define SDMMC_INTMASK_RXDR (1 << 5) /* Receive FIFO data request */
67 #define SDMMC_INTMASK_TXDR (1 << 4) /* Transmit FIFO data request */
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| /freebsd/share/man/man4/ |
| H A D | uart.4 | 1 .\"-
2 .\" SPDX-License-Identifier: BSD-2-Clause
53 .Bl -tag -compact -width 0x000000
59 set RX FIFO trigger level to ``low'' (NS8250 only)
61 set RX FIFO trigger level to ``medium low'' (NS8250 only)
63 set RX FIFO trigger level to ``medium high'' (default, NS8250 only)
65 set RX FIFO trigger level to ``high'' (NS8250 only)
72 EIA RS-232C (CCITT V.24) serial communications interface.
102 driver has a modular design to allow it to be used on differing hardware and
112 It contains the bus attachments and the low-level interrupt handler.
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| H A D | uftdi.4 | 41 .Bd -ragged -offset indent
50 .Bd -literal -offset indent
59 .Bl -bullet -compact
93 .Bl -tag -width indent
97 Flush the RX FIFO.
99 Flush the TX FIFO.
116 .Bd -literal
156 the point of an error such as FIFO overflow.
158 Set the character which causes a partial FIFO full of data
159 to be returned immediately even if the FIFO is not full.
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| H A D | ath.4 | 1 .\"-
2 .\" Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
39 .Bd -ragged -offset indent
49 .Bd -literal -offset indent
61 IBSS, MBSS, WDS/DWDS TDMA, and host-based access point operation modes.
70 AR5210-based devices support 802.11a operation with transmit speeds
72 AR5211-based devices support 802.11a and 802.11b operation with transmit
75 AR5212-based devices support 802.11a, 802.11b, and 802.11g operation
83 only interoperable with other Atheros-based devices.)
84 AR5212-based and AR5416-based devices also support half- (10MHz) and quarter-width (5MHz) channels.
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | ti,omap-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbo
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| /freebsd/sys/arm/xilinx/ |
| H A D | zy7_qspi.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
31 * This is a driver for the Quad-SPI Flash Controller in the Xilinx
32 * Zynq-7000 SoC.
64 {"xlnx,zynq-qspi-1.0", 1},
98 #define QSPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
99 #define QSPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
101 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
102 #define QSPI_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
103 #define QSPI_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
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| H A D | zy7_spi.c | 1 /*-
54 {"xlnx,zynq-spi-1.0", 1},
55 {"cdns,spi-r1p6", 1},
85 #define SPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
86 #define SPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
88 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
89 #define SPI_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
90 #define SPI_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
92 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
93 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
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| /freebsd/sys/dev/aic7xxx/ |
| H A D | aic79xx.seq | 1 /*-
4 * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
19 * 3. Neither the names of the above-listed copyright holders nor the names
49 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
56 if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) {
60 * interrupt collision on the hardware
98 cmp SCB_NEXT_COMPLETE[1], SCB_LIST_NULL jne . - 1;
122 if ((ahd->bugs & AHD_FAINT_LED_BUG) != 0) {
124 * On Rev A. hardware, the busy LED is only
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| /freebsd/sys/dev/axgbe/ |
| H A D | xgbe-drv.c | 4 * Copyright (c) 2014-2016,2020 Advanced Micro Devices, Inc.
116 #include "xgbe-common.h"
124 return (-EINVAL); in xgbe_calc_rx_buf_size()
128 rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) & in xgbe_calc_rx_buf_size()
129 ~(XGBE_RX_BUF_ALIGN - 1); in xgbe_calc_rx_buf_size()
138 struct xgbe_hw_features *hw_feat = &pdata->hw_feat; in xgbe_get_all_hw_features()
140 DBGPR("-->xgbe_get_all_hw_features\n"); in xgbe_get_all_hw_features()
148 hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR); in xgbe_get_all_hw_features()
150 /* Hardware feature register 0 */ in xgbe_get_all_hw_features()
151 hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL); in xgbe_get_all_hw_features()
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| /freebsd/sys/contrib/device-tree/Bindings/timestamp/ |
| H A D | nvidia,tegra194-hte.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Tegra on chip generic hardware timestamping engine (HTE) provider
10 - Dipen Patel <dipenp@nvidia.com>
13 Tegra SoC has two instances of generic hardware timestamping engines (GTE)
16 timestamp (taken from system counter) in its internal hardware FIFO. It has
18 to enable or disable for the hardware timestamping. The GTE GPIO monitors
24 - nvidia,tegra194-gte-aon
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| /freebsd/sys/dev/igc/ |
| H A D | igc_base.c | 1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
14 * igc_acquire_phy_base - Acquire rights to access PHY
25 if (hw->bus.func == IGC_FUNC_1) in igc_acquire_phy_base()
28 return hw->mac.ops.acquire_swfw_sync(hw, mask); in igc_acquire_phy_base()
32 * igc_release_phy_base - Release rights to access PHY
43 if (hw->bus.func == IGC_FUNC_1) in igc_release_phy_base()
46 hw->mac.ops.release_swfw_sync(hw, mask); in igc_release_phy_base()
50 * igc_init_hw_base - Initialize hardware
53 * This inits the hardware readying it for operation.
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| /freebsd/sys/dev/usb/controller/ |
| H A D | uss820dci.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
36 #define USS820_TXDAT 0x00 /* Transmit FIFO data */
38 #define USS820_TXCNTL 0x01 /* Transmit FIFO byte count low */
41 #define USS820_TXCNTH 0x02 /* Transmit FIFO byte count high */
45 #define USS820_TXCON 0x03 /* USB transmit FIFO control */
56 #define USS820_TXCON_TXCLR 0x80 /* Transmit FIFO clear */
58 #define USS820_TXFLG 0x04 /* Transmit FIFO flag (Read Only) */
67 #define USS820_RXDAT 0x05 /* Receive FIFO data */
69 #define USS820_RXCNTL 0x06 /* Receive FIFO byte count low */
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| /freebsd/sys/dev/jme/ |
| H A D | if_jmevar.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
63 #define JME_TX_DESC_HIWAT (JME_TX_RING_CNT - (((JME_TX_RING_CNT) * 3) / 10))
71 (JME_JUMBO_FRAMELEN - sizeof(struct ether_vlan_header) - \
72 ETHER_HDR_LEN - ETHER_CRC_LEN)
74 (ETHER_MAX_LEN + sizeof(struct ether_vlan_header) - \
75 ETHER_HDR_LEN - ETHER_CRC_LEN)
78 * is larger than its FIFO size(2K). It's also good idea to not
79 * use jumbo frame if hardware is running at half-duplex media.
80 * Because the jumbo frame may not fit into the Tx FIFO,
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | cirrus,madera.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
14 interfacing to external hardware and to provide logic outputs to other devices.
30 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
33 pin-settings:
40 '-pins$':
43 - $ref: pincfg-node.yaml#
44 - $ref: pinmux-node.yaml#
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_m2s.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
84 * 00 - No pending tasks
98 * 0 - Log is enabled.
99 * 1 - Log is masked.
125 /* [0x28] M2S data FIFO status */
127 /* [0x2c] M2S header FIFO status */
129 /* [0x30] M2S unack FIFO status */
134 * [0x38] M2S prefetch FIFO status.
139 * [0x3c] M2S completion FIFO status.
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| H A D | al_hal_udma_regs_s2m.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
86 * 00 - No pending tasks
100 * 0 - Log is enable
101 * 1 - Log is masked.
127 /* [0x28] S2M stream data FIFO status */
129 /* [0x2c] S2M stream header FIFO status */
131 /* [0x30] S2M AXI data FIFO status */
133 /* [0x34] S2M unack FIFO status */
138 * [0x3c] S2M prefetch FIFO status.
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| /freebsd/sys/contrib/device-tree/Bindings/spi/ |
| H A D | spi-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Brown <broonie@kernel.org>
20 pattern: "^spi(@.*|-([0-9]|[1-9][0-9]+))?$"
22 "#address-cells":
25 "#size-cells":
28 cs-gpios:
32 increased automatically with max(cs-gpios, hardware chip selects).
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| /freebsd/sys/dev/ichiic/ |
| H A D | ig4_reg.h | 40 * https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/4th-gen-core-family-mobile-i-o-datasheet.pdf
42 * This is a from-scratch driver under the BSD license using the Intel data
61 * Register width is 32-bits
87 #define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshol
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| /freebsd/sys/contrib/device-tree/Bindings/ptp/ |
| H A D | fsl,ptp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Frank Li <Frank.Li@nxp.com>
15 - enum:
16 - fsl,etsec-ptp
17 - fsl,fman-ptp-timer
18 - fsl,dpaa2-ptp
19 - items:
20 - const: pci1957,ee02
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