Lines Matching +full:hardware +full:- +full:fifo
1 /*-
6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
39 #define SDMMC_CTRL_FIFO_RESET (1 << 1) /* Reset FIFO */
46 #define SDMMC_CLKENA_LP (1 << 16) /* Low-power mode */
56 #define SDMMC_INTMASK_EBE (1 << 15) /* End-bit error */
58 #define SDMMC_INTMASK_SBE (1 << 13) /* Start-bit error */
59 #define SDMMC_INTMASK_HLE (1 << 12) /* Hardware locked write err */
60 #define SDMMC_INTMASK_FRUN (1 << 11) /* FIFO underrun/overrun err */
66 #define SDMMC_INTMASK_RXDR (1 << 5) /* Receive FIFO data request */
67 #define SDMMC_INTMASK_TXDR (1 << 4) /* Transmit FIFO data request */
95 #define SDMMC_STATUS_FIFO_FULL (1 << 3) /* FIFO full */
96 #define SDMMC_STATUS_FIFO_EMPTY (1 << 2) /* FIFO empty */
97 #define SDMMC_FIFOTH 0x4C /* FIFO Threshold Watermark Register */
99 #define SDMMC_FIFOTH_RXWMARK_S 16 /* FIFO threshold watermark level */
100 #define SDMMC_FIFOTH_TXWMARK_S 0 /* FIFO threshold watermark level */
104 #define SDMMC_TBBCNT 0x60 /* Transferred Host to BIU-FIFO Byte Count */
108 #define SDMMC_HCON 0x70 /* Hardware Configuration Register */
109 #define SDMMC_UHS_REG 0x74 /* UHS-1 Register */
111 #define SDMMC_RST_N 0x78 /* Hardware Reset Register */
134 #define SDMMC_DATA 0x200 /* Data FIFO Access */
149 /* Platform-specific defines */