1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
74 #define	FR_RXFE		(1 << 4)	/* Receive FIFO/reg empty */
75 #define	FR_TXFF		(1 << 5)	/* Transmit FIFO/reg full */
76 #define	FR_RXFF		(1 << 6)	/* Receive FIFO/reg full */
77 #define	FR_TXFE		(1 << 7)	/* Transmit FIFO/reg empty */
89 #define	LCR_H_FEN	(1 << 4)	/* FIFO mode enable */
99 #define	UART_IFLS	0x0d		/* FIFO level select register */
130  * The hardware FIFOs are 16 bytes each on rev 2 and earlier hardware, 32 bytes
132  * RX we set the size to the full hardware capacity so that the uart core
133  * allocates enough buffer space to hold a complete fifo full of incoming data.
145  * FIXME: actual register size is SoC-dependent, we need to handle it
148 	bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
150 	bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
153  * Low-level UART interface.
177 	 * this tabel. The PL011 IP is always 32-bits wide and should be shifted  in uart_pl011_probe()
178 	 * 2 to match the 4-byte size of the data. QEMU reported these values  in uart_pl011_probe()
182 	 * In additon, other hardware vendors also reported this value  in uart_pl011_probe()
191 	if (bas->regshft == 0 || bas->regiowidth == 1) {  in uart_pl011_probe()
192 		bas->regshft = 2;  in uart_pl011_probe()
193 		bas->regiowidth = 4;  in uart_pl011_probe()
241 	if (bas->rclk != 0 && baudrate != 0) {  in uart_pl011_param()
242 		baud = bas->rclk * 4 / baudrate;  in uart_pl011_param()
251 	/* Set rx and tx fifo levels. */  in uart_pl011_param()
265 	if (bas->rclk == 0 && baudrate > 0 && bas->rclk_guess) {  in uart_pl011_param()
270 		bas->rclk = (div * baudrate) / 4;  in uart_pl011_param()
309 	/* Wait when TX FIFO full. Push character otherwise. */  in uart_pl011_putc()
335  * High-level UART interface.
410 	bas = &sc->sc_bas;  in uart_pl011_bus_attach()
413 	psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY);  in uart_pl011_bus_attach()
414 	__uart_setreg(bas, UART_IMSC, psc->imsc);  in uart_pl011_bus_attach()
449 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_ioctl()
460 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_ioctl()
474 	bas = &sc->sc_bas;  in uart_pl011_bus_ipend()
476 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_ipend()
487 		if (sc->sc_txbusy)  in uart_pl011_bus_ipend()
491 		__uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY);  in uart_pl011_bus_ipend()
494 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_ipend()
504 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_param()
505 	uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity);  in uart_pl011_bus_param()
506 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_param()
519 	 * The FIFO sizes vary depending on hardware; rev 2 and below have 16  in uart_pl011_bus_hwrev_fdt()
520 	 * byte FIFOs, rev 3 and up are 32 byte.  The hardware rev is in the  in uart_pl011_bus_hwrev_fdt()
523 	 * FIFOs.  We check for both the old freebsd-historic and the proper  in uart_pl011_bus_hwrev_fdt()
524 	 * bindings-defined compatible strings for bcm2835, and also check the  in uart_pl011_bus_hwrev_fdt()
528 	if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") ||  in uart_pl011_bus_hwrev_fdt()
529 	    ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) {  in uart_pl011_bus_hwrev_fdt()
532 		node = ofw_bus_get_node(sc->sc_dev);  in uart_pl011_bus_hwrev_fdt()
533 		if (OF_getencprop(node, "arm,primecell-periphid", &periphid,  in uart_pl011_bus_hwrev_fdt()
539 	return (-1);  in uart_pl011_bus_hwrev_fdt()
548 	hwrev = -1;  in uart_pl011_bus_probe()
554 		hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4;  in uart_pl011_bus_probe()
557 		sc->sc_rxfifosz = FIFO_RX_SIZE_R2;  in uart_pl011_bus_probe()
558 		sc->sc_txfifosz = FIFO_TX_SIZE_R2;  in uart_pl011_bus_probe()
560 		sc->sc_rxfifosz = FIFO_RX_SIZE_R3;  in uart_pl011_bus_probe()
561 		sc->sc_txfifosz = FIFO_TX_SIZE_R3;  in uart_pl011_bus_probe()
564 	device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");  in uart_pl011_bus_probe()
576 	bas = &sc->sc_bas;  in uart_pl011_bus_receive()
577 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_receive()
584 			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;  in uart_pl011_bus_receive()
599 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_receive()
619 	bas = &sc->sc_bas;  in uart_pl011_bus_transmit()
620 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_transmit()
622 	for (i = 0; i < sc->sc_txdatasz; i++) {  in uart_pl011_bus_transmit()
623 		__uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);  in uart_pl011_bus_transmit()
628 	sc->sc_txbusy = 1;  in uart_pl011_bus_transmit()
629 	__uart_setreg(bas, UART_IMSC, psc->imsc);  in uart_pl011_bus_transmit()
631 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_transmit()
643 	bas = &sc->sc_bas;  in uart_pl011_bus_grab()
646 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_grab()
647 	__uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL);  in uart_pl011_bus_grab()
648 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_grab()
658 	bas = &sc->sc_bas;  in uart_pl011_bus_ungrab()
661 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_ungrab()
662 	__uart_setreg(bas, UART_IMSC, psc->imsc);  in uart_pl011_bus_ungrab()
663 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_ungrab()