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/linux/arch/arc/boot/dts/
H A Dabilis_tb101.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
H A Dabilis_tb100.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
15 bus-frequency = <166666666>;
18 clock-frequency = <1000000000>;
21 clock-mult = <1>;
22 clock-div = <2>;
25 clock-mult = <1>;
26 clock-div = <6>;
31 pctl_tsin_s0: pctl-tsin-s0 { /* Serial TS-in 0 */
34 pctl_tsin_s1: pctl-tsin-s1 { /* Serial TS-in 1 */
37 pctl_gpio_a: pctl-gpio-a { /* GPIO bank A */
[all …]
/linux/drivers/gpio/
H A Dgpio-aspeed.c1 // SPDX-License-Identifier: GPL-2.0-or-later
10 #include <linux/gpio/aspeed.h>
11 #include <linux/gpio/driver.h>
26 * These two headers aren't meant to be used by GPIO drivers. We need
31 #include <linux/gpio/consumer.h>
34 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
35 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
36 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
38 #define GPIO_G7_IRQ_STS_BASE 0x100
39 #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4)
[all …]
H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
44 #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
[all …]
H A Dgpio-npcm-sgpio.c1 // SPDX-License-Identifier: GPL-2.0
3 * Nuvoton NPCM Serial GPIO Driver
10 #include <linux/gpio/driver.h>
22 #define NPCM_IOXCFG1 0x2A
23 #define NPCM_IOXCFG1_SFT_CLK GENMASK(3, 0)
27 #define NPCM_IOXCTS 0x28
32 #define NPCM_IOXCFG2 0x2B
33 #define NPCM_IOXCFG2_PORT GENMASK(3, 0)
35 #define NPCM_IXOEVCFG_MASK GENMASK(1, 0)
37 #define NPCM_IXOEVCFG_RISING BIT(0)
[all …]
H A Dgpio-raspberrypi-exp.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Raspberry Pi 3 expander GPIO driver
6 * GPIO expander on the VPU.
12 #include <linux/gpio/driver.h>
15 #include <soc/bcm2835/raspberrypi-firmware.h>
17 #define MODULE_NAME "raspberrypi-exp-gpio"
22 #define RPI_EXP_GPIO_DIR_IN 0
33 u32 gpio; member
42 u32 gpio; member
50 u32 gpio; member
[all …]
H A Dgpio-tqmx86.c1 // SPDX-License-Identifier: GPL-2.0
3 * TQ-Systems TQMx86 PLD GPIO driver
12 #include <linux/gpio/driver.h>
23 #define TQMX86_NGPO 4 /* 0-3 - output */
24 #define TQMX86_NGPI 4 /* 4-7 - input */
25 #define TQMX86_DIR_INPUT_MASK 0xf0 /* 0-3 - output, 4-7 - input */
27 #define TQMX86_GPIODD 0 /* GPIO Data Direction Register */
28 #define TQMX86_GPIOD 1 /* GPIO Data Register */
37 #define TQMX86_INT_TRIG_NONE 0
38 #define TQMX86_INT_TRIG_FALLING BIT(0)
[all …]
H A Dgpio-aspeed-sgpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/gpio/driver.h>
22 #define ASPEED_SGPIO_CTRL 0x54
25 #define ASPEED_SGPIO_ENABLE BIT(0)
50 * Note: The "value" register returns the input value when the GPIO is
53 * The "rdata" register returns the output value when the GPIO is
58 .val_regs = 0x0000,
59 .rdata_reg = 0x0070,
60 .irq_regs = 0x0004,
61 .tolerance_regs = 0x0018,
[all …]
/linux/arch/arm64/boot/dts/amlogic/
H A Damlogic-s6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
12 #address-cells = <2>;
13 #size-cells = <0>;
15 cpu0: cpu@0 {
17 compatible = "arm,cortex-a510";
18 reg = <0x0 0x0>;
[all …]
H A Damlogic-s7d.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/amlogic,pinctrl.h>
13 #address-cells = <2>;
14 #size-cells = <0>;
16 cpu0: cpu@0 {
18 compatible = "arm,cortex-a55";
19 reg = <0x0 0x0>;
[all …]
/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-ep9301.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-ep9301.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: EP93xx GPIO controller
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <brgl@bgdev.pl>
12 - Nikita Shubin <nikita.shubin@maquefel.me>
17 - const: cirrus,ep9301-gpio
18 - items:
[all …]
H A Dmrvl-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/gpio/mrvl-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell PXA GPIO controller
10 - Linus Walleij <linus.walleij@linaro.org>
11 - Bartosz Golaszewski <bgolaszewski@baylibre.com>
12 - Rob Herring <robh@kernel.org>
15 - if:
20 - intel,pxa25x-gpio
[all …]
H A Dgpio-davinci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-davinci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO controller for Davinci and keystone devices
10 - Keerthy <j-keerthy@ti.com>
15 - items:
16 - enum:
17 - ti,k2g-gpio
18 - ti,am654-gpio
[all …]
/linux/arch/mips/include/asm/mach-au1x00/
H A Dgpio-au1000.h2 * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200
12 #include <asm/mach-au1x00/au1000.h>
14 /* The default GPIO numberspace as documented in the Alchemy manuals.
15 * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block.
17 #define ALCHEMY_GPIO1_BASE 0
22 #define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1)
23 #define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1)
28 #define AU1000_SYS_TRIOUTRD 0x100
29 #define AU1000_SYS_TRIOUTCLR 0x100
30 #define AU1000_SYS_OUTPUTRD 0x108
[all …]
/linux/arch/arm64/boot/dts/ti/
H A Dk3-am65-iot2050-arduino-connector.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) Siemens AG, 2018-2023
13 pinctrl-names =
15 "d0-uart0-rxd", "d0-gpio", "d0-gpio-pullup", "d0-gpio-pulldown",
16 "d1-uart0-txd", "d1-gpio", "d1-gpio-pullup", "d1-gpio-pulldown",
17 "d2-uart0-ctsn", "d2-gpio", "d2-gpio-pullup", "d2-gpio-pulldown",
18 "d3-uart0-rtsn", "d3-gpio", "d3-gpio-pullup", "d3-gpio-pulldown",
19 "d10-spi0-cs0", "d10-gpio", "d10-gpio-pullup", "d10-gpio-pulldown",
20 "d11-spi0-d0", "d11-gpio", "d11-gpio-pullup", "d11-gpio-pulldown",
21 "d12-spi0-d1", "d12-gpio", "d12-gpio-pullup", "d12-gpio-pulldown",
[all …]
/linux/drivers/ssb/
H A Ddriver_gpio.c3 * GPIO driver
6 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
13 #include <linux/gpio/driver.h>
26 static int ssb_gpio_to_irq(struct gpio_chip *chip, unsigned int gpio) in ssb_gpio_to_irq() argument
30 if (bus->bustype == SSB_BUSTYPE_SSB) in ssb_gpio_to_irq()
31 return irq_find_mapping(bus->irq_domain, gpio); in ssb_gpio_to_irq()
33 return -EINVAL; in ssb_gpio_to_irq()
41 static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned int gpio) in ssb_gpio_chipco_get_value() argument
45 return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio); in ssb_gpio_chipco_get_value()
48 static int ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned int gpio, in ssb_gpio_chipco_set_value() argument
[all …]
/linux/arch/powerpc/boot/dts/
H A Dmucmc52.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright 2006-2007 Secret Lab Technologies Ltd.
12 /* Timer pins that need to be in GPIO mode */
13 &gpt0 { gpio-controller; };
14 &gpt1 { gpio-controller; };
15 &gpt2 { gpio-controller; };
16 &gpt3 { gpio-controller; };
50 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
54 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
70 compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5410-pinctrl.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Exynos5410 SoC pin-mux and pin-config device tree source
9 #include "exynos-pinctrl.h"
12 gpa0: gpa0-gpio-bank {
13 gpio-controller;
14 #gpio-cells = <2>;
16 interrupt-controller;
17 #interrupt-cells = <2>;
20 gpa1: gpa1-gpio-bank {
21 gpio-controller;
[all …]
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa3xx.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 #define MFP_PIN_PXA300(gpio) \ argument
6 ((gpio <= 2) ? (0x00b4 + 4 * gpio) : \
7 (gpio <= 26) ? (0x027c + 4 * (gpio - 3)) : \
8 (gpio <= 98) ? (0x0400 + 4 * (gpio - 27)) : \
9 (gpio <= 127) ? (0x0600 + 4 * (gpio - 99)) : \
10 0)
11 #define MFP_PIN_PXA300_2(gpio) \ argument
12 ((gpio <= 1) ? (0x674 + 4 * gpio) : \
13 (gpio <= 6) ? (0x2dc + 4 * gpio) : \
[all …]
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/hi3670-clock.h>
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
19 compatible = "arm,psci-0.2";
24 #address-cells = <2>;
25 #size-cells = <0>;
27 cpu-map {
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3620.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
[all …]
/linux/arch/arm64/boot/dts/lg/
H A Dlg131x.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <0>;
21 cpu0: cpu@0 {
23 compatible = "arm,cortex-a53";
[all …]
/linux/drivers/pinctrl/
H A Dpinctrl-th1520.c1 // SPDX-License-Identifier: GPL-2.0
3 * Pinctrl driver for the T-Head TH1520 SoC
26 #include <linux/pinctrl/pinconf-generic.h>
41 #define TH1520_PADCFG_DS GENMASK(3, 0)
48 #define TH1520_PAD_MUXDATA GENMASK(29, 0)
67 return thp->base + 4 * (pin / 2); in th1520_padcfg()
72 return 16 * (pin & BIT(0)); in th1520_padcfg_shift()
78 return thp->base + 0x400 + 4 * (pin / 8); in th1520_muxcfg()
83 return 4 * (pin & GENMASK(2, 0)); in th1520_muxcfg_shift()
114 [TH1520_MUX_GPIO] = "gpio",
[all …]
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/
H A Dbase.c29 nvkm_gpio_drive(struct nvkm_gpio *gpio, int idx, int line, int dir, int out) in nvkm_gpio_drive() argument
31 return gpio->func->drive(gpio, line, dir, out); in nvkm_gpio_drive()
35 nvkm_gpio_sense(struct nvkm_gpio *gpio, int idx, int line) in nvkm_gpio_sense() argument
37 return gpio->func->sense(gpio, line); in nvkm_gpio_sense()
41 nvkm_gpio_reset(struct nvkm_gpio *gpio, u8 func) in nvkm_gpio_reset() argument
43 if (gpio->func->reset) in nvkm_gpio_reset()
44 gpio->func->reset(gpio, func); in nvkm_gpio_reset()
48 nvkm_gpio_find(struct nvkm_gpio *gpio, int idx, u8 tag, u8 line, in nvkm_gpio_find() argument
51 struct nvkm_device *device = gpio->subdev.device; in nvkm_gpio_find()
52 struct nvkm_bios *bios = device->bios; in nvkm_gpio_find()
[all …]
/linux/arch/mips/boot/dts/pic32/
H A Dpic32mzda.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
5 #include <dt-bindings/clock/microchip,pic32-clock.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
11 interrupt-parent = <&evic>;
33 #address-cells = <1>;
34 #size-cells = <0>;
36 cpu@0 {
43 compatible = "microchip,pic32mzda-infra";
[all …]

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