Lines Matching +full:gpio +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2012-2013 HiSilicon Ltd.
6 * Copyright (C) 2012-2013 Linaro Ltd.
11 #include <dt-bindings/clock/hi3620-clock.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <26000000>;
29 clock-output-names = "apb_pclk";
33 #address-cells = <1>;
34 #size-cells = <0>;
35 enable-method = "hisilicon,hi3620-smp";
37 cpu@0 {
39 compatible = "arm,cortex-a9";
40 reg = <0x0>;
41 next-level-cache = <&L2>;
45 compatible = "arm,cortex-a9";
48 next-level-cache = <&L2>;
52 compatible = "arm,cortex-a9";
55 next-level-cache = <&L2>;
59 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
66 amba-bus {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 compatible = "simple-bus";
71 interrupt-parent = <&gic>;
72 ranges = <0 0xfc000000 0x2000000>;
74 L2: cache-controller {
75 compatible = "arm,pl310-cache";
76 reg = <0x100000 0x100000>;
77 interrupts = <0 15 4>;
78 cache-unified;
79 cache-level = <2>;
82 gic: interrupt-controller@1000 {
83 compatible = "arm,cortex-a9-gic";
84 #interrupt-cells = <3>;
85 #address-cells = <0>;
86 interrupt-controller;
88 reg = <0x1000 0x1000>, <0x100 0x100>;
91 sysctrl: system-controller@802000 {
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x802000 0x1000>;
96 reg = <0x802000 0x1000>;
98 smp-offset = <0x31c>;
99 resume-offset = <0x308>;
100 reboot-offset = <0x4>;
102 clock: clock@0 {
103 compatible = "hisilicon,hi3620-clock";
104 reg = <0 0x10000>;
105 #clock-cells = <1>;
111 reg = <0x800000 0x1000>;
113 interrupts = <0 0 4>, <0 1 4>;
117 clock-names = "timer0clk", "timer1clk", "apb_pclk";
123 reg = <0x801000 0x1000>;
125 interrupts = <0 2 4>, <0 3 4>;
129 clock-names = "timer0clk", "timer1clk", "apb_pclk";
135 reg = <0xa01000 0x1000>;
137 interrupts = <0 4 4>, <0 5 4>;
141 clock-names = "timer0lck", "timer1clk", "apb_pclk";
147 reg = <0xa02000 0x1000>;
149 interrupts = <0 6 4>, <0 7 4>;
153 clock-names = "timer0clk", "timer1clk", "apb_pclk";
159 reg = <0xa03000 0x1000>;
161 interrupts = <0 96 4>, <0 97 4>;
165 clock-names = "timer0clk", "timer1clk", "apb_pclk";
170 compatible = "arm,cortex-a9-twd-timer";
171 reg = <0x600 0x20>;
172 interrupts = <1 13 0xf01>;
177 reg = <0xb00000 0x1000>;
178 interrupts = <0 20 4>;
180 clock-names = "uartclk", "apb_pclk";
186 reg = <0xb01000 0x1000>;
187 interrupts = <0 21 4>;
189 clock-names = "uartclk", "apb_pclk";
195 reg = <0xb02000 0x1000>;
196 interrupts = <0 22 4>;
198 clock-names = "uartclk", "apb_pclk";
204 reg = <0xb03000 0x1000>;
205 interrupts = <0 23 4>;
207 clock-names = "uartclk", "apb_pclk";
213 reg = <0xb04000 0x1000>;
214 interrupts = <0 24 4>;
216 clock-names = "uartclk", "apb_pclk";
220 gpio0: gpio@806000 {
222 reg = <0x806000 0x1000>;
223 interrupts = <0 64 0x4>;
224 gpio-controller;
225 #gpio-cells = <2>;
226 gpio-ranges = < &pmx0 2 0 1 &pmx0 3 0 1 &pmx0 4 0 1
227 &pmx0 5 0 1 &pmx0 6 1 1 &pmx0 7 2 1>;
228 interrupt-controller;
229 #interrupt-cells = <2>;
231 clock-names = "apb_pclk";
234 gpio1: gpio@807000 {
236 reg = <0x807000 0x1000>;
237 interrupts = <0 65 0x4>;
238 gpio-controller;
239 #gpio-cells = <2>;
240 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
243 interrupt-controller;
244 #interrupt-cells = <2>;
246 clock-names = "apb_pclk";
249 gpio2: gpio@808000 {
251 reg = <0x808000 0x1000>;
252 interrupts = <0 66 0x4>;
253 gpio-controller;
254 #gpio-cells = <2>;
255 gpio-ranges = < &pmx0 0 7 1 &pmx0 1 8 1 &pmx0 2 9 1
258 interrupt-controller;
259 #interrupt-cells = <2>;
261 clock-names = "apb_pclk";
264 gpio3: gpio@809000 {
266 reg = <0x809000 0x1000>;
267 interrupts = <0 67 0x4>;
268 gpio-controller;
269 #gpio-cells = <2>;
270 gpio-ranges = < &pmx0 0 3 1 &pmx0 1 3 1 &pmx0 2 3 1
273 interrupt-controller;
274 #interrupt-cells = <2>;
276 clock-names = "apb_pclk";
279 gpio4: gpio@80a000 {
281 reg = <0x80a000 0x1000>;
282 interrupts = <0 68 0x4>;
283 gpio-controller;
284 #gpio-cells = <2>;
285 gpio-ranges = < &pmx0 0 11 1 &pmx0 1 11 1 &pmx0 2 11 1
288 interrupt-controller;
289 #interrupt-cells = <2>;
291 clock-names = "apb_pclk";
294 gpio5: gpio@80b000 {
296 reg = <0x80b000 0x1000>;
297 interrupts = <0 69 0x4>;
298 gpio-controller;
299 #gpio-cells = <2>;
300 gpio-ranges = < &pmx0 0 14 1 &pmx0 1 15 1 &pmx0 2 16 1
303 interrupt-controller;
304 #interrupt-cells = <2>;
306 clock-names = "apb_pclk";
309 gpio6: gpio@80c000 {
311 reg = <0x80c000 0x1000>;
312 interrupts = <0 70 0x4>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 gpio-ranges = < &pmx0 0 16 1 &pmx0 1 16 1 &pmx0 2 17 1
318 interrupt-controller;
319 #interrupt-cells = <2>;
321 clock-names = "apb_pclk";
324 gpio7: gpio@80d000 {
326 reg = <0x80d000 0x1000>;
327 interrupts = <0 71 0x4>;
328 gpio-controller;
329 #gpio-cells = <2>;
330 gpio-ranges = < &pmx0 0 19 1 &pmx0 1 20 1 &pmx0 2 21 1
333 interrupt-controller;
334 #interrupt-cells = <2>;
336 clock-names = "apb_pclk";
339 gpio8: gpio@80e000 {
341 reg = <0x80e000 0x1000>;
342 interrupts = <0 72 0x4>;
343 gpio-controller;
344 #gpio-cells = <2>;
345 gpio-ranges = < &pmx0 0 27 1 &pmx0 1 28 1 &pmx0 2 29 1
348 interrupt-controller;
349 #interrupt-cells = <2>;
351 clock-names = "apb_pclk";
354 gpio9: gpio@80f000 {
356 reg = <0x80f000 0x1000>;
357 interrupts = <0 73 0x4>;
358 gpio-controller;
359 #gpio-cells = <2>;
360 gpio-ranges = < &pmx0 0 35 1 &pmx0 1 36 1 &pmx0 2 37 1
363 interrupt-controller;
364 #interrupt-cells = <2>;
366 clock-names = "apb_pclk";
369 gpio10: gpio@810000 {
371 reg = <0x810000 0x1000>;
372 interrupts = <0 74 0x4>;
373 gpio-controller;
374 #gpio-cells = <2>;
375 gpio-ranges = < &pmx0 2 43 1 &pmx0 3 44 1 &pmx0 4 45 1
377 interrupt-controller;
378 #interrupt-cells = <2>;
380 clock-names = "apb_pclk";
383 gpio11: gpio@811000 {
385 reg = <0x811000 0x1000>;
386 interrupts = <0 75 0x4>;
387 gpio-controller;
388 #gpio-cells = <2>;
389 gpio-ranges = < &pmx0 0 47 1 &pmx0 1 47 1 &pmx0 2 47 1
392 interrupt-controller;
393 #interrupt-cells = <2>;
395 clock-names = "apb_pclk";
398 gpio12: gpio@812000 {
400 reg = <0x812000 0x1000>;
401 interrupts = <0 76 0x4>;
402 gpio-controller;
403 #gpio-cells = <2>;
404 gpio-ranges = < &pmx0 0 49 1 &pmx0 1 50 1 &pmx0 2 49 1
407 interrupt-controller;
408 #interrupt-cells = <2>;
410 clock-names = "apb_pclk";
413 gpio13: gpio@813000 {
415 reg = <0x813000 0x1000>;
416 interrupts = <0 77 0x4>;
417 gpio-controller;
418 #gpio-cells = <2>;
419 gpio-ranges = < &pmx0 0 51 1 &pmx0 1 51 1 &pmx0 2 53 1
422 interrupt-controller;
423 #interrupt-cells = <2>;
425 clock-names = "apb_pclk";
428 gpio14: gpio@814000 {
430 reg = <0x814000 0x1000>;
431 interrupts = <0 78 0x4>;
432 gpio-controller;
433 #gpio-cells = <2>;
434 gpio-ranges = < &pmx0 0 57 1 &pmx0 1 97 1 &pmx0 2 97 1
437 interrupt-controller;
438 #interrupt-cells = <2>;
440 clock-names = "apb_pclk";
443 gpio15: gpio@815000 {
445 reg = <0x815000 0x1000>;
446 interrupts = <0 79 0x4>;
447 gpio-controller;
448 #gpio-cells = <2>;
449 gpio-ranges = < &pmx0 0 61 1 &pmx0 1 62 1 &pmx0 2 62 1
452 interrupt-controller;
453 #interrupt-cells = <2>;
455 clock-names = "apb_pclk";
458 gpio16: gpio@816000 {
460 reg = <0x816000 0x1000>;
461 interrupts = <0 80 0x4>;
462 gpio-controller;
463 #gpio-cells = <2>;
464 gpio-ranges = < &pmx0 0 66 1 &pmx0 1 67 1 &pmx0 2 68 1
467 interrupt-controller;
468 #interrupt-cells = <2>;
470 clock-names = "apb_pclk";
473 gpio17: gpio@817000 {
475 reg = <0x817000 0x1000>;
476 interrupts = <0 81 0x4>;
477 gpio-controller;
478 #gpio-cells = <2>;
479 gpio-ranges = < &pmx0 0 74 1 &pmx0 1 75 1 &pmx0 2 76 1
482 interrupt-controller;
483 #interrupt-cells = <2>;
485 clock-names = "apb_pclk";
488 gpio18: gpio@818000 {
490 reg = <0x818000 0x1000>;
491 interrupts = <0 82 0x4>;
492 gpio-controller;
493 #gpio-cells = <2>;
494 gpio-ranges = < &pmx0 0 82 1 &pmx0 1 83 1 &pmx0 2 83 1
497 interrupt-controller;
498 #interrupt-cells = <2>;
500 clock-names = "apb_pclk";
503 gpio19: gpio@819000 {
505 reg = <0x819000 0x1000>;
506 interrupts = <0 83 0x4>;
507 gpio-controller;
508 #gpio-cells = <2>;
509 gpio-ranges = < &pmx0 0 87 1 &pmx0 1 87 1 &pmx0 2 88 1
511 interrupt-controller;
512 #interrupt-cells = <2>;
514 clock-names = "apb_pclk";
517 gpio20: gpio@81a000 {
519 reg = <0x81a000 0x1000>;
520 interrupts = <0 84 0x4>;
521 gpio-controller;
522 #gpio-cells = <2>;
523 gpio-ranges = < &pmx0 0 89 1 &pmx0 1 89 1 &pmx0 2 90 1
525 interrupt-controller;
526 #interrupt-cells = <2>;
528 clock-names = "apb_pclk";
531 gpio21: gpio@81b000 {
533 reg = <0x81b000 0x1000>;
534 interrupts = <0 85 0x4>;
535 gpio-controller;
536 #gpio-cells = <2>;
537 gpio-ranges = < &pmx0 3 94 1 &pmx0 7 96 1>;
538 interrupt-controller;
539 #interrupt-cells = <2>;
541 clock-names = "apb_pclk";
545 compatible = "pinctrl-single";
546 reg = <0x803000 0x188>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #pinctrl-cells = <1>;
550 #gpio-range-cells = <3>;
552 pinctrl-single,register-width = <32>;
553 pinctrl-single,function-mask = <7>;
554 /* pin base, nr pins & gpio function */
555 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
556 &range 12 1 0 &range 13 29 1
557 &range 43 1 0 &range 44 49 1
560 range: gpio-range {
561 #pinctrl-single,gpio-range-cells = <3>;
566 compatible = "pinconf-single";
567 reg = <0x803800 0x2dc>;
568 #address-cells = <1>;
569 #size-cells = <0>;
570 #pinctrl-cells = <1>;
572 pinctrl-single,register-width = <32>;