Lines Matching +full:gpio +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/gpio/aspeed.h>
10 #include <linux/gpio/driver.h>
25 * These two headers aren't meant to be used by GPIO drivers. We need
30 #include <linux/gpio/consumer.h>
33 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
34 #define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
35 #define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
37 #define GPIO_G7_IRQ_STS_BASE 0x100
38 #define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4)
39 #define GPIO_G7_CTRL_REG_BASE 0x180
40 #define GPIO_G7_CTRL_REG_OFFSET(x) (GPIO_G7_CTRL_REG_BASE + (x) * 0x4)
41 #define GPIO_G7_CTRL_OUT_DATA BIT(0)
75 * represents disabled debouncing for the GPIO. Any other value for an element
97 uint16_t val_regs; /* +0: Rd: read input value, Wr: set write latch
98 * +4: Rd/Wr: Direction (0=in, 1=out)
109 * line even when the GPIO is configured as an output. Since
118 static const int debounce_timers[4] = { 0x00, 0x50, 0x54, 0x58 };
119 static const int g7_debounce_timers[4] = { 0x00, 0x00, 0x04, 0x08 };
126 * Array Index 0: No debounce timer is set;
128 * Array Index 1: Debounce setting #2 is set to 1, and debounce setting #1 is set to 0.
129 * Array Value: offset for configuring debounce timer 0 (g4: 0x50, g7: 0x00)
130 * Array Index 2: Debounce setting #2 is set to 0, and debounce setting #1 is set to 1.
131 * Array Value: offset for configuring debounce timer 1 (g4: 0x54, g7: 0x04)
133 * Array Value: offset for configuring debounce timer 2 (g4: 0x58, g7: 0x8)
141 .val_regs = 0x0000,
142 .rdata_reg = 0x00c0,
143 .irq_regs = 0x0008,
144 .debounce_regs = 0x0040,
145 .tolerance_regs = 0x001c,
146 .cmdsrc_regs = 0x0060,
149 .val_regs = 0x0020,
150 .rdata_reg = 0x00c4,
151 .irq_regs = 0x0028,
152 .debounce_regs = 0x0048,
153 .tolerance_regs = 0x003c,
154 .cmdsrc_regs = 0x0068,
157 .val_regs = 0x0070,
158 .rdata_reg = 0x00c8,
159 .irq_regs = 0x0098,
160 .debounce_regs = 0x00b0,
161 .tolerance_regs = 0x00ac,
162 .cmdsrc_regs = 0x0090,
165 .val_regs = 0x0078,
166 .rdata_reg = 0x00cc,
167 .irq_regs = 0x00e8,
168 .debounce_regs = 0x0100,
169 .tolerance_regs = 0x00fc,
170 .cmdsrc_regs = 0x00e0,
173 .val_regs = 0x0080,
174 .rdata_reg = 0x00d0,
175 .irq_regs = 0x0118,
176 .debounce_regs = 0x0130,
177 .tolerance_regs = 0x012c,
178 .cmdsrc_regs = 0x0110,
181 .val_regs = 0x0088,
182 .rdata_reg = 0x00d4,
183 .irq_regs = 0x0148,
184 .debounce_regs = 0x0160,
185 .tolerance_regs = 0x015c,
186 .cmdsrc_regs = 0x0140,
189 .val_regs = 0x01E0,
190 .rdata_reg = 0x00d8,
191 .irq_regs = 0x0178,
192 .debounce_regs = 0x0190,
193 .tolerance_regs = 0x018c,
194 .cmdsrc_regs = 0x0170,
197 .val_regs = 0x01e8,
198 .rdata_reg = 0x00dc,
199 .irq_regs = 0x01a8,
200 .debounce_regs = 0x01c0,
201 .tolerance_regs = 0x01bc,
202 .cmdsrc_regs = 0x01a0,
223 void (*reg_bit_set)(struct aspeed_gpio *gpio, unsigned int offset,
225 bool (*reg_bit_get)(struct aspeed_gpio *gpio, unsigned int offset,
227 int (*reg_bank_get)(struct aspeed_gpio *gpio, unsigned int offset,
229 void (*privilege_ctrl)(struct aspeed_gpio *gpio, unsigned int offset, int owner);
230 void (*privilege_init)(struct aspeed_gpio *gpio);
231 bool (*copro_request)(struct aspeed_gpio *gpio, unsigned int offset);
232 void (*copro_release)(struct aspeed_gpio *gpio, unsigned int offset);
235 #define GPIO_VAL_VALUE 0x00
236 #define GPIO_VAL_DIR 0x04
238 #define GPIO_IRQ_ENABLE 0x00
239 #define GPIO_IRQ_TYPE0 0x04
240 #define GPIO_IRQ_TYPE1 0x08
241 #define GPIO_IRQ_TYPE2 0x0c
242 #define GPIO_IRQ_STATUS 0x10
244 #define GPIO_DEBOUNCE_SEL1 0x00
245 #define GPIO_DEBOUNCE_SEL2 0x04
247 #define GPIO_CMDSRC_0 0x00
248 #define GPIO_CMDSRC_1 0x04
249 #define GPIO_CMDSRC_ARM 0
255 static void __iomem *aspeed_gpio_g4_bank_reg(struct aspeed_gpio *gpio, in aspeed_gpio_g4_bank_reg() argument
261 return gpio->base + bank->val_regs + GPIO_VAL_VALUE; in aspeed_gpio_g4_bank_reg()
263 return gpio->base + bank->rdata_reg; in aspeed_gpio_g4_bank_reg()
265 return gpio->base + bank->val_regs + GPIO_VAL_DIR; in aspeed_gpio_g4_bank_reg()
267 return gpio->base + bank->irq_regs + GPIO_IRQ_ENABLE; in aspeed_gpio_g4_bank_reg()
269 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE0; in aspeed_gpio_g4_bank_reg()
271 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE1; in aspeed_gpio_g4_bank_reg()
273 return gpio->base + bank->irq_regs + GPIO_IRQ_TYPE2; in aspeed_gpio_g4_bank_reg()
275 return gpio->base + bank->irq_regs + GPIO_IRQ_STATUS; in aspeed_gpio_g4_bank_reg()
277 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL1; in aspeed_gpio_g4_bank_reg()
279 return gpio->base + bank->debounce_regs + GPIO_DEBOUNCE_SEL2; in aspeed_gpio_g4_bank_reg()
281 return gpio->base + bank->tolerance_regs; in aspeed_gpio_g4_bank_reg()
283 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_0; in aspeed_gpio_g4_bank_reg()
285 return gpio->base + bank->cmdsrc_regs + GPIO_CMDSRC_1; in aspeed_gpio_g4_bank_reg()
319 return 0; in aspeed_gpio_g7_reg_mask()
324 #define GPIO_OFFSET(x) ((x) & 0x1f)
337 return !(props->input || props->output); in is_bank_props_sentinel()
341 struct aspeed_gpio *gpio, unsigned int offset) in find_bank_props() argument
343 const struct aspeed_bank_props *props = gpio->config->props; in find_bank_props()
346 if (props->bank == GPIO_BANK(offset)) in find_bank_props()
354 static inline bool have_gpio(struct aspeed_gpio *gpio, unsigned int offset) in have_gpio() argument
356 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_gpio()
358 if (offset >= gpio->chip.ngpio) in have_gpio()
361 return (!props || ((props->input | props->output) & GPIO_BIT(offset))); in have_gpio()
364 static inline bool have_input(struct aspeed_gpio *gpio, unsigned int offset) in have_input() argument
366 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_input()
368 return !props || (props->input & GPIO_BIT(offset)); in have_input()
374 static inline bool have_output(struct aspeed_gpio *gpio, unsigned int offset) in have_output() argument
376 const struct aspeed_bank_props *props = find_bank_props(gpio, offset); in have_output()
378 return !props || (props->output & GPIO_BIT(offset)); in have_output()
381 static void aspeed_gpio_change_cmd_source(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) in aspeed_gpio_change_cmd_source() argument
383 if (gpio->config->llops->privilege_ctrl) in aspeed_gpio_change_cmd_source()
384 gpio->config->llops->privilege_ctrl(gpio, offset, cmdsrc); in aspeed_gpio_change_cmd_source()
387 static bool aspeed_gpio_copro_request(struct aspeed_gpio *gpio, in aspeed_gpio_copro_request() argument
390 if (gpio->config->llops->copro_request) in aspeed_gpio_copro_request()
391 return gpio->config->llops->copro_request(gpio, offset); in aspeed_gpio_copro_request()
396 static void aspeed_gpio_copro_release(struct aspeed_gpio *gpio, in aspeed_gpio_copro_release() argument
399 if (gpio->config->llops->copro_release) in aspeed_gpio_copro_release()
400 gpio->config->llops->copro_release(gpio, offset); in aspeed_gpio_copro_release()
403 static bool aspeed_gpio_support_copro(struct aspeed_gpio *gpio) in aspeed_gpio_support_copro() argument
405 return gpio->config->llops->copro_request && gpio->config->llops->copro_release && in aspeed_gpio_support_copro()
406 gpio->config->llops->privilege_ctrl && gpio->config->llops->privilege_init; in aspeed_gpio_support_copro()
411 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_get() local
413 return gpio->config->llops->reg_bit_get(gpio, offset, reg_val); in aspeed_gpio_get()
419 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in __aspeed_gpio_set() local
421 gpio->config->llops->reg_bit_set(gpio, offset, reg_val, val); in __aspeed_gpio_set()
423 gpio->config->llops->reg_bit_get(gpio, offset, reg_val); in __aspeed_gpio_set()
429 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_set() local
433 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set()
434 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set()
439 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set()
440 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set()
445 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_dir_in() local
449 if (!have_input(gpio, offset)) in aspeed_gpio_dir_in()
450 return -ENOTSUPP; in aspeed_gpio_dir_in()
452 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_in()
454 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_in()
455 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0); in aspeed_gpio_dir_in()
457 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_in()
459 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_in()
461 return 0; in aspeed_gpio_dir_in()
467 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_dir_out() local
471 if (!have_output(gpio, offset)) in aspeed_gpio_dir_out()
472 return -ENOTSUPP; in aspeed_gpio_dir_out()
474 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_dir_out()
476 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_dir_out()
478 gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 1); in aspeed_gpio_dir_out()
481 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_dir_out()
482 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_dir_out()
484 return 0; in aspeed_gpio_dir_out()
489 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_get_direction() local
493 if (!have_input(gpio, offset)) in aspeed_gpio_get_direction()
496 if (!have_output(gpio, offset)) in aspeed_gpio_get_direction()
499 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_get_direction()
501 val = gpio->config->llops->reg_bit_get(gpio, offset, reg_dir); in aspeed_gpio_get_direction()
503 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_get_direction()
509 struct aspeed_gpio **gpio, in irqd_to_aspeed_gpio_data() argument
520 return -ENOTSUPP; in irqd_to_aspeed_gpio_data()
522 *gpio = internal; in irqd_to_aspeed_gpio_data()
524 return 0; in irqd_to_aspeed_gpio_data()
529 struct aspeed_gpio *gpio; in aspeed_gpio_irq_ack() local
534 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); in aspeed_gpio_irq_ack()
538 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_ack()
539 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_ack()
541 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); in aspeed_gpio_irq_ack()
544 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_ack()
545 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_ack()
550 struct aspeed_gpio *gpio; in aspeed_gpio_irq_set_mask() local
555 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); in aspeed_gpio_irq_set_mask()
561 gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
563 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
564 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_irq_set_mask()
566 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set); in aspeed_gpio_irq_set_mask()
569 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_irq_set_mask()
570 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_irq_set_mask()
574 gpiochip_disable_irq(&gpio->chip, irqd_to_hwirq(d)); in aspeed_gpio_irq_set_mask()
589 u32 type0 = 0; in aspeed_gpio_set_type()
590 u32 type1 = 0; in aspeed_gpio_set_type()
591 u32 type2 = 0; in aspeed_gpio_set_type()
593 struct aspeed_gpio *gpio; in aspeed_gpio_set_type() local
598 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); in aspeed_gpio_set_type()
600 return -EINVAL; in aspeed_gpio_set_type()
620 return -EINVAL; in aspeed_gpio_set_type()
623 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_set_type()
624 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_set_type()
626 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, type0); in aspeed_gpio_set_type()
627 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, type1); in aspeed_gpio_set_type()
628 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, type2); in aspeed_gpio_set_type()
631 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_set_type()
632 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_set_type()
636 return 0; in aspeed_gpio_set_type()
645 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_gpio_irq_handler() local
649 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_irq_handler()
650 for (i = 0; i < banks; i++) { in aspeed_gpio_irq_handler()
651 reg = gpio->config->llops->reg_bank_get(gpio, i * 32, reg_irq_status); in aspeed_gpio_irq_handler()
654 generic_handle_domain_irq(gc->irq.domain, i * 32 + p); in aspeed_gpio_irq_handler()
664 struct aspeed_gpio *gpio = gpiochip_get_data(gc); in aspeed_init_irq_valid_mask() local
665 const struct aspeed_bank_props *props = gpio->config->props; in aspeed_init_irq_valid_mask()
669 const unsigned long int input = props->input; in aspeed_init_irq_valid_mask()
671 /* Pretty crummy approach, but similar to GPIO core */ in aspeed_init_irq_valid_mask()
673 unsigned int i = props->bank * 32 + offset; in aspeed_init_irq_valid_mask()
675 if (i >= gpio->chip.ngpio) in aspeed_init_irq_valid_mask()
688 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in aspeed_gpio_reset_tolerance() local
692 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
693 copro = aspeed_gpio_copro_request(gpio, offset); in aspeed_gpio_reset_tolerance()
695 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); in aspeed_gpio_reset_tolerance()
698 aspeed_gpio_copro_release(gpio, offset); in aspeed_gpio_reset_tolerance()
699 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_reset_tolerance()
701 return 0; in aspeed_gpio_reset_tolerance()
707 return -ENODEV; in aspeed_gpio_request()
717 static int usecs_to_cycles(struct aspeed_gpio *gpio, unsigned long usecs, in usecs_to_cycles() argument
724 rate = clk_get_rate(gpio->clk); in usecs_to_cycles()
726 return -ENOTSUPP; in usecs_to_cycles()
732 return -ERANGE; in usecs_to_cycles()
737 return 0; in usecs_to_cycles()
740 /* Call under gpio->lock */
741 static int register_allocated_timer(struct aspeed_gpio *gpio, in register_allocated_timer() argument
744 if (WARN(gpio->offset_timer[offset] != 0, in register_allocated_timer()
746 offset, gpio->offset_timer[offset])) in register_allocated_timer()
747 return -EINVAL; in register_allocated_timer()
749 if (WARN(gpio->timer_users[timer] == UINT_MAX, in register_allocated_timer()
751 return -EPERM; in register_allocated_timer()
753 gpio->offset_timer[offset] = timer; in register_allocated_timer()
754 gpio->timer_users[timer]++; in register_allocated_timer()
756 return 0; in register_allocated_timer()
759 /* Call under gpio->lock */
760 static int unregister_allocated_timer(struct aspeed_gpio *gpio, in unregister_allocated_timer() argument
763 if (WARN(gpio->offset_timer[offset] == 0, in unregister_allocated_timer()
765 return -EINVAL; in unregister_allocated_timer()
767 if (WARN(gpio->timer_users[gpio->offset_timer[offset]] == 0, in unregister_allocated_timer()
769 gpio->offset_timer[offset])) in unregister_allocated_timer()
770 return -EINVAL; in unregister_allocated_timer()
772 gpio->timer_users[gpio->offset_timer[offset]]--; in unregister_allocated_timer()
773 gpio->offset_timer[offset] = 0; in unregister_allocated_timer()
775 return 0; in unregister_allocated_timer()
778 /* Call under gpio->lock */
779 static inline bool timer_allocation_registered(struct aspeed_gpio *gpio, in timer_allocation_registered() argument
782 return gpio->offset_timer[offset] > 0; in timer_allocation_registered()
785 /* Call under gpio->lock */
786 static void configure_timer(struct aspeed_gpio *gpio, unsigned int offset, in configure_timer() argument
792 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel1, !!(timer & BIT(1))); in configure_timer()
793 gpio->config->llops->reg_bit_set(gpio, offset, reg_debounce_sel2, !!(timer & BIT(0))); in configure_timer()
799 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in enable_debounce() local
805 if (!gpio->clk) in enable_debounce()
806 return -EINVAL; in enable_debounce()
808 rc = usecs_to_cycles(gpio, usecs, &requested_cycles); in enable_debounce()
809 if (rc < 0) { in enable_debounce()
810 dev_warn(chip->parent, "Failed to convert %luus to cycles at %luHz: %d\n", in enable_debounce()
811 usecs, clk_get_rate(gpio->clk), rc); in enable_debounce()
815 raw_spin_lock_irqsave(&gpio->lock, flags); in enable_debounce()
817 if (timer_allocation_registered(gpio, offset)) { in enable_debounce()
818 rc = unregister_allocated_timer(gpio, offset); in enable_debounce()
819 if (rc < 0) in enable_debounce()
824 for (i = 1; i < gpio->config->debounce_timers_num; i++) { in enable_debounce()
827 cycles = ioread32(gpio->base + gpio->config->debounce_timers_array[i]); in enable_debounce()
832 if (i == gpio->config->debounce_timers_num) { in enable_debounce()
839 for (j = 1; j < ARRAY_SIZE(gpio->timer_users); j++) { in enable_debounce()
840 if (gpio->timer_users[j] == 0) in enable_debounce()
844 if (j == ARRAY_SIZE(gpio->timer_users)) { in enable_debounce()
845 dev_warn(chip->parent, in enable_debounce()
849 rc = -EPERM; in enable_debounce()
857 configure_timer(gpio, offset, 0); in enable_debounce()
863 iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_array[i]); in enable_debounce()
866 if (WARN(i == 0, "Cannot register index of disabled timer\n")) { in enable_debounce()
867 rc = -EINVAL; in enable_debounce()
871 register_allocated_timer(gpio, offset, i); in enable_debounce()
872 configure_timer(gpio, offset, i); in enable_debounce()
875 raw_spin_unlock_irqrestore(&gpio->lock, flags); in enable_debounce()
882 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in disable_debounce() local
886 raw_spin_lock_irqsave(&gpio->lock, flags); in disable_debounce()
888 rc = unregister_allocated_timer(gpio, offset); in disable_debounce()
890 configure_timer(gpio, offset, 0); in disable_debounce()
892 raw_spin_unlock_irqrestore(&gpio->lock, flags); in disable_debounce()
900 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in set_debounce() local
902 if (!have_debounce(gpio, offset)) in set_debounce()
903 return -ENOTSUPP; in set_debounce()
925 /* Return -ENOTSUPP to trigger emulation, as per datasheet */ in aspeed_gpio_set_config()
926 return -ENOTSUPP; in aspeed_gpio_set_config()
930 return -ENOTSUPP; in aspeed_gpio_set_config()
934 * aspeed_gpio_copro_set_ops - Sets the callbacks used for handshaking with
935 * the coprocessor for shared GPIO banks
944 return 0; in aspeed_gpio_copro_set_ops()
949 * aspeed_gpio_copro_grab_gpio - Mark a GPIO used by the coprocessor. The entire
952 * @desc: The GPIO to be marked
953 * @vreg_offset: If non-NULL, returns the value register offset in the GPIO space
954 * @dreg_offset: If non-NULL, returns the data latch register offset in the GPIO space
955 * @bit: If non-NULL, returns the bit number of the GPIO in the registers
961 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in aspeed_gpio_copro_grab_gpio() local
962 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); in aspeed_gpio_copro_grab_gpio()
966 if (!aspeed_gpio_support_copro(gpio)) in aspeed_gpio_copro_grab_gpio()
967 return -EOPNOTSUPP; in aspeed_gpio_copro_grab_gpio()
969 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
970 gpio->cf_copro_bankmap = kzalloc(gpio->chip.ngpio >> 3, GFP_KERNEL); in aspeed_gpio_copro_grab_gpio()
971 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_grab_gpio()
972 return -ENOMEM; in aspeed_gpio_copro_grab_gpio()
973 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_grab_gpio()
974 return -EINVAL; in aspeed_gpio_copro_grab_gpio()
977 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
980 if (gpio->cf_copro_bankmap[bindex] == 0xff) { in aspeed_gpio_copro_grab_gpio()
981 rc = -EIO; in aspeed_gpio_copro_grab_gpio()
984 gpio->cf_copro_bankmap[bindex]++; in aspeed_gpio_copro_grab_gpio()
987 if (gpio->cf_copro_bankmap[bindex] == 1) in aspeed_gpio_copro_grab_gpio()
988 aspeed_gpio_change_cmd_source(gpio, offset, in aspeed_gpio_copro_grab_gpio()
992 *vreg_offset = bank->val_regs; in aspeed_gpio_copro_grab_gpio()
994 *dreg_offset = bank->rdata_reg; in aspeed_gpio_copro_grab_gpio()
998 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_grab_gpio()
1004 * aspeed_gpio_copro_release_gpio - Unmark a GPIO used by the coprocessor.
1005 * @desc: The GPIO to be marked
1010 struct aspeed_gpio *gpio = gpiochip_get_data(chip); in aspeed_gpio_copro_release_gpio() local
1011 int rc = 0, bindex, offset = gpio_chip_hwgpio(desc); in aspeed_gpio_copro_release_gpio()
1014 if (!aspeed_gpio_support_copro(gpio)) in aspeed_gpio_copro_release_gpio()
1015 return -EOPNOTSUPP; in aspeed_gpio_copro_release_gpio()
1017 if (!gpio->cf_copro_bankmap) in aspeed_gpio_copro_release_gpio()
1018 return -ENXIO; in aspeed_gpio_copro_release_gpio()
1020 if (offset < 0 || offset > gpio->chip.ngpio) in aspeed_gpio_copro_release_gpio()
1021 return -EINVAL; in aspeed_gpio_copro_release_gpio()
1024 raw_spin_lock_irqsave(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1027 if (gpio->cf_copro_bankmap[bindex] == 0) { in aspeed_gpio_copro_release_gpio()
1028 rc = -EIO; in aspeed_gpio_copro_release_gpio()
1031 gpio->cf_copro_bankmap[bindex]--; in aspeed_gpio_copro_release_gpio()
1034 if (gpio->cf_copro_bankmap[bindex] == 0) in aspeed_gpio_copro_release_gpio()
1035 aspeed_gpio_change_cmd_source(gpio, offset, in aspeed_gpio_copro_release_gpio()
1038 raw_spin_unlock_irqrestore(&gpio->lock, flags); in aspeed_gpio_copro_release_gpio()
1045 struct aspeed_gpio *gpio; in aspeed_gpio_irq_print_chip() local
1048 rc = irqd_to_aspeed_gpio_data(d, &gpio, &offset); in aspeed_gpio_irq_print_chip()
1052 seq_puts(p, dev_name(gpio->dev)); in aspeed_gpio_irq_print_chip()
1065 static void aspeed_g4_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g4_reg_bit_set() argument
1069 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); in aspeed_g4_reg_bit_set()
1073 temp = gpio->dcache[GPIO_BANK(offset)]; in aspeed_g4_reg_bit_set()
1083 gpio->dcache[GPIO_BANK(offset)] = temp; in aspeed_g4_reg_bit_set()
1087 static bool aspeed_g4_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g4_reg_bit_get() argument
1091 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); in aspeed_g4_reg_bit_get()
1096 static int aspeed_g4_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g4_reg_bank_get() argument
1100 void __iomem *addr = aspeed_gpio_g4_bank_reg(gpio, bank, reg); in aspeed_g4_reg_bank_get()
1105 return -EOPNOTSUPP; in aspeed_g4_reg_bank_get()
1108 static void aspeed_g4_privilege_ctrl(struct aspeed_gpio *gpio, unsigned int offset, int cmdsrc) in aspeed_g4_privilege_ctrl() argument
1111 * The command source register is only valid in bits 0, 8, 16, and 24, so we use in aspeed_g4_privilege_ctrl()
1112 * (offset & ~(0x7)) to ensure that reg_bits_set always targets a valid bit. in aspeed_g4_privilege_ctrl()
1115 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc1, !!(cmdsrc & BIT(1))); in aspeed_g4_privilege_ctrl()
1116 /* Then Source 0 */ in aspeed_g4_privilege_ctrl()
1117 aspeed_g4_reg_bit_set(gpio, offset & ~(0x7), reg_cmdsrc0, !!(cmdsrc & BIT(0))); in aspeed_g4_privilege_ctrl()
1120 static void aspeed_g4_privilege_init(struct aspeed_gpio *gpio) in aspeed_g4_privilege_init() argument
1125 for (i = 0; i < DIV_ROUND_UP(gpio->chip.ngpio, 32); i++) { in aspeed_g4_privilege_init()
1126 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 0, GPIO_CMDSRC_ARM); in aspeed_g4_privilege_init()
1127 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 8, GPIO_CMDSRC_ARM); in aspeed_g4_privilege_init()
1128 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 16, GPIO_CMDSRC_ARM); in aspeed_g4_privilege_init()
1129 aspeed_g4_privilege_ctrl(gpio, (i << 5) + 24, GPIO_CMDSRC_ARM); in aspeed_g4_privilege_init()
1133 static bool aspeed_g4_copro_request(struct aspeed_gpio *gpio, unsigned int offset) in aspeed_g4_copro_request() argument
1135 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_g4_copro_request()
1137 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_g4_copro_request()
1139 if (!copro_ops->request_access) in aspeed_g4_copro_request()
1143 copro_ops->request_access(copro_data); in aspeed_g4_copro_request()
1146 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_ARM); in aspeed_g4_copro_request()
1149 gpio->dcache[GPIO_BANK(offset)] = aspeed_g4_reg_bank_get(gpio, offset, reg_rdata); in aspeed_g4_copro_request()
1154 static void aspeed_g4_copro_release(struct aspeed_gpio *gpio, unsigned int offset) in aspeed_g4_copro_release() argument
1156 if (!copro_ops || !gpio->cf_copro_bankmap) in aspeed_g4_copro_release()
1158 if (!gpio->cf_copro_bankmap[offset >> 3]) in aspeed_g4_copro_release()
1160 if (!copro_ops->release_access) in aspeed_g4_copro_release()
1164 aspeed_g4_privilege_ctrl(gpio, offset, GPIO_CMDSRC_COLDFIRE); in aspeed_g4_copro_release()
1167 copro_ops->release_access(copro_data); in aspeed_g4_copro_release()
1180 static void aspeed_g7_reg_bit_set(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g7_reg_bit_set() argument
1184 void __iomem *addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); in aspeed_g7_reg_bit_set()
1193 static bool aspeed_g7_reg_bit_get(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g7_reg_bit_get() argument
1199 addr = gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset); in aspeed_g7_reg_bit_get()
1206 return 0; in aspeed_g7_reg_bit_get()
1209 static int aspeed_g7_reg_bank_get(struct aspeed_gpio *gpio, unsigned int offset, in aspeed_g7_reg_bank_get() argument
1215 addr = gpio->base + GPIO_G7_IRQ_STS_OFFSET(offset >> 5); in aspeed_g7_reg_bank_get()
1218 return -EOPNOTSUPP; in aspeed_g7_reg_bank_get()
1236 * { .input = 0xffffffff, .output = 0xffffffff }
1241 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1242 { 6, 0x0000000f, 0x0fffff0f }, /* Y/Z/AA/AB, two 4-GPIO holes */
1247 /* 220 for simplicity, really 216 with two 4-GPIO holes, four at end */
1259 { 5, 0xffffffff, 0x0000ffff }, /* U/V/W/X */
1260 { 6, 0x0fffffff, 0x0fffffff }, /* Y/Z/AA/AB, 4-GPIO hole */
1261 { 7, 0x000000ff, 0x000000ff }, /* AC */
1266 /* 232 for simplicity, actual number is 228 (4-GPIO hole in GPIOAB) */
1278 {4, 0xffffffff, 0x00ffffff}, /* Q/R/S/T */
1279 {5, 0xffffffff, 0xffffff00}, /* U/V/W/X */
1280 {6, 0x0000ffff, 0x0000ffff}, /* Y/Z */
1301 { 1, 0x0fffffff, 0x0fffffff }, /* E/F/G/H, 4-GPIO hole */
1302 { 6, 0x00ffffff, 0x00ff0000 }, /* Y/Z/AA */
1309 * 216 for simplicity, actual number is 212 (4-GPIO hole in GPIOH)
1323 { .compatible = "aspeed,ast2400-gpio", .data = &ast2400_config, },
1324 { .compatible = "aspeed,ast2500-gpio", .data = &ast2500_config, },
1325 { .compatible = "aspeed,ast2600-gpio", .data = &ast2600_config, },
1326 { .compatible = "aspeed,ast2700-gpio", .data = &ast2700_config, },
1335 struct aspeed_gpio *gpio; in aspeed_gpio_probe() local
1339 gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL); in aspeed_gpio_probe()
1340 if (!gpio) in aspeed_gpio_probe()
1341 return -ENOMEM; in aspeed_gpio_probe()
1343 gpio->base = devm_platform_ioremap_resource(pdev, 0); in aspeed_gpio_probe()
1344 if (IS_ERR(gpio->base)) in aspeed_gpio_probe()
1345 return PTR_ERR(gpio->base); in aspeed_gpio_probe()
1347 gpio->dev = &pdev->dev; in aspeed_gpio_probe()
1349 raw_spin_lock_init(&gpio->lock); in aspeed_gpio_probe()
1351 gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node); in aspeed_gpio_probe()
1353 return -EINVAL; in aspeed_gpio_probe()
1355 gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL); in aspeed_gpio_probe()
1356 if (IS_ERR(gpio->clk)) { in aspeed_gpio_probe()
1357 dev_warn(&pdev->dev, in aspeed_gpio_probe()
1359 gpio->clk = NULL; in aspeed_gpio_probe()
1362 gpio->config = gpio_id->data; in aspeed_gpio_probe()
1364 if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get || in aspeed_gpio_probe()
1365 !gpio->config->llops->reg_bank_get) in aspeed_gpio_probe()
1366 return -EINVAL; in aspeed_gpio_probe()
1368 gpio->chip.parent = &pdev->dev; in aspeed_gpio_probe()
1369 err = of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpio); in aspeed_gpio_probe()
1370 gpio->chip.ngpio = (u16) ngpio; in aspeed_gpio_probe()
1372 gpio->chip.ngpio = gpio->config->nr_gpios; in aspeed_gpio_probe()
1373 gpio->chip.direction_input = aspeed_gpio_dir_in; in aspeed_gpio_probe()
1374 gpio->chip.direction_output = aspeed_gpio_dir_out; in aspeed_gpio_probe()
1375 gpio->chip.get_direction = aspeed_gpio_get_direction; in aspeed_gpio_probe()
1376 gpio->chip.request = aspeed_gpio_request; in aspeed_gpio_probe()
1377 gpio->chip.free = aspeed_gpio_free; in aspeed_gpio_probe()
1378 gpio->chip.get = aspeed_gpio_get; in aspeed_gpio_probe()
1379 gpio->chip.set = aspeed_gpio_set; in aspeed_gpio_probe()
1380 gpio->chip.set_config = aspeed_gpio_set_config; in aspeed_gpio_probe()
1381 gpio->chip.label = dev_name(&pdev->dev); in aspeed_gpio_probe()
1382 gpio->chip.base = -1; in aspeed_gpio_probe()
1384 if (gpio->config->require_dcache) { in aspeed_gpio_probe()
1386 banks = DIV_ROUND_UP(gpio->chip.ngpio, 32); in aspeed_gpio_probe()
1387 gpio->dcache = devm_kcalloc(&pdev->dev, banks, sizeof(u32), GFP_KERNEL); in aspeed_gpio_probe()
1388 if (!gpio->dcache) in aspeed_gpio_probe()
1389 return -ENOMEM; in aspeed_gpio_probe()
1393 for (i = 0; i < banks; i++) in aspeed_gpio_probe()
1394 gpio->dcache[i] = in aspeed_gpio_probe()
1395 gpio->config->llops->reg_bank_get(gpio, (i << 5), reg_rdata); in aspeed_gpio_probe()
1398 if (gpio->config->llops->privilege_init) in aspeed_gpio_probe()
1399 gpio->config->llops->privilege_init(gpio); in aspeed_gpio_probe()
1402 irq = platform_get_irq(pdev, 0); in aspeed_gpio_probe()
1403 if (irq < 0) in aspeed_gpio_probe()
1405 gpio->irq = irq; in aspeed_gpio_probe()
1406 girq = &gpio->chip.irq; in aspeed_gpio_probe()
1409 girq->parent_handler = aspeed_gpio_irq_handler; in aspeed_gpio_probe()
1410 girq->num_parents = 1; in aspeed_gpio_probe()
1411 girq->parents = devm_kcalloc(&pdev->dev, 1, sizeof(*girq->parents), GFP_KERNEL); in aspeed_gpio_probe()
1412 if (!girq->parents) in aspeed_gpio_probe()
1413 return -ENOMEM; in aspeed_gpio_probe()
1414 girq->parents[0] = gpio->irq; in aspeed_gpio_probe()
1415 girq->default_type = IRQ_TYPE_NONE; in aspeed_gpio_probe()
1416 girq->handler = handle_bad_irq; in aspeed_gpio_probe()
1417 girq->init_valid_mask = aspeed_init_irq_valid_mask; in aspeed_gpio_probe()
1419 gpio->offset_timer = in aspeed_gpio_probe()
1420 devm_kzalloc(&pdev->dev, gpio->chip.ngpio, GFP_KERNEL); in aspeed_gpio_probe()
1421 if (!gpio->offset_timer) in aspeed_gpio_probe()
1422 return -ENOMEM; in aspeed_gpio_probe()
1424 rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio); in aspeed_gpio_probe()
1425 if (rc < 0) in aspeed_gpio_probe()
1428 return 0; in aspeed_gpio_probe()
1441 MODULE_DESCRIPTION("Aspeed GPIO Driver");