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Searched +full:eyeq5 +full:- +full:olb (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/soc/mobileye/
H A Dmobileye,eyeq5-olb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Grégory Clement <gregory.clement@bootlin.com>
11 - Théo Lebrun <theo.lebrun@bootlin.com>
12 - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
15 OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks,
16 resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a single
22 - enum:
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/linux/Documentation/devicetree/bindings/i2c/
H A Dst,nomadik-i2c.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/st,nomadik-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 STn8815. It was part of the prototype STn8500 which then became ST-Ericsson
15 - Linus Walleij <linus.walleij@linaro.org>
23 - st,nomadik-i2c
24 - mobileye,eyeq5-i2c
25 - mobileye,eyeq6h-i2c
27 - compatible
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/linux/drivers/reset/
H A Dreset-eyeq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Reset driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
5 * Controllers live in a shared register region called OLB. EyeQ5 and EyeQ6L
6 * have a single OLB instance for a single reset controller. EyeQ6H has seven
7 * OLB instances; three host reset controllers.
13 * Domain types define expected behavior: one-register-per-reset,
14 * one-bit-per-reset, status detection method, busywait duration, etc.
16 * We use eqr_ as prefix, as-in "EyeQ Reset", but way shorter.
18 * Known resets in EyeQ5 domain 0 (type EQR_EYEQ5_SARCR):
27 * Known resets in EyeQ5 domain 1 (type EQR_EYEQ5_ACRP):
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
12 via GPIOs or SoC-internal reset controller modules.
75 This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
79 Registers are located in a shared register region called OLB. EyeQ6H
87 GPIOs. Typically for OF platforms this driver expects "reset-gpios"
90 If compiled as module, it will be called reset-gpio.
132 Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
208 Raspberry Pi 4's co-processor controls some of the board's HW
211 interfacing with RPi4's co-processor and model these firmware
242 - Altera SoCFPGAs
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/linux/drivers/clk/
H A Dclk-eyeq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PLL clock driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
6 * - Read-only PLLs, all derived from the same main crystal clock.
7 * - It also exposes divider clocks, those are children to PLLs.
8 * - Fixed factor clocks, children to PLLs.
11 * shared region called OLB. Some PLLs and fixed-factors are initialised early
14 * We use eqc_ as prefix, as-in "EyeQ Clock", but way shorter.
23 #define pr_fmt(fmt) "clk-eyeq: " fmt
29 #include <linux/clk-provider.h>
34 #include <linux/io-64-nonatomic-hi-lo.h>
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
59 Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs
88 These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
98 multi-function device has one fixed-rate oscillator, clocked
129 be pre-programmed to support other configurations and features not yet
178 This driver supports TI CDCE706 programmable 3-PLL clock synthesizer.
196 For example, the CDCE925 contains two PLLs with spread-spectrum
206 tristate "Clock driver for CS2000 Fractional-N Clock Synthesizer & Clock Multiplier"
235 This driver provides clocks found on Mobileye EyeQ5, EyeQ6L and Eye6H
236 SoCs. Controllers live in shared register regions called OLB. Driver
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/linux/drivers/i2c/busses/
H A Di2c-nomadik.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2009 ST-Ericsson SA
9 * The Mobileye EyeQ5 and EyeQ6H platforms are also supported; they use
11 * - The memory bus only supports 32-bit accesses.
12 * - (only EyeQ5) A register must be configured for the I2C speed mode;
13 * it is located in a shared register region called OLB.
35 #define DRIVER_NAME "nmk-i2c"
74 #define I2C_MCR_A7 GENMASK(7, 1) /* 7-bit address */
75 #define I2C_MCR_EA10 GENMASK(10, 8) /* 10-bit Extended address */
88 /* Baud-rate counter register (BRCR) */
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/linux/arch/mips/boot/dts/mobileye/
H A Deyeq5-pins.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Default pin configuration for Mobileye EyeQ5 boards. We mostly create one
8 &olb {
9 timer0_pins: timer0-pins {
13 timer1_pins: timer1-pins {
17 timer2_pins: timer2-pins {
21 pps0_pins: pps0-pin {
25 pps1_pins: pps1-pin {
29 timer5_ext_pins: timer5-ext-pins {
33 timer5_ext_input_pins: timer5-ext-input-pins {
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/linux/drivers/pinctrl/
H A Dpinctrl-eyeq5.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Pinctrl driver for the Mobileye EyeQ5 platform.
5 * The registers are located in a syscon region called OLB. There are two pin
7 * pull-down, pull-up, drive strength and muxing.
10 * that is pin-dependent. Functions are declared statically in this driver.
15 * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter.
33 #include <linux/pinctrl/pinconf-generic.h>
39 #include "pinctrl-utils.h"
205 void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg]; in eq5p_update_bits()
213 u32 val = readl(pctrl->base + eq5p_regs[bank][reg]); in eq5p_test_bit()
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