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/linux/Documentation/devicetree/bindings/dma/
H A Dfsl,edma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/fsl,edma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale enhanced Direct Memory Access(eDMA) Controller
10 The eDMA channels have multiplex capability by programmable
11 memory-mapped registers. channels are split into two groups, called
16 - Peng Fan <peng.fan@nxp.com>
21 - enum:
22 - fsl,vf610-edma
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/linux/drivers/dma/
H A Dfsl-edma-main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * drivers/dma/fsl-edma.c
5 * Copyright 2013-2014 Freescale Semiconductor, Inc.
8 * Driver for the Freescale eDMA engine with flexible channel multiplexing
9 * capability for DMA request sources. The eDMA block can be found on some
13 #include <dt-bindings/dma/fsl-edma.h>
20 #include <linux/dma-mapping.h>
25 #include "fsl-edma-common.h"
31 vchan_synchronize(&fsl_chan->vchan); in fsl_edma_synchronize()
38 struct edma_regs *regs = &fsl_edma->regs; in fsl_edma_tx_handler()
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H A Dfsl-edma-common.c1 // SPDX-License-Identifier: GPL-2.0+
3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
11 #include <linux/dma-mapping.h>
15 #include "fsl-edma-common.h"
49 spin_lock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
51 if (!fsl_chan->edesc) { in fsl_edma_tx_chan_handler()
53 spin_unlock(&fsl_chan->vchan.lock); in fsl_edma_tx_chan_handler()
57 if (!fsl_chan->edesc->iscyclic) { in fsl_edma_tx_chan_handler()
58 list_del(&fsl_chan->edesc->vdesc.node); in fsl_edma_tx_chan_handler()
59 vchan_cookie_complete(&fsl_chan->edesc->vdesc); in fsl_edma_tx_chan_handler()
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H A Dfsl-edma-common.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2014 Freescale Semiconductor, Inc.
9 #include <linux/dma-direction.h>
11 #include "virt-dma.h"
167 struct fsl_edma_engine *edma; member
226 /* All channel ERR IRQ share one IRQ line */
274 return fsl_chan->edma->drvdata->flags; in fsl_edma_drvflags()
278 _Generic(((_tcd)->__name), \
279 __iomem __le64 : edma_readq(chan->edma, &(_tcd)->__name), \
280 __iomem __le32 : edma_readl(chan->edma, &(_tcd)->__name), \
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/linux/drivers/dma/dw-edma/
H A Ddw-edma-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA PCIe driver
13 #include <linux/dma/edma.h>
14 #include <linux/pci-epf.h>
18 #include "dw-edma-core.h"
40 /* eDMA registers location */
42 /* eDMA memory linked list location */
45 /* eDMA memory data location */
56 /* eDMA registers location */
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H A Ddw-edma-core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
4 * Synopsys DesignWare eDMA core driver
13 #include <linux/err.h>
16 #include <linux/dma/edma.h>
17 #include <linux/dma-mapping.h>
20 #include "dw-edma-core.h"
21 #include "dw-edma-v0-core.h"
22 #include "dw-hdma-v0-core.h"
24 #include "../virt-dma.h"
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/linux/Documentation/devicetree/bindings/pci/
H A Dsnps,dw-pcie-ep.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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H A Drockchip-dw-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Lin <shawn.lin@rock-chips.com>
11 - Simon Xue <xxm@rock-chips.com>
12 - Heiko Stuebner <heiko@sntech.de>
22 - description: AHB clock for PCIe master
23 - description: AHB clock for PCIe slave
24 - description: AHB clock for PCIe dbi
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H A Dsnps,dw-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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/linux/drivers/ata/
H A Dsata_mv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
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/linux/drivers/dma/ti/
H A Dedma.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * TI EDMA DMA engine driver
9 #include <linux/dma-mapping.h>
11 #include <linux/err.h>
26 #include <linux/platform_data/edma.h>
29 #include "../virt-dma.h"
43 /* Offsets for EDMA CC global channel registers and their shadows */
67 /* Offsets for EDMA CC global registers */
71 #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
101 #define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
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H A Ddma-crossbar.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
8 #include <linux/err.h>
25 .compatible = "ti,dra7-dma-crossbar",
29 .compatible = "ti,am335x-edma-crossbar",
44 u32 dma_requests; /* number of DMA requests on eDMA */
60 writeb_relaxed(val, iomem + (63 - event % 4)); in ti_am335x_xbar_write()
71 map->mux_val, map->dma_line); in ti_am335x_xbar_free()
73 ti_am335x_xbar_write(xbar->iomem, map->dma_line, 0); in ti_am335x_xbar_free()
80 struct platform_device *pdev = of_find_device_by_node(ofdma->of_node); in ti_am335x_xbar_route_allocate()
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/linux/Documentation/devicetree/bindings/iommu/
H A Dti,omap-iommu.txt4 - compatible : Should be one of,
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
10 - reg : Address space for the configuration registers
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
19 - ti,#tlb-entries : Number of entries in the translation look-aside buffer.
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/linux/drivers/spi/
H A Dspi-fsl-lpspi.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
23 #include <linux/dma/imx-dma.h>
35 /* The maximum bytes that edma can transfer once.*/
36 #define FSL_LPSPI_MAX_EDMA_BYTES ((1 << 15) - 1)
154 { .compatible = "fsl,imx7ulp-spi", .data = &imx7ulp_lpspi_devtype_data,},
155 { .compatible = "fsl,imx93-spi", .data = &imx93_lpspi_devtype_data,},
156 { .compatible = "nxp,s32g2-lpspi", .data = &s32g_lpspi_devtype_data,},
164 unsigned int val = readl(fsl_lpspi->base + IMX7ULP_RDR); \
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/linux/drivers/pci/controller/dwc/
H A Dpcie-rcar-gen4.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
4 * Copyright (C) 2022-2023 Renesas Electronics Corporation
6 * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be
24 #include "pcie-designware.h"
26 /* Renesas-specific */
95 val = readl(rcar->base + PCIEINTSTS0); in rcar_gen4_pcie_link_up()
103 * -ETIMEDOUT.
125 return -ETIMEDOUT; in rcar_gen4_pcie_speed_change()
137 if (rcar->drvdata->ltssm_control) { in rcar_gen4_pcie_start_link()
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/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for NXP Layerscape-1028A family SoC.
5 * Copyright 2018-2020 NXP
11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
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/linux/drivers/net/wireless/ath/ath9k/
H A Dxmit.c2 * Copyright (c) 2008-2011 Atheros Communications Inc.
17 #include <linux/dma-mapping.h>
33 #define TIME_SYMBOLS_HALFGI(t) (((t) * 5 - 4) / 18)
35 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
49 { 104, 216 }, /* 3: 16-QAM 1/2 */
50 { 156, 324 }, /* 4: 16-QAM 3/4 */
51 { 208, 432 }, /* 5: 64-QAM 2/3 */
52 { 234, 486 }, /* 6: 64-QAM 3/4 */
53 { 260, 540 }, /* 7: 64-QAM 5/6 */
92 struct ieee80211_sta *sta = info->status.status_driver_data[0]; in ath_tx_status()
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/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
8 #include <dt-bindings/bus/ti-sysc.h>
9 #include <dt-bindings/clock/dra7.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/dra.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
20 interrupt-parent = <&crossbar_mpu>;
47 compatible = "arm,armv7-timer";
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/linux/drivers/gpio/
H A Dgpio-davinci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (c) 2006-2007 David Brownell
13 #include <linux/err.h>
43 #define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
73 /*--------------------------------------------------------------------------*/
86 g = d->regs[bank]; in __davinci_direction()
87 spin_lock_irqsave(&d->lock, flags); in __davinci_direction()
88 temp = readl_relaxed(&g->dir); in __davinci_direction()
91 writel_relaxed(mask, value ? &g->set_data : &g->clr_data); in __davinci_direction()
95 writel_relaxed(temp, &g->dir); in __davinci_direction()
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/linux/arch/s390/pci/
H A Dpci_clp.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/err.h>
20 #include <asm/asm-extable.h>
107 zdev->tlb_refresh = response->refresh; in clp_store_query_pci_fngrp()
108 zdev->dma_mask = response->dasm; in clp_store_query_pci_fngrp()
109 zdev->msi_addr = response->msia; in clp_store_query_pci_fngrp()
110 zdev->max_msi = response->noi; in clp_store_query_pci_fngrp()
111 zdev->fmb_update = response->mui; in clp_store_query_pci_fngrp()
112 zdev->version = response->version; in clp_store_query_pci_fngrp()
113 zdev->maxstbl = response->maxstbl; in clp_store_query_pci_fngrp()
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/linux/sound/soc/ti/
H A Ddavinci-mcasp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Multi-channel Audio Serial Port Driver
7 * Author: Nirmal Pandey <n-pandey@ti.com>,
37 #include "edma-pcm.h"
38 #include "sdma-pcm.h"
39 #include "udma-pcm.h"
40 #include "davinci-mcasp.h"
134 void __iomem *reg = mcasp->base + offset; in mcasp_set_bits()
141 void __iomem *reg = mcasp->base + offset; in mcasp_clr_bits()
148 void __iomem *reg = mcasp->base + offset; in mcasp_mod_bits()
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/linux/sound/soc/fsl/
H A Dfsl_xcvr.c1 // SPDX-License-Identifier: GPL-2.0
19 #include "imx-pcm.h"
78 * HDMI2.1 spec defines 6- and 12-channels layout for one bit audio
116 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in fsl_xcvr_arc_mode_put()
117 unsigned int *item = ucontrol->value.enumerated.item; in fsl_xcvr_arc_mode_put()
119 xcvr->arc_mode = snd_soc_enum_item_to_val(e, item[0]); in fsl_xcvr_arc_mode_put()
130 ucontrol->value.enumerated.item[0] = xcvr->arc_mode; in fsl_xcvr_arc_mode_get()
150 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; in fsl_xcvr_type_capds_bytes_info()
151 uinfo->count = FSL_XCVR_CAPDS_SIZE; in fsl_xcvr_type_capds_bytes_info()
162 memcpy(ucontrol->value.bytes.data, xcvr->cap_ds, FSL_XCVR_CAPDS_SIZE); in fsl_xcvr_capds_get()
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/linux/drivers/net/wireless/ath/wil6210/
H A Dtxrx_edma.c1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved.
32 dma_addr_t pa = wil_tx_desc_get_addr_edma(&d->dma); in wil_tx_desc_unmap_edma()
33 u16 dmalen = le16_to_cpu(d->dma.length); in wil_tx_desc_unmap_edma()
35 switch (ctx->mapped_as) { in wil_tx_desc_unmap_edma()
52 if (!wil->srings[i].va) in wil_find_free_sring()
56 return -EINVAL; in wil_find_free_sring()
65 if (!sring || !sring->va) in wil_sring_free()
68 sz = sring->elem_size * sring->size; in wil_sring_free()
71 sz, sring->va, &sring->pa); in wil_sring_free()
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/linux/drivers/tty/serial/
H A Dfsl_lpuart.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2012-2014 Freescale Semiconductor, Inc.
14 #include <linux/dma-mapping.h>
30 /* All registers are 8-bit width */
119 /* 32-bit global registers only for i.MX7ULP/i.MX8x
124 /* 32-bit register definition */
246 #define DRIVER_NAME "fsl-lpuart"
349 { .compatible = "fsl,vf610-lpuart", .data = &vf_data, },
350 { .compatible = "fsl,ls1021a-lpuart", .data = &ls1021a_data, },
351 { .compatible = "fsl,ls1028a-lpuart", .data = &ls1028a_data, },
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/linux/drivers/accel/habanalabs/common/
H A Dfirmware_if.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright 2016-2022 HabanaLabs, Ltd.
45 * hl_fw_version_cmp() - compares the FW version to a specific version
50 * @subminor: sub-minor number of a reference version
52 * Return 1 if FW version greater than the reference version, -1 if it's
57 if (hdev->fw_sw_major_ver != major) in hl_fw_version_cmp()
58 return (hdev->fw_sw_major_ver > major) ? 1 : -1; in hl_fw_version_cmp()
60 if (hdev->fw_sw_minor_ver != minor) in hl_fw_version_cmp()
61 return (hdev->fw_sw_minor_ver > minor) ? 1 : -1; in hl_fw_version_cmp()
63 if (hdev->fw_sw_sub_minor_ver != subminor) in hl_fw_version_cmp()
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