Lines Matching +full:edma +full:- +full:err
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 * Copyright 2017-2021, 2024 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
18 #address-cells = <2>;
19 #size-cells = <2>;
23 compatible = "arm,scmi-shmem";
25 no-map;
30 #address-cells = <1>;
31 #size-cells = <0>;
35 compatible = "arm,cortex-a53";
37 enable-method = "psci";
38 next-level-cache = <&cluster0_l2>;
43 compatible = "arm,cortex-a53";
45 enable-method = "psci";
46 next-level-cache = <&cluster0_l2>;
51 compatible = "arm,cortex-a53";
53 enable-method = "psci";
54 next-level-cache = <&cluster1_l2>;
59 compatible = "arm,cortex-a53";
61 enable-method = "psci";
62 next-level-cache = <&cluster1_l2>;
65 cluster0_l2: l2-cache0 {
67 cache-level = <2>;
68 cache-unified;
71 cluster1_l2: l2-cache1 {
73 cache-level = <2>;
74 cache-unified;
79 compatible = "arm,cortex-a53-pmu";
84 compatible = "arm,armv8-timer";
93 compatible = "arm,scmi-smc";
94 arm,smc-id = <0xc20000fe>;
95 #address-cells = <1>;
96 #size-cells = <0>;
101 #clock-cells = <1>;
106 compatible = "arm,psci-1.0";
112 compatible = "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
118 compatible = "nxp,s32g2-rtc";
122 clock-names = "ipg", "source0";
126 compatible = "nxp,s32g2-siul2-pinctrl";
127 /* MSCR0-MSCR101 registers on siul2_0 */
129 /* MSCR112-MSCR122 registers on siul2_1 */
131 /* MSCR144-MSCR190 registers on siul2_1 */
133 /* IMCR0-IMCR83 registers on siul2_0 */
135 /* IMCR119-IMCR397 registers on siul2_1 */
137 /* IMCR430-IMCR495 registers on siul2_1 */
140 jtag_pins: jtag-pins {
141 jtag-grp0 {
143 input-enable;
144 bias-pull-up;
145 slew-rate = <166>;
148 jtag-grp1 {
150 slew-rate = <166>;
153 jtag-grp2 {
155 input-enable;
156 bias-pull-down;
157 slew-rate = <166>;
160 jtag-grp3 {
166 jtag-grp4 {
168 input-enable;
169 bias-pull-up;
170 slew-rate = <166>;
174 pinctrl_usdhc0: usdhc0grp-pins {
175 usdhc0-grp0 {
178 output-enable;
179 bias-pull-down;
180 slew-rate = <150>;
183 usdhc0-grp1 {
193 output-enable;
194 input-enable;
195 bias-pull-up;
196 slew-rate = <150>;
199 usdhc0-grp2 {
201 output-enable;
202 slew-rate = <150>;
205 usdhc0-grp3 {
207 input-enable;
208 slew-rate = <150>;
211 usdhc0-grp4 {
225 pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
226 usdhc0-100mhz-grp0 {
229 output-enable;
230 bias-pull-down;
231 slew-rate = <150>;
234 usdhc0-100mhz-grp1 {
244 output-enable;
245 input-enable;
246 bias-pull-up;
247 slew-rate = <150>;
250 usdhc0-100mhz-grp2 {
252 output-enable;
253 slew-rate = <150>;
256 usdhc0-100mhz-grp3 {
258 input-enable;
259 slew-rate = <150>;
262 usdhc0-100mhz-grp4 {
276 pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
277 usdhc0-200mhz-grp0 {
280 output-enable;
281 bias-pull-down;
282 slew-rate = <208>;
285 usdhc0-200mhz-grp1 {
295 output-enable;
296 input-enable;
297 bias-pull-up;
298 slew-rate = <208>;
301 usdhc0-200mhz-grp2 {
303 output-enable;
304 slew-rate = <208>;
307 usdhc0-200mhz-grp3 {
309 input-enable;
310 slew-rate = <208>;
313 usdhc0-200mhz-grp4 {
328 edma0: dma-controller@40144000 {
329 compatible = "nxp,s32g2-edma";
333 #dma-cells = <2>;
334 dma-channels = <32>;
338 interrupt-names = "tx-0-15",
339 "tx-16-31",
340 "err";
342 clock-names = "dmamux0", "dmamux1";
346 compatible = "nxp,s32g2-flexcan";
352 interrupt-names = "mb-0", "state", "berr", "mb-1";
354 clock-names = "ipg", "per";
359 compatible = "nxp,s32g2-flexcan";
365 interrupt-names = "mb-0", "state", "berr", "mb-1";
367 clock-names = "ipg", "per";
372 compatible = "nxp,s32g2-linflexuart",
373 "fsl,s32v234-linflexuart";
380 compatible = "nxp,s32g2-linflexuart",
381 "fsl,s32v234-linflexuart";
388 #index-cells = <1>;
389 compatible = "nxp,s32g2-usbmisc";
394 compatible = "nxp,s32g2-usb";
396 interrupt-parent = <&gic>;
401 ahb-burst-config = <0x3>;
402 tx-burst-size-dword = <0x10>;
403 rx-burst-size-dword = <0x10>;
406 maximum-speed = "high-speed";
411 compatible = "nxp,s32g2-dspi";
415 clock-names = "dspi";
416 spi-num-chipselects = <8>;
417 bus-num = <0>;
419 dma-names = "tx", "rx";
424 compatible = "nxp,s32g2-dspi";
428 clock-names = "dspi";
429 spi-num-chipselects = <5>;
430 bus-num = <1>;
432 dma-names = "tx", "rx";
437 compatible = "nxp,s32g2-dspi";
441 clock-names = "dspi";
442 spi-num-chipselects = <5>;
443 bus-num = <2>;
445 dma-names = "tx", "rx";
450 compatible = "nxp,s32g2-i2c";
452 #address-cells = <1>;
453 #size-cells = <0>;
456 clock-names = "ipg";
461 compatible = "nxp,s32g2-i2c";
463 #address-cells = <1>;
464 #size-cells = <0>;
467 clock-names = "ipg";
472 compatible = "nxp,s32g2-i2c";
474 #address-cells = <1>;
475 #size-cells = <0>;
478 clock-names = "ipg";
482 edma1: dma-controller@40244000 {
483 compatible = "nxp,s32g2-edma";
487 #dma-cells = <2>;
488 dma-channels = <32>;
492 interrupt-names = "tx-0-15",
493 "tx-16-31",
494 "err";
496 clock-names = "dmamux0", "dmamux1";
500 compatible = "nxp,s32g2-flexcan";
506 interrupt-names = "mb-0", "state", "berr", "mb-1";
508 clock-names = "ipg", "per";
513 compatible = "nxp,s32g2-flexcan";
519 interrupt-names = "mb-0", "state", "berr", "mb-1";
521 clock-names = "ipg", "per";
526 compatible = "nxp,s32g2-linflexuart",
527 "fsl,s32v234-linflexuart";
534 compatible = "nxp,s32g2-dspi";
538 clock-names = "dspi";
539 spi-num-chipselects = <5>;
540 bus-num = <3>;
542 dma-names = "tx", "rx";
547 compatible = "nxp,s32g2-dspi";
551 clock-names = "dspi";
552 spi-num-chipselects = <5>;
553 bus-num = <4>;
555 dma-names = "tx", "rx";
560 compatible = "nxp,s32g2-dspi";
564 clock-names = "dspi";
565 spi-num-chipselects = <5>;
566 bus-num = <5>;
568 dma-names = "tx", "rx";
573 compatible = "nxp,s32g2-i2c";
575 #address-cells = <1>;
576 #size-cells = <0>;
579 clock-names = "ipg";
584 compatible = "nxp,s32g2-i2c";
586 #address-cells = <1>;
587 #size-cells = <0>;
590 clock-names = "ipg";
595 compatible = "nxp,s32g2-usdhc";
599 clock-names = "ipg", "ahb", "per";
600 bus-width = <8>;
604 gic: interrupt-controller@50800000 {
605 compatible = "arm,gic-v3";
612 interrupt-controller;
613 #interrupt-cells = <3>;