10d0c5510SYoshihiro Shimoda // SPDX-License-Identifier: GPL-2.0-only
20d0c5510SYoshihiro Shimoda /*
30d0c5510SYoshihiro Shimoda * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
40d0c5510SYoshihiro Shimoda * Copyright (C) 2022-2023 Renesas Electronics Corporation
5faf5a975SYoshihiro Shimoda *
6faf5a975SYoshihiro Shimoda * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be
7faf5a975SYoshihiro Shimoda * provided, to initialize the PHY. Otherwise, the PCIe controller will not
8faf5a975SYoshihiro Shimoda * work.
90d0c5510SYoshihiro Shimoda */
100d0c5510SYoshihiro Shimoda
110d0c5510SYoshihiro Shimoda #include <linux/delay.h>
12faf5a975SYoshihiro Shimoda #include <linux/firmware.h>
130d0c5510SYoshihiro Shimoda #include <linux/interrupt.h>
140d0c5510SYoshihiro Shimoda #include <linux/io.h>
15faf5a975SYoshihiro Shimoda #include <linux/iopoll.h>
160d0c5510SYoshihiro Shimoda #include <linux/module.h>
17ec215237SRob Herring #include <linux/of.h>
180d0c5510SYoshihiro Shimoda #include <linux/pci.h>
190d0c5510SYoshihiro Shimoda #include <linux/platform_device.h>
200d0c5510SYoshihiro Shimoda #include <linux/pm_runtime.h>
210d0c5510SYoshihiro Shimoda #include <linux/reset.h>
220d0c5510SYoshihiro Shimoda
230d0c5510SYoshihiro Shimoda #include "../../pci.h"
240d0c5510SYoshihiro Shimoda #include "pcie-designware.h"
250d0c5510SYoshihiro Shimoda
260d0c5510SYoshihiro Shimoda /* Renesas-specific */
270d0c5510SYoshihiro Shimoda /* PCIe Mode Setting Register 0 */
280d0c5510SYoshihiro Shimoda #define PCIEMSR0 0x0000
29faf5a975SYoshihiro Shimoda #define APP_SRIS_MODE BIT(6)
30e311b383SYoshihiro Shimoda #define DEVICE_TYPE_EP 0
310d0c5510SYoshihiro Shimoda #define DEVICE_TYPE_RC BIT(4)
32faf5a975SYoshihiro Shimoda #define BIFUR_MOD_SET_ON BIT(0)
330d0c5510SYoshihiro Shimoda
340d0c5510SYoshihiro Shimoda /* PCIe Interrupt Status 0 */
350d0c5510SYoshihiro Shimoda #define PCIEINTSTS0 0x0084
360d0c5510SYoshihiro Shimoda
370d0c5510SYoshihiro Shimoda /* PCIe Interrupt Status 0 Enable */
380d0c5510SYoshihiro Shimoda #define PCIEINTSTS0EN 0x0310
390d0c5510SYoshihiro Shimoda #define MSI_CTRL_INT BIT(26)
400d0c5510SYoshihiro Shimoda #define SMLH_LINK_UP BIT(7)
410d0c5510SYoshihiro Shimoda #define RDLH_LINK_UP BIT(6)
420d0c5510SYoshihiro Shimoda
430d0c5510SYoshihiro Shimoda /* PCIe DMA Interrupt Status Enable */
440d0c5510SYoshihiro Shimoda #define PCIEDMAINTSTSEN 0x0314
450d0c5510SYoshihiro Shimoda #define PCIEDMAINTSTSEN_INIT GENMASK(15, 0)
460d0c5510SYoshihiro Shimoda
47faf5a975SYoshihiro Shimoda /* Port Logic Registers 89 */
48faf5a975SYoshihiro Shimoda #define PRTLGC89 0x0b70
49faf5a975SYoshihiro Shimoda
50faf5a975SYoshihiro Shimoda /* Port Logic Registers 90 */
51faf5a975SYoshihiro Shimoda #define PRTLGC90 0x0b74
52faf5a975SYoshihiro Shimoda
530d0c5510SYoshihiro Shimoda /* PCIe Reset Control Register 1 */
540d0c5510SYoshihiro Shimoda #define PCIERSTCTRL1 0x0014
550d0c5510SYoshihiro Shimoda #define APP_HOLD_PHY_RST BIT(16)
560d0c5510SYoshihiro Shimoda #define APP_LTSSM_ENABLE BIT(0)
570d0c5510SYoshihiro Shimoda
58faf5a975SYoshihiro Shimoda /* PCIe Power Management Control */
59faf5a975SYoshihiro Shimoda #define PCIEPWRMNGCTRL 0x0070
60faf5a975SYoshihiro Shimoda #define APP_CLK_REQ_N BIT(11)
61faf5a975SYoshihiro Shimoda #define APP_CLK_PM_EN BIT(10)
62faf5a975SYoshihiro Shimoda
630d0c5510SYoshihiro Shimoda #define RCAR_NUM_SPEED_CHANGE_RETRIES 10
640d0c5510SYoshihiro Shimoda #define RCAR_MAX_LINK_SPEED 4
650d0c5510SYoshihiro Shimoda
66e311b383SYoshihiro Shimoda #define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET 0x1000
67e311b383SYoshihiro Shimoda #define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET 0x800
68e311b383SYoshihiro Shimoda
69faf5a975SYoshihiro Shimoda #define RCAR_GEN4_PCIE_FIRMWARE_NAME "rcar_gen4_pcie.bin"
70faf5a975SYoshihiro Shimoda #define RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR 0xc000
71faf5a975SYoshihiro Shimoda MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME);
72faf5a975SYoshihiro Shimoda
732c49151bSYoshihiro Shimoda struct rcar_gen4_pcie;
74ac1d89f8SYoshihiro Shimoda struct rcar_gen4_pcie_drvdata {
75faf5a975SYoshihiro Shimoda void (*additional_common_init)(struct rcar_gen4_pcie *rcar);
762c49151bSYoshihiro Shimoda int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable);
77ac1d89f8SYoshihiro Shimoda enum dw_pcie_device_mode mode;
78ac1d89f8SYoshihiro Shimoda };
79ac1d89f8SYoshihiro Shimoda
800d0c5510SYoshihiro Shimoda struct rcar_gen4_pcie {
810d0c5510SYoshihiro Shimoda struct dw_pcie dw;
820d0c5510SYoshihiro Shimoda void __iomem *base;
83faf5a975SYoshihiro Shimoda void __iomem *phy_base;
840d0c5510SYoshihiro Shimoda struct platform_device *pdev;
85ac1d89f8SYoshihiro Shimoda const struct rcar_gen4_pcie_drvdata *drvdata;
860d0c5510SYoshihiro Shimoda };
870d0c5510SYoshihiro Shimoda #define to_rcar_gen4_pcie(_dw) container_of(_dw, struct rcar_gen4_pcie, dw)
880d0c5510SYoshihiro Shimoda
89e311b383SYoshihiro Shimoda /* Common */
rcar_gen4_pcie_link_up(struct dw_pcie * dw)900d0c5510SYoshihiro Shimoda static int rcar_gen4_pcie_link_up(struct dw_pcie *dw)
910d0c5510SYoshihiro Shimoda {
920d0c5510SYoshihiro Shimoda struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
930d0c5510SYoshihiro Shimoda u32 val, mask;
940d0c5510SYoshihiro Shimoda
950d0c5510SYoshihiro Shimoda val = readl(rcar->base + PCIEINTSTS0);
960d0c5510SYoshihiro Shimoda mask = RDLH_LINK_UP | SMLH_LINK_UP;
970d0c5510SYoshihiro Shimoda
980d0c5510SYoshihiro Shimoda return (val & mask) == mask;
990d0c5510SYoshihiro Shimoda }
1000d0c5510SYoshihiro Shimoda
1010d0c5510SYoshihiro Shimoda /*
1020d0c5510SYoshihiro Shimoda * Manually initiate the speed change. Return 0 if change succeeded; otherwise
1030d0c5510SYoshihiro Shimoda * -ETIMEDOUT.
1040d0c5510SYoshihiro Shimoda */
rcar_gen4_pcie_speed_change(struct dw_pcie * dw)1050d0c5510SYoshihiro Shimoda static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
1060d0c5510SYoshihiro Shimoda {
1070d0c5510SYoshihiro Shimoda u32 val;
1080d0c5510SYoshihiro Shimoda int i;
1090d0c5510SYoshihiro Shimoda
1100d0c5510SYoshihiro Shimoda val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
1110d0c5510SYoshihiro Shimoda val &= ~PORT_LOGIC_SPEED_CHANGE;
1120d0c5510SYoshihiro Shimoda dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
1130d0c5510SYoshihiro Shimoda
1140d0c5510SYoshihiro Shimoda val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
1150d0c5510SYoshihiro Shimoda val |= PORT_LOGIC_SPEED_CHANGE;
1160d0c5510SYoshihiro Shimoda dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
1170d0c5510SYoshihiro Shimoda
1180d0c5510SYoshihiro Shimoda for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
1190d0c5510SYoshihiro Shimoda val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
1200d0c5510SYoshihiro Shimoda if (!(val & PORT_LOGIC_SPEED_CHANGE))
1210d0c5510SYoshihiro Shimoda return 0;
1220d0c5510SYoshihiro Shimoda usleep_range(10000, 11000);
1230d0c5510SYoshihiro Shimoda }
1240d0c5510SYoshihiro Shimoda
1250d0c5510SYoshihiro Shimoda return -ETIMEDOUT;
1260d0c5510SYoshihiro Shimoda }
1270d0c5510SYoshihiro Shimoda
1280d0c5510SYoshihiro Shimoda /*
1290d0c5510SYoshihiro Shimoda * Enable LTSSM of this controller and manually initiate the speed change.
1300d0c5510SYoshihiro Shimoda * Always return 0.
1310d0c5510SYoshihiro Shimoda */
rcar_gen4_pcie_start_link(struct dw_pcie * dw)1320d0c5510SYoshihiro Shimoda static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
1330d0c5510SYoshihiro Shimoda {
1340d0c5510SYoshihiro Shimoda struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
1352c49151bSYoshihiro Shimoda int i, changes, ret;
1360d0c5510SYoshihiro Shimoda
1372c49151bSYoshihiro Shimoda if (rcar->drvdata->ltssm_control) {
1382c49151bSYoshihiro Shimoda ret = rcar->drvdata->ltssm_control(rcar, true);
1392c49151bSYoshihiro Shimoda if (ret)
1402c49151bSYoshihiro Shimoda return ret;
1412c49151bSYoshihiro Shimoda }
1420d0c5510SYoshihiro Shimoda
1430d0c5510SYoshihiro Shimoda /*
1440d0c5510SYoshihiro Shimoda * Require direct speed change with retrying here if the link_gen is
1450d0c5510SYoshihiro Shimoda * PCIe Gen2 or higher.
1460d0c5510SYoshihiro Shimoda */
1470d0c5510SYoshihiro Shimoda changes = min_not_zero(dw->link_gen, RCAR_MAX_LINK_SPEED) - 1;
1480d0c5510SYoshihiro Shimoda
1490d0c5510SYoshihiro Shimoda /*
1500d0c5510SYoshihiro Shimoda * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
1510d0c5510SYoshihiro Shimoda * So, this needs remaining times for up to PCIe Gen4 if RC mode.
1520d0c5510SYoshihiro Shimoda */
153ac1d89f8SYoshihiro Shimoda if (changes && rcar->drvdata->mode == DW_PCIE_RC_TYPE)
1540d0c5510SYoshihiro Shimoda changes--;
1550d0c5510SYoshihiro Shimoda
1560d0c5510SYoshihiro Shimoda for (i = 0; i < changes; i++) {
1570d0c5510SYoshihiro Shimoda /* It may not be connected in EP mode yet. So, break the loop */
1580d0c5510SYoshihiro Shimoda if (rcar_gen4_pcie_speed_change(dw))
1590d0c5510SYoshihiro Shimoda break;
1600d0c5510SYoshihiro Shimoda }
1610d0c5510SYoshihiro Shimoda
1620d0c5510SYoshihiro Shimoda return 0;
1630d0c5510SYoshihiro Shimoda }
1640d0c5510SYoshihiro Shimoda
rcar_gen4_pcie_stop_link(struct dw_pcie * dw)1650d0c5510SYoshihiro Shimoda static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
1660d0c5510SYoshihiro Shimoda {
1670d0c5510SYoshihiro Shimoda struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
1680d0c5510SYoshihiro Shimoda
1692c49151bSYoshihiro Shimoda if (rcar->drvdata->ltssm_control)
1702c49151bSYoshihiro Shimoda rcar->drvdata->ltssm_control(rcar, false);
1710d0c5510SYoshihiro Shimoda }
1720d0c5510SYoshihiro Shimoda
rcar_gen4_pcie_common_init(struct rcar_gen4_pcie * rcar)1730d0c5510SYoshihiro Shimoda static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
1740d0c5510SYoshihiro Shimoda {
1750d0c5510SYoshihiro Shimoda struct dw_pcie *dw = &rcar->dw;
1760d0c5510SYoshihiro Shimoda u32 val;
1770d0c5510SYoshihiro Shimoda int ret;
1780d0c5510SYoshihiro Shimoda
1790d0c5510SYoshihiro Shimoda ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
1800d0c5510SYoshihiro Shimoda if (ret) {
1810d0c5510SYoshihiro Shimoda dev_err(dw->dev, "Enabling core clocks failed\n");
1820d0c5510SYoshihiro Shimoda return ret;
1830d0c5510SYoshihiro Shimoda }
1840d0c5510SYoshihiro Shimoda
1850d0c5510SYoshihiro Shimoda if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc))
1860d0c5510SYoshihiro Shimoda reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
1870d0c5510SYoshihiro Shimoda
1880d0c5510SYoshihiro Shimoda val = readl(rcar->base + PCIEMSR0);
189ac1d89f8SYoshihiro Shimoda if (rcar->drvdata->mode == DW_PCIE_RC_TYPE) {
1900d0c5510SYoshihiro Shimoda val |= DEVICE_TYPE_RC;
191ac1d89f8SYoshihiro Shimoda } else if (rcar->drvdata->mode == DW_PCIE_EP_TYPE) {
192e311b383SYoshihiro Shimoda val |= DEVICE_TYPE_EP;
1930d0c5510SYoshihiro Shimoda } else {
1940d0c5510SYoshihiro Shimoda ret = -EINVAL;
1950d0c5510SYoshihiro Shimoda goto err_unprepare;
1960d0c5510SYoshihiro Shimoda }
1970d0c5510SYoshihiro Shimoda
1980d0c5510SYoshihiro Shimoda if (dw->num_lanes < 4)
1990d0c5510SYoshihiro Shimoda val |= BIFUR_MOD_SET_ON;
2000d0c5510SYoshihiro Shimoda
2010d0c5510SYoshihiro Shimoda writel(val, rcar->base + PCIEMSR0);
2020d0c5510SYoshihiro Shimoda
2030d0c5510SYoshihiro Shimoda ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
2040d0c5510SYoshihiro Shimoda if (ret)
2050d0c5510SYoshihiro Shimoda goto err_unprepare;
2060d0c5510SYoshihiro Shimoda
207faf5a975SYoshihiro Shimoda if (rcar->drvdata->additional_common_init)
208faf5a975SYoshihiro Shimoda rcar->drvdata->additional_common_init(rcar);
209faf5a975SYoshihiro Shimoda
2100d0c5510SYoshihiro Shimoda return 0;
2110d0c5510SYoshihiro Shimoda
2120d0c5510SYoshihiro Shimoda err_unprepare:
2130d0c5510SYoshihiro Shimoda clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
2140d0c5510SYoshihiro Shimoda
2150d0c5510SYoshihiro Shimoda return ret;
2160d0c5510SYoshihiro Shimoda }
2170d0c5510SYoshihiro Shimoda
rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie * rcar)2180d0c5510SYoshihiro Shimoda static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
2190d0c5510SYoshihiro Shimoda {
2200d0c5510SYoshihiro Shimoda struct dw_pcie *dw = &rcar->dw;
2210d0c5510SYoshihiro Shimoda
2220d0c5510SYoshihiro Shimoda reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
2230d0c5510SYoshihiro Shimoda clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
2240d0c5510SYoshihiro Shimoda }
2250d0c5510SYoshihiro Shimoda
rcar_gen4_pcie_prepare(struct rcar_gen4_pcie * rcar)2260d0c5510SYoshihiro Shimoda static int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
2270d0c5510SYoshihiro Shimoda {
2280d0c5510SYoshihiro Shimoda struct device *dev = rcar->dw.dev;
2290d0c5510SYoshihiro Shimoda int err;
2300d0c5510SYoshihiro Shimoda
2310d0c5510SYoshihiro Shimoda pm_runtime_enable(dev);
2320d0c5510SYoshihiro Shimoda err = pm_runtime_resume_and_get(dev);
2330d0c5510SYoshihiro Shimoda if (err < 0) {
2340d0c5510SYoshihiro Shimoda dev_err(dev, "Runtime resume failed\n");
2350d0c5510SYoshihiro Shimoda pm_runtime_disable(dev);
2360d0c5510SYoshihiro Shimoda }
2370d0c5510SYoshihiro Shimoda
2380d0c5510SYoshihiro Shimoda return err;
2390d0c5510SYoshihiro Shimoda }
2400d0c5510SYoshihiro Shimoda
rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie * rcar)2410d0c5510SYoshihiro Shimoda static void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
2420d0c5510SYoshihiro Shimoda {
2430d0c5510SYoshihiro Shimoda struct device *dev = rcar->dw.dev;
2440d0c5510SYoshihiro Shimoda
2450d0c5510SYoshihiro Shimoda pm_runtime_put(dev);
2460d0c5510SYoshihiro Shimoda pm_runtime_disable(dev);
2470d0c5510SYoshihiro Shimoda }
2480d0c5510SYoshihiro Shimoda
rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie * rcar)2490d0c5510SYoshihiro Shimoda static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
2500d0c5510SYoshihiro Shimoda {
251faf5a975SYoshihiro Shimoda rcar->phy_base = devm_platform_ioremap_resource_byname(rcar->pdev, "phy");
252faf5a975SYoshihiro Shimoda if (IS_ERR(rcar->phy_base))
253faf5a975SYoshihiro Shimoda return PTR_ERR(rcar->phy_base);
254faf5a975SYoshihiro Shimoda
2550d0c5510SYoshihiro Shimoda /* Renesas-specific registers */
2560d0c5510SYoshihiro Shimoda rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
2570d0c5510SYoshihiro Shimoda
2580d0c5510SYoshihiro Shimoda return PTR_ERR_OR_ZERO(rcar->base);
2590d0c5510SYoshihiro Shimoda }
2600d0c5510SYoshihiro Shimoda
2610d0c5510SYoshihiro Shimoda static const struct dw_pcie_ops dw_pcie_ops = {
2620d0c5510SYoshihiro Shimoda .start_link = rcar_gen4_pcie_start_link,
2630d0c5510SYoshihiro Shimoda .stop_link = rcar_gen4_pcie_stop_link,
2640d0c5510SYoshihiro Shimoda .link_up = rcar_gen4_pcie_link_up,
2650d0c5510SYoshihiro Shimoda };
2660d0c5510SYoshihiro Shimoda
rcar_gen4_pcie_alloc(struct platform_device * pdev)2670d0c5510SYoshihiro Shimoda static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev)
2680d0c5510SYoshihiro Shimoda {
2690d0c5510SYoshihiro Shimoda struct device *dev = &pdev->dev;
2700d0c5510SYoshihiro Shimoda struct rcar_gen4_pcie *rcar;
2710d0c5510SYoshihiro Shimoda
2720d0c5510SYoshihiro Shimoda rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
2730d0c5510SYoshihiro Shimoda if (!rcar)
2740d0c5510SYoshihiro Shimoda return ERR_PTR(-ENOMEM);
2750d0c5510SYoshihiro Shimoda
2760d0c5510SYoshihiro Shimoda rcar->dw.ops = &dw_pcie_ops;
2770d0c5510SYoshihiro Shimoda rcar->dw.dev = dev;
2780d0c5510SYoshihiro Shimoda rcar->pdev = pdev;
2790551abf2SManivannan Sadhasivam rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL;
2800d0c5510SYoshihiro Shimoda dw_pcie_cap_set(&rcar->dw, REQ_RES);
2810d0c5510SYoshihiro Shimoda platform_set_drvdata(pdev, rcar);
2820d0c5510SYoshihiro Shimoda
2830d0c5510SYoshihiro Shimoda return rcar;
2840d0c5510SYoshihiro Shimoda }
2850d0c5510SYoshihiro Shimoda
2860d0c5510SYoshihiro Shimoda /* Host mode */
rcar_gen4_pcie_host_init(struct dw_pcie_rp * pp)2870d0c5510SYoshihiro Shimoda static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
2880d0c5510SYoshihiro Shimoda {
2890d0c5510SYoshihiro Shimoda struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
2900d0c5510SYoshihiro Shimoda struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
2910d0c5510SYoshihiro Shimoda int ret;
2920d0c5510SYoshihiro Shimoda u32 val;
2930d0c5510SYoshihiro Shimoda
2940d0c5510SYoshihiro Shimoda gpiod_set_value_cansleep(dw->pe_rst, 1);
2950d0c5510SYoshihiro Shimoda
2960d0c5510SYoshihiro Shimoda ret = rcar_gen4_pcie_common_init(rcar);
2970d0c5510SYoshihiro Shimoda if (ret)
2980d0c5510SYoshihiro Shimoda return ret;
2990d0c5510SYoshihiro Shimoda
3000d0c5510SYoshihiro Shimoda /*
3010d0c5510SYoshihiro Shimoda * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
3020d0c5510SYoshihiro Shimoda * Rev.5.20a and 3.5.6.1 "RC mode" in DWC PCIe RC databook v5.20a, we
3030d0c5510SYoshihiro Shimoda * should disable two BARs to avoid unnecessary memory assignment
3040d0c5510SYoshihiro Shimoda * during device enumeration.
3050d0c5510SYoshihiro Shimoda */
3060d0c5510SYoshihiro Shimoda dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
3070d0c5510SYoshihiro Shimoda dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
3080d0c5510SYoshihiro Shimoda
3090d0c5510SYoshihiro Shimoda /* Enable MSI interrupt signal */
3100d0c5510SYoshihiro Shimoda val = readl(rcar->base + PCIEINTSTS0EN);
3110d0c5510SYoshihiro Shimoda val |= MSI_CTRL_INT;
3120d0c5510SYoshihiro Shimoda writel(val, rcar->base + PCIEINTSTS0EN);
3130d0c5510SYoshihiro Shimoda
3140d0c5510SYoshihiro Shimoda msleep(PCIE_T_PVPERL_MS); /* pe_rst requires 100msec delay */
3150d0c5510SYoshihiro Shimoda
3160d0c5510SYoshihiro Shimoda gpiod_set_value_cansleep(dw->pe_rst, 0);
3170d0c5510SYoshihiro Shimoda
3180d0c5510SYoshihiro Shimoda return 0;
3190d0c5510SYoshihiro Shimoda }
3200d0c5510SYoshihiro Shimoda
rcar_gen4_pcie_host_deinit(struct dw_pcie_rp * pp)3210d0c5510SYoshihiro Shimoda static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)
3220d0c5510SYoshihiro Shimoda {
3230d0c5510SYoshihiro Shimoda struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
3240d0c5510SYoshihiro Shimoda struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
3250d0c5510SYoshihiro Shimoda
3260d0c5510SYoshihiro Shimoda gpiod_set_value_cansleep(dw->pe_rst, 1);
3270d0c5510SYoshihiro Shimoda rcar_gen4_pcie_common_deinit(rcar);
3280d0c5510SYoshihiro Shimoda }
3290d0c5510SYoshihiro Shimoda
3300d0c5510SYoshihiro Shimoda static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
331aea370b2SYoshihiro Shimoda .init = rcar_gen4_pcie_host_init,
332aea370b2SYoshihiro Shimoda .deinit = rcar_gen4_pcie_host_deinit,
3330d0c5510SYoshihiro Shimoda };
3340d0c5510SYoshihiro Shimoda
rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie * rcar)3350d0c5510SYoshihiro Shimoda static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
3360d0c5510SYoshihiro Shimoda {
3370d0c5510SYoshihiro Shimoda struct dw_pcie_rp *pp = &rcar->dw.pp;
3380d0c5510SYoshihiro Shimoda
339e311b383SYoshihiro Shimoda if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_HOST))
340e311b383SYoshihiro Shimoda return -ENODEV;
341e311b383SYoshihiro Shimoda
3420d0c5510SYoshihiro Shimoda pp->num_vectors = MAX_MSI_IRQS;
3430d0c5510SYoshihiro Shimoda pp->ops = &rcar_gen4_pcie_host_ops;
3440d0c5510SYoshihiro Shimoda
3450d0c5510SYoshihiro Shimoda return dw_pcie_host_init(pp);
3460d0c5510SYoshihiro Shimoda }
3470d0c5510SYoshihiro Shimoda
rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie * rcar)3480d0c5510SYoshihiro Shimoda static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
3490d0c5510SYoshihiro Shimoda {
3500d0c5510SYoshihiro Shimoda dw_pcie_host_deinit(&rcar->dw.pp);
3510d0c5510SYoshihiro Shimoda }
3520d0c5510SYoshihiro Shimoda
353e311b383SYoshihiro Shimoda /* Endpoint mode */
rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep * ep)354e311b383SYoshihiro Shimoda static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
355e311b383SYoshihiro Shimoda {
356e311b383SYoshihiro Shimoda struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
357e311b383SYoshihiro Shimoda struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
358e311b383SYoshihiro Shimoda int ret;
359e311b383SYoshihiro Shimoda
360e311b383SYoshihiro Shimoda ret = rcar_gen4_pcie_common_init(rcar);
361e311b383SYoshihiro Shimoda if (ret)
362e311b383SYoshihiro Shimoda return;
363e311b383SYoshihiro Shimoda
364e311b383SYoshihiro Shimoda writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
365e311b383SYoshihiro Shimoda }
366e311b383SYoshihiro Shimoda
rcar_gen4_pcie_ep_init(struct dw_pcie_ep * ep)367e311b383SYoshihiro Shimoda static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
368e311b383SYoshihiro Shimoda {
369e311b383SYoshihiro Shimoda struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
370e311b383SYoshihiro Shimoda enum pci_barno bar;
371e311b383SYoshihiro Shimoda
372e311b383SYoshihiro Shimoda for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
373e311b383SYoshihiro Shimoda dw_pcie_ep_reset_bar(pci, bar);
374e311b383SYoshihiro Shimoda }
375e311b383SYoshihiro Shimoda
rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie * rcar)376b7dec6b8SManivannan Sadhasivam static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar)
377e311b383SYoshihiro Shimoda {
378e311b383SYoshihiro Shimoda writel(0, rcar->base + PCIEDMAINTSTSEN);
379e311b383SYoshihiro Shimoda rcar_gen4_pcie_common_deinit(rcar);
380e311b383SYoshihiro Shimoda }
381e311b383SYoshihiro Shimoda
rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep * ep,u8 func_no,unsigned int type,u16 interrupt_num)382e311b383SYoshihiro Shimoda static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
38374955cb8SDamien Le Moal unsigned int type, u16 interrupt_num)
384e311b383SYoshihiro Shimoda {
385e311b383SYoshihiro Shimoda struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
386e311b383SYoshihiro Shimoda
387e311b383SYoshihiro Shimoda switch (type) {
38874955cb8SDamien Le Moal case PCI_IRQ_INTX:
389e9af4800SDamien Le Moal return dw_pcie_ep_raise_intx_irq(ep, func_no);
39074955cb8SDamien Le Moal case PCI_IRQ_MSI:
391e311b383SYoshihiro Shimoda return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
392e311b383SYoshihiro Shimoda default:
393e311b383SYoshihiro Shimoda dev_err(dw->dev, "Unknown IRQ type\n");
394e311b383SYoshihiro Shimoda return -EINVAL;
395e311b383SYoshihiro Shimoda }
396e311b383SYoshihiro Shimoda
397e311b383SYoshihiro Shimoda return 0;
398e311b383SYoshihiro Shimoda }
399e311b383SYoshihiro Shimoda
400e311b383SYoshihiro Shimoda static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
401e311b383SYoshihiro Shimoda .linkup_notifier = false,
402e311b383SYoshihiro Shimoda .msi_capable = true,
403e311b383SYoshihiro Shimoda .msix_capable = false,
404e01c9797SNiklas Cassel .bar[BAR_1] = { .type = BAR_RESERVED, },
405e01c9797SNiklas Cassel .bar[BAR_3] = { .type = BAR_RESERVED, },
406e01c9797SNiklas Cassel .bar[BAR_5] = { .type = BAR_RESERVED, },
407e311b383SYoshihiro Shimoda .align = SZ_1M,
408e311b383SYoshihiro Shimoda };
409e311b383SYoshihiro Shimoda
410e311b383SYoshihiro Shimoda static const struct pci_epc_features*
rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep * ep)411e311b383SYoshihiro Shimoda rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep)
412e311b383SYoshihiro Shimoda {
413e311b383SYoshihiro Shimoda return &rcar_gen4_pcie_epc_features;
414e311b383SYoshihiro Shimoda }
415e311b383SYoshihiro Shimoda
rcar_gen4_pcie_ep_get_dbi_offset(struct dw_pcie_ep * ep,u8 func_no)416641f79beSYoshihiro Shimoda static unsigned int rcar_gen4_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep,
417e311b383SYoshihiro Shimoda u8 func_no)
418e311b383SYoshihiro Shimoda {
419e311b383SYoshihiro Shimoda return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET;
420e311b383SYoshihiro Shimoda }
421e311b383SYoshihiro Shimoda
rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep * ep,u8 func_no)422e311b383SYoshihiro Shimoda static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
423e311b383SYoshihiro Shimoda u8 func_no)
424e311b383SYoshihiro Shimoda {
425e311b383SYoshihiro Shimoda return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET;
426e311b383SYoshihiro Shimoda }
427e311b383SYoshihiro Shimoda
428e311b383SYoshihiro Shimoda static const struct dw_pcie_ep_ops pcie_ep_ops = {
429e311b383SYoshihiro Shimoda .pre_init = rcar_gen4_pcie_ep_pre_init,
430756dcb5aSYoshihiro Shimoda .init = rcar_gen4_pcie_ep_init,
431e311b383SYoshihiro Shimoda .raise_irq = rcar_gen4_pcie_ep_raise_irq,
432e311b383SYoshihiro Shimoda .get_features = rcar_gen4_pcie_ep_get_features,
433641f79beSYoshihiro Shimoda .get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,
434e311b383SYoshihiro Shimoda .get_dbi2_offset = rcar_gen4_pcie_ep_get_dbi2_offset,
435e311b383SYoshihiro Shimoda };
436e311b383SYoshihiro Shimoda
rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie * rcar)437e311b383SYoshihiro Shimoda static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
438e311b383SYoshihiro Shimoda {
439e311b383SYoshihiro Shimoda struct dw_pcie_ep *ep = &rcar->dw.ep;
440df69e17cSManivannan Sadhasivam struct device *dev = rcar->dw.dev;
441b7dec6b8SManivannan Sadhasivam int ret;
442e311b383SYoshihiro Shimoda
443e311b383SYoshihiro Shimoda if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_EP))
444e311b383SYoshihiro Shimoda return -ENODEV;
445e311b383SYoshihiro Shimoda
446e311b383SYoshihiro Shimoda ep->ops = &pcie_ep_ops;
447e311b383SYoshihiro Shimoda
448b7dec6b8SManivannan Sadhasivam ret = dw_pcie_ep_init(ep);
449df69e17cSManivannan Sadhasivam if (ret) {
450b7dec6b8SManivannan Sadhasivam rcar_gen4_pcie_ep_deinit(rcar);
451df69e17cSManivannan Sadhasivam return ret;
452df69e17cSManivannan Sadhasivam }
453df69e17cSManivannan Sadhasivam
454df69e17cSManivannan Sadhasivam ret = dw_pcie_ep_init_registers(ep);
455df69e17cSManivannan Sadhasivam if (ret) {
456df69e17cSManivannan Sadhasivam dev_err(dev, "Failed to initialize DWC endpoint registers\n");
457df69e17cSManivannan Sadhasivam dw_pcie_ep_deinit(ep);
458df69e17cSManivannan Sadhasivam rcar_gen4_pcie_ep_deinit(rcar);
459df69e17cSManivannan Sadhasivam }
460b7dec6b8SManivannan Sadhasivam
461*245b9ebfSManivannan Sadhasivam pci_epc_init_notify(ep->epc);
462a01e7214SManivannan Sadhasivam
463b7dec6b8SManivannan Sadhasivam return ret;
464e311b383SYoshihiro Shimoda }
465e311b383SYoshihiro Shimoda
rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie * rcar)466e311b383SYoshihiro Shimoda static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
467e311b383SYoshihiro Shimoda {
468c8682a33SManivannan Sadhasivam dw_pcie_ep_deinit(&rcar->dw.ep);
469b7dec6b8SManivannan Sadhasivam rcar_gen4_pcie_ep_deinit(rcar);
470e311b383SYoshihiro Shimoda }
471e311b383SYoshihiro Shimoda
472e311b383SYoshihiro Shimoda /* Common */
rcar_gen4_add_dw_pcie(struct rcar_gen4_pcie * rcar)473e311b383SYoshihiro Shimoda static int rcar_gen4_add_dw_pcie(struct rcar_gen4_pcie *rcar)
474e311b383SYoshihiro Shimoda {
475ac1d89f8SYoshihiro Shimoda rcar->drvdata = of_device_get_match_data(&rcar->pdev->dev);
476ac1d89f8SYoshihiro Shimoda if (!rcar->drvdata)
477ac1d89f8SYoshihiro Shimoda return -EINVAL;
478e311b383SYoshihiro Shimoda
479ac1d89f8SYoshihiro Shimoda switch (rcar->drvdata->mode) {
480e311b383SYoshihiro Shimoda case DW_PCIE_RC_TYPE:
481e311b383SYoshihiro Shimoda return rcar_gen4_add_dw_pcie_rp(rcar);
482e311b383SYoshihiro Shimoda case DW_PCIE_EP_TYPE:
483e311b383SYoshihiro Shimoda return rcar_gen4_add_dw_pcie_ep(rcar);
484e311b383SYoshihiro Shimoda default:
485e311b383SYoshihiro Shimoda return -EINVAL;
486e311b383SYoshihiro Shimoda }
487e311b383SYoshihiro Shimoda }
488e311b383SYoshihiro Shimoda
rcar_gen4_pcie_probe(struct platform_device * pdev)4890d0c5510SYoshihiro Shimoda static int rcar_gen4_pcie_probe(struct platform_device *pdev)
4900d0c5510SYoshihiro Shimoda {
4910d0c5510SYoshihiro Shimoda struct rcar_gen4_pcie *rcar;
4920d0c5510SYoshihiro Shimoda int err;
4930d0c5510SYoshihiro Shimoda
4940d0c5510SYoshihiro Shimoda rcar = rcar_gen4_pcie_alloc(pdev);
4950d0c5510SYoshihiro Shimoda if (IS_ERR(rcar))
4960d0c5510SYoshihiro Shimoda return PTR_ERR(rcar);
4970d0c5510SYoshihiro Shimoda
4980d0c5510SYoshihiro Shimoda err = rcar_gen4_pcie_get_resources(rcar);
4990d0c5510SYoshihiro Shimoda if (err)
5000d0c5510SYoshihiro Shimoda return err;
5010d0c5510SYoshihiro Shimoda
5020d0c5510SYoshihiro Shimoda err = rcar_gen4_pcie_prepare(rcar);
5030d0c5510SYoshihiro Shimoda if (err)
5040d0c5510SYoshihiro Shimoda return err;
5050d0c5510SYoshihiro Shimoda
506e311b383SYoshihiro Shimoda err = rcar_gen4_add_dw_pcie(rcar);
5070d0c5510SYoshihiro Shimoda if (err)
5080d0c5510SYoshihiro Shimoda goto err_unprepare;
5090d0c5510SYoshihiro Shimoda
5100d0c5510SYoshihiro Shimoda return 0;
5110d0c5510SYoshihiro Shimoda
5120d0c5510SYoshihiro Shimoda err_unprepare:
5130d0c5510SYoshihiro Shimoda rcar_gen4_pcie_unprepare(rcar);
5140d0c5510SYoshihiro Shimoda
5150d0c5510SYoshihiro Shimoda return err;
5160d0c5510SYoshihiro Shimoda }
5170d0c5510SYoshihiro Shimoda
rcar_gen4_remove_dw_pcie(struct rcar_gen4_pcie * rcar)518e311b383SYoshihiro Shimoda static void rcar_gen4_remove_dw_pcie(struct rcar_gen4_pcie *rcar)
519e311b383SYoshihiro Shimoda {
520ac1d89f8SYoshihiro Shimoda switch (rcar->drvdata->mode) {
521e311b383SYoshihiro Shimoda case DW_PCIE_RC_TYPE:
522e311b383SYoshihiro Shimoda rcar_gen4_remove_dw_pcie_rp(rcar);
523e311b383SYoshihiro Shimoda break;
524e311b383SYoshihiro Shimoda case DW_PCIE_EP_TYPE:
525e311b383SYoshihiro Shimoda rcar_gen4_remove_dw_pcie_ep(rcar);
526e311b383SYoshihiro Shimoda break;
527e311b383SYoshihiro Shimoda default:
528e311b383SYoshihiro Shimoda break;
529e311b383SYoshihiro Shimoda }
530e311b383SYoshihiro Shimoda }
531e311b383SYoshihiro Shimoda
rcar_gen4_pcie_remove(struct platform_device * pdev)5320d0c5510SYoshihiro Shimoda static void rcar_gen4_pcie_remove(struct platform_device *pdev)
5330d0c5510SYoshihiro Shimoda {
5340d0c5510SYoshihiro Shimoda struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
5350d0c5510SYoshihiro Shimoda
536e311b383SYoshihiro Shimoda rcar_gen4_remove_dw_pcie(rcar);
5370d0c5510SYoshihiro Shimoda rcar_gen4_pcie_unprepare(rcar);
5380d0c5510SYoshihiro Shimoda }
5390d0c5510SYoshihiro Shimoda
r8a779f0_pcie_ltssm_control(struct rcar_gen4_pcie * rcar,bool enable)5402c49151bSYoshihiro Shimoda static int r8a779f0_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable)
5412c49151bSYoshihiro Shimoda {
5422c49151bSYoshihiro Shimoda u32 val;
5432c49151bSYoshihiro Shimoda
5442c49151bSYoshihiro Shimoda val = readl(rcar->base + PCIERSTCTRL1);
5452c49151bSYoshihiro Shimoda if (enable) {
5462c49151bSYoshihiro Shimoda val |= APP_LTSSM_ENABLE;
5472c49151bSYoshihiro Shimoda val &= ~APP_HOLD_PHY_RST;
5482c49151bSYoshihiro Shimoda } else {
5492c49151bSYoshihiro Shimoda /*
5502c49151bSYoshihiro Shimoda * Since the datasheet of R-Car doesn't mention how to assert
5512c49151bSYoshihiro Shimoda * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
5522c49151bSYoshihiro Shimoda * hang-up issue happened in the dw_edma_core_off() when
5532c49151bSYoshihiro Shimoda * the controller didn't detect a PCI device.
5542c49151bSYoshihiro Shimoda */
5552c49151bSYoshihiro Shimoda val &= ~APP_LTSSM_ENABLE;
5562c49151bSYoshihiro Shimoda }
5572c49151bSYoshihiro Shimoda writel(val, rcar->base + PCIERSTCTRL1);
5582c49151bSYoshihiro Shimoda
5592c49151bSYoshihiro Shimoda return 0;
5602c49151bSYoshihiro Shimoda }
5612c49151bSYoshihiro Shimoda
rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie * rcar)562faf5a975SYoshihiro Shimoda static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *rcar)
563faf5a975SYoshihiro Shimoda {
564faf5a975SYoshihiro Shimoda struct dw_pcie *dw = &rcar->dw;
565faf5a975SYoshihiro Shimoda u32 val;
566faf5a975SYoshihiro Shimoda
567faf5a975SYoshihiro Shimoda val = dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW);
568faf5a975SYoshihiro Shimoda val &= ~PORT_LANE_SKEW_INSERT_MASK;
569faf5a975SYoshihiro Shimoda if (dw->num_lanes < 4)
570faf5a975SYoshihiro Shimoda val |= BIT(6);
571faf5a975SYoshihiro Shimoda dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val);
572faf5a975SYoshihiro Shimoda
573faf5a975SYoshihiro Shimoda val = readl(rcar->base + PCIEPWRMNGCTRL);
574faf5a975SYoshihiro Shimoda val |= APP_CLK_REQ_N | APP_CLK_PM_EN;
575faf5a975SYoshihiro Shimoda writel(val, rcar->base + PCIEPWRMNGCTRL);
576faf5a975SYoshihiro Shimoda }
577faf5a975SYoshihiro Shimoda
rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie * rcar,u32 offset,u32 mask,u32 val)578faf5a975SYoshihiro Shimoda static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar,
579faf5a975SYoshihiro Shimoda u32 offset, u32 mask, u32 val)
580faf5a975SYoshihiro Shimoda {
581faf5a975SYoshihiro Shimoda u32 tmp;
582faf5a975SYoshihiro Shimoda
583faf5a975SYoshihiro Shimoda tmp = readl(rcar->phy_base + offset);
584faf5a975SYoshihiro Shimoda tmp &= ~mask;
585faf5a975SYoshihiro Shimoda tmp |= val;
586faf5a975SYoshihiro Shimoda writel(tmp, rcar->phy_base + offset);
587faf5a975SYoshihiro Shimoda }
588faf5a975SYoshihiro Shimoda
589faf5a975SYoshihiro Shimoda /*
590faf5a975SYoshihiro Shimoda * SoC datasheet suggests checking port logic register bits during firmware
591faf5a975SYoshihiro Shimoda * write. If read returns non-zero value, then this function returns -EAGAIN
592faf5a975SYoshihiro Shimoda * indicating that the write needs to be done again. If read returns zero,
593faf5a975SYoshihiro Shimoda * then return 0 to indicate success.
594faf5a975SYoshihiro Shimoda */
rcar_gen4_pcie_reg_test_bit(struct rcar_gen4_pcie * rcar,u32 offset,u32 mask)595faf5a975SYoshihiro Shimoda static int rcar_gen4_pcie_reg_test_bit(struct rcar_gen4_pcie *rcar,
596faf5a975SYoshihiro Shimoda u32 offset, u32 mask)
597faf5a975SYoshihiro Shimoda {
598faf5a975SYoshihiro Shimoda struct dw_pcie *dw = &rcar->dw;
599faf5a975SYoshihiro Shimoda
600faf5a975SYoshihiro Shimoda if (dw_pcie_readl_dbi(dw, offset) & mask)
601faf5a975SYoshihiro Shimoda return -EAGAIN;
602faf5a975SYoshihiro Shimoda
603faf5a975SYoshihiro Shimoda return 0;
604faf5a975SYoshihiro Shimoda }
605faf5a975SYoshihiro Shimoda
rcar_gen4_pcie_download_phy_firmware(struct rcar_gen4_pcie * rcar)606faf5a975SYoshihiro Shimoda static int rcar_gen4_pcie_download_phy_firmware(struct rcar_gen4_pcie *rcar)
607faf5a975SYoshihiro Shimoda {
608faf5a975SYoshihiro Shimoda /* The check_addr values are magical numbers in the datasheet */
609faf5a975SYoshihiro Shimoda const u32 check_addr[] = { 0x00101018, 0x00101118, 0x00101021, 0x00101121};
610faf5a975SYoshihiro Shimoda struct dw_pcie *dw = &rcar->dw;
611faf5a975SYoshihiro Shimoda const struct firmware *fw;
612faf5a975SYoshihiro Shimoda unsigned int i, timeout;
613faf5a975SYoshihiro Shimoda u32 data;
614faf5a975SYoshihiro Shimoda int ret;
615faf5a975SYoshihiro Shimoda
616faf5a975SYoshihiro Shimoda ret = request_firmware(&fw, RCAR_GEN4_PCIE_FIRMWARE_NAME, dw->dev);
617faf5a975SYoshihiro Shimoda if (ret) {
618faf5a975SYoshihiro Shimoda dev_err(dw->dev, "Failed to load firmware (%s): %d\n",
619faf5a975SYoshihiro Shimoda RCAR_GEN4_PCIE_FIRMWARE_NAME, ret);
620faf5a975SYoshihiro Shimoda return ret;
621faf5a975SYoshihiro Shimoda }
622faf5a975SYoshihiro Shimoda
623faf5a975SYoshihiro Shimoda for (i = 0; i < (fw->size / 2); i++) {
624faf5a975SYoshihiro Shimoda data = fw->data[(i * 2) + 1] << 8 | fw->data[i * 2];
625faf5a975SYoshihiro Shimoda timeout = 100;
626faf5a975SYoshihiro Shimoda do {
627faf5a975SYoshihiro Shimoda dw_pcie_writel_dbi(dw, PRTLGC89, RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR + i);
628faf5a975SYoshihiro Shimoda dw_pcie_writel_dbi(dw, PRTLGC90, data);
629faf5a975SYoshihiro Shimoda if (!rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC89, BIT(30)))
630faf5a975SYoshihiro Shimoda break;
631faf5a975SYoshihiro Shimoda if (!(--timeout)) {
632faf5a975SYoshihiro Shimoda ret = -ETIMEDOUT;
633faf5a975SYoshihiro Shimoda goto exit;
634faf5a975SYoshihiro Shimoda }
635faf5a975SYoshihiro Shimoda usleep_range(100, 200);
636faf5a975SYoshihiro Shimoda } while (1);
637faf5a975SYoshihiro Shimoda }
638faf5a975SYoshihiro Shimoda
639faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(17), BIT(17));
640faf5a975SYoshihiro Shimoda
641faf5a975SYoshihiro Shimoda for (i = 0; i < ARRAY_SIZE(check_addr); i++) {
642faf5a975SYoshihiro Shimoda timeout = 100;
643faf5a975SYoshihiro Shimoda do {
644faf5a975SYoshihiro Shimoda dw_pcie_writel_dbi(dw, PRTLGC89, check_addr[i]);
645faf5a975SYoshihiro Shimoda ret = rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC89, BIT(30));
646faf5a975SYoshihiro Shimoda ret |= rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC90, BIT(0));
647faf5a975SYoshihiro Shimoda if (!ret)
648faf5a975SYoshihiro Shimoda break;
649faf5a975SYoshihiro Shimoda if (!(--timeout)) {
650faf5a975SYoshihiro Shimoda ret = -ETIMEDOUT;
651faf5a975SYoshihiro Shimoda goto exit;
652faf5a975SYoshihiro Shimoda }
653faf5a975SYoshihiro Shimoda usleep_range(100, 200);
654faf5a975SYoshihiro Shimoda } while (1);
655faf5a975SYoshihiro Shimoda }
656faf5a975SYoshihiro Shimoda
657faf5a975SYoshihiro Shimoda exit:
658faf5a975SYoshihiro Shimoda release_firmware(fw);
659faf5a975SYoshihiro Shimoda
660faf5a975SYoshihiro Shimoda return ret;
661faf5a975SYoshihiro Shimoda }
662faf5a975SYoshihiro Shimoda
rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie * rcar,bool enable)663faf5a975SYoshihiro Shimoda static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable)
664faf5a975SYoshihiro Shimoda {
665faf5a975SYoshihiro Shimoda struct dw_pcie *dw = &rcar->dw;
666faf5a975SYoshihiro Shimoda u32 val;
667faf5a975SYoshihiro Shimoda int ret;
668faf5a975SYoshihiro Shimoda
669faf5a975SYoshihiro Shimoda if (!enable) {
670faf5a975SYoshihiro Shimoda val = readl(rcar->base + PCIERSTCTRL1);
671faf5a975SYoshihiro Shimoda val &= ~APP_LTSSM_ENABLE;
672faf5a975SYoshihiro Shimoda writel(val, rcar->base + PCIERSTCTRL1);
673faf5a975SYoshihiro Shimoda
674faf5a975SYoshihiro Shimoda return 0;
675faf5a975SYoshihiro Shimoda }
676faf5a975SYoshihiro Shimoda
677faf5a975SYoshihiro Shimoda val = dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE);
678faf5a975SYoshihiro Shimoda val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
679faf5a975SYoshihiro Shimoda dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val);
680faf5a975SYoshihiro Shimoda
681faf5a975SYoshihiro Shimoda val = readl(rcar->base + PCIEMSR0);
682faf5a975SYoshihiro Shimoda val |= APP_SRIS_MODE;
683faf5a975SYoshihiro Shimoda writel(val, rcar->base + PCIEMSR0);
684faf5a975SYoshihiro Shimoda
685faf5a975SYoshihiro Shimoda /*
686faf5a975SYoshihiro Shimoda * The R-Car Gen4 datasheet doesn't describe the PHY registers' name.
687faf5a975SYoshihiro Shimoda * But, the initialization procedure describes these offsets. So,
688faf5a975SYoshihiro Shimoda * this driver has magical offset numbers.
689faf5a975SYoshihiro Shimoda */
690faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(28), 0);
691faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(20), 0);
692faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(12), 0);
693faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(4), 0);
694faf5a975SYoshihiro Shimoda
695faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(23, 22), BIT(22));
696faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(18, 16), GENMASK(17, 16));
697faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(7, 6), BIT(6));
698faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(2, 0), GENMASK(11, 0));
699faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x1d4, GENMASK(16, 15), GENMASK(16, 15));
700faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x514, BIT(26), BIT(26));
701faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(16), 0);
702faf5a975SYoshihiro Shimoda rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(19), BIT(19));
703faf5a975SYoshihiro Shimoda
704faf5a975SYoshihiro Shimoda val = readl(rcar->base + PCIERSTCTRL1);
705faf5a975SYoshihiro Shimoda val &= ~APP_HOLD_PHY_RST;
706faf5a975SYoshihiro Shimoda writel(val, rcar->base + PCIERSTCTRL1);
707faf5a975SYoshihiro Shimoda
708faf5a975SYoshihiro Shimoda ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, !(val & BIT(18)), 100, 10000);
709faf5a975SYoshihiro Shimoda if (ret < 0)
710faf5a975SYoshihiro Shimoda return ret;
711faf5a975SYoshihiro Shimoda
712faf5a975SYoshihiro Shimoda ret = rcar_gen4_pcie_download_phy_firmware(rcar);
713faf5a975SYoshihiro Shimoda if (ret)
714faf5a975SYoshihiro Shimoda return ret;
715faf5a975SYoshihiro Shimoda
716faf5a975SYoshihiro Shimoda val = readl(rcar->base + PCIERSTCTRL1);
717faf5a975SYoshihiro Shimoda val |= APP_LTSSM_ENABLE;
718faf5a975SYoshihiro Shimoda writel(val, rcar->base + PCIERSTCTRL1);
719faf5a975SYoshihiro Shimoda
720faf5a975SYoshihiro Shimoda return 0;
721faf5a975SYoshihiro Shimoda }
722faf5a975SYoshihiro Shimoda
7232c49151bSYoshihiro Shimoda static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie = {
7242c49151bSYoshihiro Shimoda .ltssm_control = r8a779f0_pcie_ltssm_control,
7252c49151bSYoshihiro Shimoda .mode = DW_PCIE_RC_TYPE,
7262c49151bSYoshihiro Shimoda };
7272c49151bSYoshihiro Shimoda
7282c49151bSYoshihiro Shimoda static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep = {
7292c49151bSYoshihiro Shimoda .ltssm_control = r8a779f0_pcie_ltssm_control,
7302c49151bSYoshihiro Shimoda .mode = DW_PCIE_EP_TYPE,
7312c49151bSYoshihiro Shimoda };
7322c49151bSYoshihiro Shimoda
733ac1d89f8SYoshihiro Shimoda static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie = {
734faf5a975SYoshihiro Shimoda .additional_common_init = rcar_gen4_pcie_additional_common_init,
735faf5a975SYoshihiro Shimoda .ltssm_control = rcar_gen4_pcie_ltssm_control,
736ac1d89f8SYoshihiro Shimoda .mode = DW_PCIE_RC_TYPE,
737ac1d89f8SYoshihiro Shimoda };
738ac1d89f8SYoshihiro Shimoda
739ac1d89f8SYoshihiro Shimoda static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep = {
740faf5a975SYoshihiro Shimoda .additional_common_init = rcar_gen4_pcie_additional_common_init,
741faf5a975SYoshihiro Shimoda .ltssm_control = rcar_gen4_pcie_ltssm_control,
742ac1d89f8SYoshihiro Shimoda .mode = DW_PCIE_EP_TYPE,
743ac1d89f8SYoshihiro Shimoda };
744ac1d89f8SYoshihiro Shimoda
7450d0c5510SYoshihiro Shimoda static const struct of_device_id rcar_gen4_pcie_of_match[] = {
746e311b383SYoshihiro Shimoda {
7472c49151bSYoshihiro Shimoda .compatible = "renesas,r8a779f0-pcie",
7482c49151bSYoshihiro Shimoda .data = &drvdata_r8a779f0_pcie,
7492c49151bSYoshihiro Shimoda },
7502c49151bSYoshihiro Shimoda {
7512c49151bSYoshihiro Shimoda .compatible = "renesas,r8a779f0-pcie-ep",
7522c49151bSYoshihiro Shimoda .data = &drvdata_r8a779f0_pcie_ep,
7532c49151bSYoshihiro Shimoda },
7542c49151bSYoshihiro Shimoda {
755e311b383SYoshihiro Shimoda .compatible = "renesas,rcar-gen4-pcie",
756ac1d89f8SYoshihiro Shimoda .data = &drvdata_rcar_gen4_pcie,
757e311b383SYoshihiro Shimoda },
758e311b383SYoshihiro Shimoda {
759e311b383SYoshihiro Shimoda .compatible = "renesas,rcar-gen4-pcie-ep",
760ac1d89f8SYoshihiro Shimoda .data = &drvdata_rcar_gen4_pcie_ep,
761e311b383SYoshihiro Shimoda },
7620d0c5510SYoshihiro Shimoda {},
7630d0c5510SYoshihiro Shimoda };
7640d0c5510SYoshihiro Shimoda MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match);
7650d0c5510SYoshihiro Shimoda
7660d0c5510SYoshihiro Shimoda static struct platform_driver rcar_gen4_pcie_driver = {
7670d0c5510SYoshihiro Shimoda .driver = {
7680d0c5510SYoshihiro Shimoda .name = "pcie-rcar-gen4",
7690d0c5510SYoshihiro Shimoda .of_match_table = rcar_gen4_pcie_of_match,
7700d0c5510SYoshihiro Shimoda .probe_type = PROBE_PREFER_ASYNCHRONOUS,
7710d0c5510SYoshihiro Shimoda },
7720d0c5510SYoshihiro Shimoda .probe = rcar_gen4_pcie_probe,
7730d0c5510SYoshihiro Shimoda .remove_new = rcar_gen4_pcie_remove,
7740d0c5510SYoshihiro Shimoda };
7750d0c5510SYoshihiro Shimoda module_platform_driver(rcar_gen4_pcie_driver);
7760d0c5510SYoshihiro Shimoda
7770d0c5510SYoshihiro Shimoda MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe controller driver");
7780d0c5510SYoshihiro Shimoda MODULE_LICENSE("GPL");
779