| /freebsd/sys/contrib/device-tree/include/dt-bindings/dma/ |
| H A D | dw-dmac.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
7 * Protection Control bits provide protection against illegal transactions.
8 * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
11 #define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */
12 #define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */
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| /freebsd/sys/contrib/device-tree/Bindings/dma/ |
| H A D | snps-dma.txt | 1 * Synopsys Designware DMA Controller
4 - compatible: "snps,dma-spear1340"
5 - reg: Address range of the DMAC registers
6 - interrupt: Should contain the DMAC interrupt number
7 - dma-channels: Number of channels supported by hardware
8 - dma-requests: Number of DMA request lines supported, up to 16
9 - dma-masters: Number of AHB masters supported by the controller
10 - #dma-cells: must be <3>
11 - chan_allocation_order: order of allocation of channel, 0 (default): ascending,
13 - chan_priority: priority of channels. 0 (default): increase from chan 0->n, 1:
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| H A D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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| /freebsd/sys/contrib/device-tree/Bindings/reserved-memory/ |
| H A D | shared-dma-pool.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/shared-dma-pool.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: /reserved-memory DMA pool
10 - devicetree-spec@vger.kernel.org
13 - $ref: reserved-memory.yaml
18 - const: shared-dma-pool
21 pool of DMA buffers for a set of devices. It can be used by an
25 - const: restricted-dma-pool
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| /freebsd/sys/dev/flash/ |
| H A D | cqspi.h | 1 /*-
2 * Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
87 #define CQSPI_DMAPER 0x20 /* DMA Peripheral Configuration Register */
102 #define CQSPI_LOWWRPROT 0x50 /* Lower Write Protection */
103 #define CQSPI_UPPWRPROT 0x54 /* Upper Write Protection */
104 #define CQSPI_WRPROT 0x58 /* Write Protection Control Register */
105 #define CQSPI_INDRD 0x60 /* Indirect Read Transfer Control Register */
111 #define CQSPI_INDWR 0x70 /* Indirect Write Transfer Control Register */
115 #define CQSPI_FLASHCMD 0x90 /* Flash Command Control Register */
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| H A D | snps,dw-pcie-ep.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie-ep
23 - compatible
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | brcm,brcmnand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Brian Norris <computersforpeace@gmail.com>
11 - Kamal Dasu <kdasu.kdev@gmail.com>
12 - William Zhang <william.zhang@broadcom.com>
15 The Broadcom Set-Top Box NAND controller supports low-level access to raw NAND
16 flash chips. It has a memory-mapped register interface for both control
18 is paired with a custom DMA engine (inventively named "Flash DMA") which
27 -- Additional SoC-specific NAND controller properties --
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| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_udma_regs_m2s.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
83 * [0x0] DMA state.
84 * 00 - No pending tasks
90 /* [0x4] CPU request to change DMA state */
94 * [0xc] M2S DMA error log mask.
96 * This register determines if these errors cause the M2S DMA to log the
98 * 0 - Log is enabled.
99 * 1 - Log is masked.
104 * [0x14] DMA header log.
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| H A D | al_hal_udma_regs_s2m.h | 1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
85 * [0x0] DMA state
86 * 00 - No pending tasks
92 /* [0x4] CPU request to change DMA state */
96 * [0xc] S2M DMA error log mask.
98 * This register determines if these errors cause the S2M DMA to log the
100 * 0 - Log is enable
101 * 1 - Log is masked.
106 * [0x14] DMA header log
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| /freebsd/sys/dev/wtap/ |
| H A D | if_wtapioctl.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2010-2011 Monthadar Al Jaberi, TerraNet AB
7 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
36 * Ioctl-related defintions for the Wireless TAP
73 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
77 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
78 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
85 u_int32_t ast_tx_protect; /* tx frames with protection */
89 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
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| /freebsd/sys/dev/ath/ |
| H A D | if_athioctl.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
33 * Ioctl-related defintions for the Atheros Wireless LAN controller driver.
78 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */
82 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */
83 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */
90 u_int32_t ast_tx_protect; /* tx frames with protection */
94 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */
102 /* rx PHY error per-code counts */
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| H A D | if_ath_tx.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2010-2012 Adrian Chadd, Xenion Pty Ltd
116 * What queue to throw the non-QoS TID traffic into
148 if (bf->bf_nseg == 0) in ath_tx_alq_post()
150 n = ((bf->bf_nseg - 1) / sc->sc_tx_nmaps) + 1; in ath_tx_alq_post()
151 for (i = 0, ds = (const char *) bf->bf_desc; in ath_tx_alq_post()
153 i++, ds += sc->sc_tx_desclen) { in ath_tx_alq_post()
154 if_ath_alq_post(&sc->sc_alq, in ath_tx_alq_post()
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| /freebsd/sys/dev/ath/ath_hal/ar5211/ |
| H A D | ar5211reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2006 Atheros Communications, Inc.
31 /* DMA Control and Interrupt Registers */
32 #define AR_CR 0x0008 /* control register */
38 #define AR_TXCFG 0x0030 /* tx DMA size config register */
39 #define AR_RXCFG 0x0034 /* rx DMA size config register */
41 #define AR_MIBC 0x0040 /* MIB control register */
47 #define AR_MACMISC 0x0058 /* miscellaneous control/status */
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| /freebsd/sys/dev/mwl/ |
| H A D | mwlhal.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
5 * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
39 #define MWL_MBSS_SUPPORT /* enable multi-bss support */
85 * Query whether multi-bss support is available/enabled.
132 cause = bus_space_read_4(mh->mh_iot, mh->mh_ioh, in mwl_hal_getisr()
138 bus_space_write_4(mh->mh_iot, mh->mh_ioh, in mwl_hal_getisr()
139 MACREG_REG_A2H_INTERRUPT_CAUSE, cause &~ mh->mh_imask); in mwl_hal_getisr()
140 (void) bus_space_read_4(mh->mh_iot, mh->mh_ioh, in mwl_hal_getisr()
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| /freebsd/sys/contrib/dev/acpica/components/hardware/ |
| H A D | hwvalid.c | 3 * Module Name: hwvalid - I/O request validation
11 * Some or all of this work - Copyright (c) 1999 - 2024, Intel Corp.
28 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
104 * re-exports any such software from a foreign destination, Licensee shall
105 * ensure that the distribution and export/re-export of the software is in
108 * any of its subsidiaries will export/re-export any technical data, process,
130 * 3. Neither the names of the above-listed copyright holders nor the names
179 * DMA: DMA controller
183 * RTC: Real-time clock
185 * DMA1: DMA 1 page registers
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| /freebsd/sys/contrib/device-tree/Bindings/arm/ |
| H A D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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| /freebsd/sys/contrib/device-tree/Bindings/cache/ |
| H A D | l2c2x0.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
16 models (Note 1). Some of the properties that are just prefixed "cache-*" are
22 cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
28 - $ref: /schemas/cache-controller.yaml#
33 - enum:
34 - arm,pl310-cache
35 - arm,l220-cache
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| /freebsd/sys/dev/ath/ath_hal/ar5212/ |
| H A D | ar5212reg.h | 1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Copyright (c) 2002-2008 Atheros Communications, Inc.
26 /* DMA Control and Interrupt Registers */
27 #define AR_CR 0x0008 /* MAC control register */
33 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */
34 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */
36 #define AR_MIBC 0x0040 /* MAC MIB control register */
42 #define AR_MACMISC 0x0058 /* MAC miscellaneous control/status register */
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| /freebsd/sys/contrib/ncsw/inc/flib/ |
| H A D | fsl_fman.h | 50 uint8_t num_backup_pools; /**< Number of BM backup pools -
73 considered for depletion (Note - this
76 will be sent after a single-pool
80 considered for depletion (Note - this
89 @Description Enum for defining port DMA swap mode
100 @Description Enum for defining port DMA cache attributes
130 uint32_t fmfp_tnc; /**< FPM TNUM Control 0x00 */
132 uint32_t fmfp_brkc; /**< FPM Breakpoint Control 0x08 */
133 uint32_t fmfp_mxd; /**< FPM Flush Control 0x0c */
138 uint32_t fmfp_fcev[4]; /**< FPM FMan-Controller Event 1-4 0x20-0x2f */
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| /freebsd/sys/dev/iser/ |
| H A D | icl_iser.h | 1 /*-
100 #define MASK_4K (~(SIZE_4K-1))
119 * supports -EAGAIN scheme where tx is suspended till the QP has room for more *
131 - ISER_MAX_TX_MISC_PDUS \
132 - ISER_MAX_RX_MISC_PDUS - 1) / \
158 * struct iser_hdr - iSER header
211 * struct iser_mem_reg - iSER memory registration info
230 * struct iser_data_buf - iSER data buffer
240 * @sg_single: SG-ified clone of a non SG SC or
260 * struct iser_tx_desc - iSER TX descriptor (for send wr_id)
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| /freebsd/sys/arm/ti/ |
| H A D | ti_edma3.c | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
101 * We use one-element array in case if we need to add
102 * mem resources for transfer control windows
113 { -1, 0, 0 }
119 { -1, 0, 0 }
123 #define ti_edma3_cc_rd_4(reg) bus_read_4(ti_edma3_sc->mem_res[0], reg)
124 #define ti_edma3_cc_wr_4(reg, val) bus_write_4(ti_edma3_sc->mem_res[0], reg, val)
135 { ti_edma3_intr_mperr, "EDMA Memory Protection Error Interrupt" },
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| /freebsd/sys/dev/usb/controller/ |
| H A D | ehci_imx.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2010-2012 Semihalf
71 * refers to them as "core" and "non-core" registers. A set of core register
72 * exists for each OTG or EHCI device. There is a single set of non-core
73 * registers per USBOH3, and they control aspects of operation not directly
78 * non-core registers by using a pair of resource address/size values (two
82 * whose reg property describes the non-core registers. The way we handle FDT
83 * data, this means that the resources (memory-mapped register range) for the
84 * non-core registers belongs to a device other than the echi devices.
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| /freebsd/sys/contrib/dev/athk/ath10k/ |
| H A D | wmi.h | 1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
5 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
28 * 1. Add new WMI commands ONLY within the specified range - 0x9000 - 0x9fff
44 * variable is already 4-byte aligned by virtue of being a u32
53 /* Control Path */
526 * for wmi_services is 64 as target is using only 4-bits of each 32-bit
532 __le32_to_cpu((wmi_svc_bmap)[((svc_id) - (len)) / 28]) & \
533 BIT(((((svc_id) - (len)) % 28) & 0x1f) + 4))
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| /freebsd/sys/dev/ral/ |
| H A D | rt2860.c | 1 /*-
2 * Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
21 /*-
70 #define DPRINTF(x) do { if (sc->sc_debug > 0) printf x; } while (0)
71 #define DPRINTFN(n, x) do { if (sc->sc_debug >= (n)) printf x; } while (0)
238 struct ieee80211com *ic = &sc->sc_ic; in rt2860_attach()
242 sc->sc_dev = dev; in rt2860_attach()
243 sc->sc_debug = 0; in rt2860_attach()
245 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, in rt2860_attach()
248 callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); in rt2860_attach()
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