1 /*-
2 * SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
3 */
4
5 /* $OpenBSD: if_iwxreg.h,v 1.51 2023/03/06 11:18:37 stsp Exp $ */
6
7 /*-
8 * Based on BSD-licensed source modules in the Linux iwlwifi driver,
9 * which were used as the reference documentation for this implementation.
10 *
11 ******************************************************************************
12 *
13 * This file is provided under a dual BSD/GPLv2 license. When using or
14 * redistributing this file, you may do so under either license.
15 *
16 * GPL LICENSE SUMMARY
17 *
18 * Copyright(c) 2017 Intel Deutschland GmbH
19 * Copyright(c) 2018 - 2019 Intel Corporation
20 *
21 * This program is free software; you can redistribute it and/or modify
22 * it under the terms of version 2 of the GNU General Public License as
23 * published by the Free Software Foundation.
24 *
25 * This program is distributed in the hope that it will be useful, but
26 * WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
28 * General Public License for more details.
29 *
30 * BSD LICENSE
31 *
32 * Copyright(c) 2017 Intel Deutschland GmbH
33 * Copyright(c) 2018 - 2019 Intel Corporation
34 * All rights reserved.
35 *
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
38 * are met:
39 *
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
45 * distribution.
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *
62 *****************************************************************************
63 */
64
65
66 /* maximum number of DRAM map entries supported by FW */
67 #define IWX_MAX_DRAM_ENTRY 64
68 #define IWX_CSR_CTXT_INFO_BA 0x40
69
70 /**
71 * enum iwx_context_info_flags - Context information control flags
72 * @IWX_CTXT_INFO_AUTO_FUNC_INIT: If set, FW will not wait before interrupting
73 * the init done for driver command that configures several system modes
74 * @IWX_CTXT_INFO_EARLY_DEBUG: enable early debug
75 * @IWX_CTXT_INFO_ENABLE_CDMP: enable core dump
76 * @IWX_CTXT_INFO_RB_CB_SIZE_POS: position of the RBD Cyclic Buffer Size
77 * exponent, the actual size is 2**value, valid sizes are 8-2048.
78 * The value is four bits long. Maximum valid exponent is 12
79 * @IWX_CTXT_INFO_TFD_FORMAT_LONG: use long TFD Format (the
80 * default is short format - not supported by the driver)
81 * @IWX_CTXT_INFO_RB_SIZE_POS: RB size position
82 * (values are IWX_CTXT_INFO_RB_SIZE_*K)
83 * @IWX_CTXT_INFO_RB_SIZE_1K: Value for 1K RB size
84 * @IWX_CTXT_INFO_RB_SIZE_2K: Value for 2K RB size
85 * @IWX_CTXT_INFO_RB_SIZE_4K: Value for 4K RB size
86 * @IWX_CTXT_INFO_RB_SIZE_8K: Value for 8K RB size
87 * @IWX_CTXT_INFO_RB_SIZE_12K: Value for 12K RB size
88 * @IWX_CTXT_INFO_RB_SIZE_16K: Value for 16K RB size
89 * @IWX_CTXT_INFO_RB_SIZE_20K: Value for 20K RB size
90 * @IWX_CTXT_INFO_RB_SIZE_24K: Value for 24K RB size
91 * @IWX_CTXT_INFO_RB_SIZE_28K: Value for 28K RB size
92 * @IWX_CTXT_INFO_RB_SIZE_32K: Value for 32K RB size
93 */
94 enum iwx_context_info_flags {
95 IWX_CTXT_INFO_AUTO_FUNC_INIT = (1 << 0),
96 IWX_CTXT_INFO_EARLY_DEBUG = (1 << 1),
97 IWX_CTXT_INFO_ENABLE_CDMP = (1 << 2),
98 IWX_CTXT_INFO_RB_CB_SIZE_POS = 4,
99 IWX_CTXT_INFO_TFD_FORMAT_LONG = (1 << 8),
100 IWX_CTXT_INFO_RB_SIZE_POS = 9,
101 IWX_CTXT_INFO_RB_SIZE_1K = 0x1,
102 IWX_CTXT_INFO_RB_SIZE_2K = 0x2,
103 IWX_CTXT_INFO_RB_SIZE_4K = 0x4,
104 IWX_CTXT_INFO_RB_SIZE_8K = 0x8,
105 IWX_CTXT_INFO_RB_SIZE_12K = 0x9,
106 IWX_CTXT_INFO_RB_SIZE_16K = 0xa,
107 IWX_CTXT_INFO_RB_SIZE_20K = 0xb,
108 IWX_CTXT_INFO_RB_SIZE_24K = 0xc,
109 IWX_CTXT_INFO_RB_SIZE_28K = 0xd,
110 IWX_CTXT_INFO_RB_SIZE_32K = 0xe,
111 };
112
113 /*
114 * struct iwx_context_info_version - version structure
115 * @mac_id: SKU and revision id
116 * @version: context information version id
117 * @size: the size of the context information in DWs
118 */
119 struct iwx_context_info_version {
120 uint16_t mac_id;
121 uint16_t version;
122 uint16_t size;
123 uint16_t reserved;
124 } __packed;
125
126 /*
127 * struct iwx_context_info_control - version structure
128 * @control_flags: context information flags see &enum iwx_context_info_flags
129 */
130 struct iwx_context_info_control {
131 uint32_t control_flags;
132 uint32_t reserved;
133 } __packed;
134
135 /*
136 * struct iwx_context_info_dram - images DRAM map
137 * each entry in the map represents a DRAM chunk of up to 32 KB
138 * @umac_img: UMAC image DRAM map
139 * @lmac_img: LMAC image DRAM map
140 * @virtual_img: paged image DRAM map
141 */
142 struct iwx_context_info_dram {
143 uint64_t umac_img[IWX_MAX_DRAM_ENTRY];
144 uint64_t lmac_img[IWX_MAX_DRAM_ENTRY];
145 uint64_t virtual_img[IWX_MAX_DRAM_ENTRY];
146 } __packed;
147
148 /*
149 * struct iwx_context_info_rbd_cfg - RBDs configuration
150 * @free_rbd_addr: default queue free RB CB base address
151 * @used_rbd_addr: default queue used RB CB base address
152 * @status_wr_ptr: default queue used RB status write pointer
153 */
154 struct iwx_context_info_rbd_cfg {
155 uint64_t free_rbd_addr;
156 uint64_t used_rbd_addr;
157 uint64_t status_wr_ptr;
158 } __packed;
159
160 /*
161 * struct iwx_context_info_hcmd_cfg - command queue configuration
162 * @cmd_queue_addr: address of command queue
163 * @cmd_queue_size: number of entries
164 */
165 struct iwx_context_info_hcmd_cfg {
166 uint64_t cmd_queue_addr;
167 uint8_t cmd_queue_size;
168 uint8_t reserved[7];
169 } __packed;
170
171 /*
172 * struct iwx_context_info_dump_cfg - Core Dump configuration
173 * @core_dump_addr: core dump (debug DRAM address) start address
174 * @core_dump_size: size, in DWs
175 */
176 struct iwx_context_info_dump_cfg {
177 uint64_t core_dump_addr;
178 uint32_t core_dump_size;
179 uint32_t reserved;
180 } __packed;
181
182 /*
183 * struct iwx_context_info_pnvm_cfg - platform NVM data configuration
184 * @platform_nvm_addr: Platform NVM data start address
185 * @platform_nvm_size: size in DWs
186 */
187 struct iwx_context_info_pnvm_cfg {
188 uint64_t platform_nvm_addr;
189 uint32_t platform_nvm_size;
190 uint32_t reserved;
191 } __packed;
192
193 /*
194 * struct iwx_context_info_early_dbg_cfg - early debug configuration for
195 * dumping DRAM addresses
196 * @early_debug_addr: early debug start address
197 * @early_debug_size: size in DWs
198 */
199 struct iwx_context_info_early_dbg_cfg {
200 uint64_t early_debug_addr;
201 uint32_t early_debug_size;
202 uint32_t reserved;
203 } __packed;
204
205 /*
206 * struct iwx_context_info - device INIT configuration
207 * @version: version information of context info and HW
208 * @control: control flags of FH configurations
209 * @rbd_cfg: default RX queue configuration
210 * @hcmd_cfg: command queue configuration
211 * @dump_cfg: core dump data
212 * @edbg_cfg: early debug configuration
213 * @pnvm_cfg: platform nvm configuration
214 * @dram: firmware image addresses in DRAM
215 */
216 struct iwx_context_info {
217 struct iwx_context_info_version version;
218 struct iwx_context_info_control control;
219 uint64_t reserved0;
220 struct iwx_context_info_rbd_cfg rbd_cfg;
221 struct iwx_context_info_hcmd_cfg hcmd_cfg;
222 uint32_t reserved1[4];
223 struct iwx_context_info_dump_cfg dump_cfg;
224 struct iwx_context_info_early_dbg_cfg edbg_cfg;
225 struct iwx_context_info_pnvm_cfg pnvm_cfg;
226 uint32_t reserved2[16];
227 struct iwx_context_info_dram dram;
228 uint32_t reserved3[16];
229 } __packed;
230
231
232 /*
233 * Context info definitions for AX210 devices.
234 */
235
236 #define IWX_CSR_CTXT_INFO_BOOT_CTRL 0x0
237 #define IWX_CSR_CTXT_INFO_ADDR 0x118
238 #define IWX_CSR_IML_DATA_ADDR 0x120
239 #define IWX_CSR_IML_SIZE_ADDR 0x128
240 #define IWX_CSR_IML_RESP_ADDR 0x12c
241
242 /* Set bit for enabling automatic function boot */
243 #define IWX_CSR_AUTO_FUNC_BOOT_ENA (1 << 1)
244 /* Set bit for initiating function boot */
245 #define IWX_CSR_AUTO_FUNC_INIT (1 << 7)
246
247 /**
248 * iwx_prph_scratch_mtr_format - tfd size configuration
249 * @IWX_PRPH_MTR_FORMAT_16B: 16 bit tfd
250 * @IWX_PRPH_MTR_FORMAT_32B: 32 bit tfd
251 * @IWX_PRPH_MTR_FORMAT_64B: 64 bit tfd
252 * @IWX_PRPH_MTR_FORMAT_256B: 256 bit tfd
253 */
254 #define IWX_PRPH_MTR_FORMAT_16B 0x0
255 #define IWX_PRPH_MTR_FORMAT_32B 0x40000
256 #define IWX_PRPH_MTR_FORMAT_64B 0x80000
257 #define IWX_PRPH_MTR_FORMAT_256B 0xC0000
258
259 /**
260 * iwx_prph_scratch_flags - PRPH scratch control flags
261 * @IWX_PRPH_SCRATCH_IMR_DEBUG_EN: IMR support for debug
262 * @IWX_PRPH_SCRATCH_EARLY_DEBUG_EN: enable early debug conf
263 * @IWX_PRPH_SCRATCH_EDBG_DEST_DRAM: use DRAM, with size allocated
264 * in hwm config.
265 * @IWX_PRPH_SCRATCH_EDBG_DEST_INTERNAL: use buffer on SRAM
266 * @IWX_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER: use st arbiter, mainly for
267 * multicomm.
268 * @IWX_PRPH_SCRATCH_EDBG_DEST_TB22DTF: route debug data to SoC HW
269 * @IWX_PRPH_SCTATCH_RB_SIZE_4K: Use 4K RB size (the default is 2K)
270 * @IWX_PRPH_SCRATCH_MTR_MODE: format used for completion - 0: for
271 * completion descriptor, 1 for responses (legacy)
272 * @IWX_PRPH_SCRATCH_MTR_FORMAT: a mask for the size of the tfd.
273 * There are 4 optional values: 0: 16 bit, 1: 32 bit, 2: 64 bit,
274 * 3: 256 bit.
275 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_MASK: RB size full information, ignored
276 * by older firmware versions, so set IWX_PRPH_SCRATCH_RB_SIZE_4K
277 * appropriately; use the below values for this.
278 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_8K: 8kB RB size
279 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_12K: 12kB RB size
280 * @IWX_PRPH_SCRATCH_RB_SIZE_EXT_16K: 16kB RB size
281 */
282 #define IWX_PRPH_SCRATCH_IMR_DEBUG_EN (1 << 1)
283 #define IWX_PRPH_SCRATCH_EARLY_DEBUG_EN (1 << 4)
284 #define IWX_PRPH_SCRATCH_EDBG_DEST_DRAM (1 << 8)
285 #define IWX_PRPH_SCRATCH_EDBG_DEST_INTERNAL (1 << 9)
286 #define IWX_PRPH_SCRATCH_EDBG_DEST_ST_ARBITER (1 << 10)
287 #define IWX_PRPH_SCRATCH_EDBG_DEST_TB22DTF (1 << 11)
288 #define IWX_PRPH_SCRATCH_RB_SIZE_4K (1 << 16)
289 #define IWX_PRPH_SCRATCH_MTR_MODE (1 << 17)
290 #define IWX_PRPH_SCRATCH_MTR_FORMAT ((1 << 18) | (1 << 19))
291 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_MASK (0xf << 20)
292 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_8K (8 << 20)
293 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_12K (9 << 20)
294 #define IWX_PRPH_SCRATCH_RB_SIZE_EXT_16K (10 << 20)
295
296 /*
297 * struct iwx_prph_scratch_version - version structure
298 * @mac_id: SKU and revision id
299 * @version: prph scratch information version id
300 * @size: the size of the context information in DWs
301 * @reserved: reserved
302 */
303 struct iwx_prph_scratch_version {
304 uint16_t mac_id;
305 uint16_t version;
306 uint16_t size;
307 uint16_t reserved;
308 } __packed; /* PERIPH_SCRATCH_VERSION_S */
309
310 /*
311 * struct iwx_prph_scratch_control - control structure
312 * @control_flags: context information flags see &iwx_prph_scratch_flags
313 * @reserved: reserved
314 */
315 struct iwx_prph_scratch_control {
316 uint32_t control_flags;
317 uint32_t reserved;
318 } __packed; /* PERIPH_SCRATCH_CONTROL_S */
319
320 /*
321 * struct iwx_prph_scratch_pnvm_cfg - ror config
322 * @pnvm_base_addr: PNVM start address
323 * @pnvm_size: PNVM size in DWs
324 * @reserved: reserved
325 */
326 struct iwx_prph_scratch_pnvm_cfg {
327 uint64_t pnvm_base_addr;
328 uint32_t pnvm_size;
329 uint32_t reserved;
330 } __packed; /* PERIPH_SCRATCH_PNVM_CFG_S */
331
332 struct iwx_pnvm_section {
333 uint32_t offset;
334 const uint8_t data[];
335 } __packed;
336
337 /*
338 * struct iwx_prph_scratch_hwm_cfg - hwm config
339 * @hwm_base_addr: hwm start address
340 * @hwm_size: hwm size in DWs
341 * @debug_token_config: debug preset
342 */
343 struct iwx_prph_scratch_hwm_cfg {
344 uint64_t hwm_base_addr;
345 uint32_t hwm_size;
346 uint32_t debug_token_config;
347 } __packed; /* PERIPH_SCRATCH_HWM_CFG_S */
348
349 /*
350 * struct iwx_prph_scratch_rbd_cfg - RBDs configuration
351 * @free_rbd_addr: default queue free RB CB base address
352 * @reserved: reserved
353 */
354 struct iwx_prph_scratch_rbd_cfg {
355 uint64_t free_rbd_addr;
356 uint32_t reserved;
357 } __packed; /* PERIPH_SCRATCH_RBD_CFG_S */
358
359 /*
360 * struct iwx_prph_scratch_uefi_cfg - prph scratch reduce power table
361 * @base_addr: reduce power table address
362 * @size: table size in dwords
363 */
364 struct iwx_prph_scratch_uefi_cfg {
365 uint64_t base_addr;
366 uint32_t size;
367 uint32_t reserved;
368 } __packed; /* PERIPH_SCRATCH_UEFI_CFG_S */
369
370 /*
371 * struct iwx_prph_scratch_ctrl_cfg - prph scratch ctrl and config
372 * @version: version information of context info and HW
373 * @control: control flags of FH configurations
374 * @pnvm_cfg: ror configuration
375 * @hwm_cfg: hwm configuration
376 * @rbd_cfg: default RX queue configuration
377 */
378 struct iwx_prph_scratch_ctrl_cfg {
379 struct iwx_prph_scratch_version version;
380 struct iwx_prph_scratch_control control;
381 struct iwx_prph_scratch_pnvm_cfg pnvm_cfg;
382 struct iwx_prph_scratch_hwm_cfg hwm_cfg;
383 struct iwx_prph_scratch_rbd_cfg rbd_cfg;
384 struct iwx_prph_scratch_uefi_cfg reduce_power_cfg;
385 } __packed; /* PERIPH_SCRATCH_CTRL_CFG_S */
386
387 /*
388 * struct iwx_prph_scratch - peripheral scratch mapping
389 * @ctrl_cfg: control and configuration of prph scratch
390 * @dram: firmware images addresses in DRAM
391 * @reserved: reserved
392 */
393 struct iwx_prph_scratch {
394 struct iwx_prph_scratch_ctrl_cfg ctrl_cfg;
395 uint32_t reserved[12];
396 struct iwx_context_info_dram dram;
397 } __packed; /* PERIPH_SCRATCH_S */
398
399 /*
400 * struct iwx_prph_info - peripheral information
401 * @boot_stage_mirror: reflects the value in the Boot Stage CSR register
402 * @ipc_status_mirror: reflects the value in the IPC Status CSR register
403 * @sleep_notif: indicates the peripheral sleep status
404 * @reserved: reserved
405 */
406 struct iwx_prph_info {
407 uint32_t boot_stage_mirror;
408 uint32_t ipc_status_mirror;
409 uint32_t sleep_notif;
410 uint32_t reserved;
411 } __packed; /* PERIPH_INFO_S */
412
413 /*
414 * struct iwx_context_info_gen3 - device INIT configuration
415 * @version: version of the context information
416 * @size: size of context information in DWs
417 * @config: context in which the peripheral would execute - a subset of
418 * capability csr register published by the peripheral
419 * @prph_info_base_addr: the peripheral information structure start address
420 * @cr_head_idx_arr_base_addr: the completion ring head index array
421 * start address
422 * @tr_tail_idx_arr_base_addr: the transfer ring tail index array
423 * start address
424 * @cr_tail_idx_arr_base_addr: the completion ring tail index array
425 * start address
426 * @tr_head_idx_arr_base_addr: the transfer ring head index array
427 * start address
428 * @cr_idx_arr_size: number of entries in the completion ring index array
429 * @tr_idx_arr_size: number of entries in the transfer ring index array
430 * @mtr_base_addr: the message transfer ring start address
431 * @mcr_base_addr: the message completion ring start address
432 * @mtr_size: number of entries which the message transfer ring can hold
433 * @mcr_size: number of entries which the message completion ring can hold
434 * @mtr_doorbell_vec: the doorbell vector associated with the message
435 * transfer ring
436 * @mcr_doorbell_vec: the doorbell vector associated with the message
437 * completion ring
438 * @mtr_msi_vec: the MSI which shall be generated by the peripheral after
439 * completing a transfer descriptor in the message transfer ring
440 * @mcr_msi_vec: the MSI which shall be generated by the peripheral after
441 * completing a completion descriptor in the message completion ring
442 * @mtr_opt_header_size: the size of the optional header in the transfer
443 * descriptor associated with the message transfer ring in DWs
444 * @mtr_opt_footer_size: the size of the optional footer in the transfer
445 * descriptor associated with the message transfer ring in DWs
446 * @mcr_opt_header_size: the size of the optional header in the completion
447 * descriptor associated with the message completion ring in DWs
448 * @mcr_opt_footer_size: the size of the optional footer in the completion
449 * descriptor associated with the message completion ring in DWs
450 * @msg_rings_ctrl_flags: message rings control flags
451 * @prph_info_msi_vec: the MSI which shall be generated by the peripheral
452 * after updating the Peripheral Information structure
453 * @prph_scratch_base_addr: the peripheral scratch structure start address
454 * @prph_scratch_size: the size of the peripheral scratch structure in DWs
455 * @reserved: reserved
456 */
457 struct iwx_context_info_gen3 {
458 uint16_t version;
459 uint16_t size;
460 uint32_t config;
461 uint64_t prph_info_base_addr;
462 uint64_t cr_head_idx_arr_base_addr;
463 uint64_t tr_tail_idx_arr_base_addr;
464 uint64_t cr_tail_idx_arr_base_addr;
465 uint64_t tr_head_idx_arr_base_addr;
466 uint16_t cr_idx_arr_size;
467 uint16_t tr_idx_arr_size;
468 uint64_t mtr_base_addr;
469 uint64_t mcr_base_addr;
470 uint16_t mtr_size;
471 uint16_t mcr_size;
472 uint16_t mtr_doorbell_vec;
473 uint16_t mcr_doorbell_vec;
474 uint16_t mtr_msi_vec;
475 uint16_t mcr_msi_vec;
476 uint8_t mtr_opt_header_size;
477 uint8_t mtr_opt_footer_size;
478 uint8_t mcr_opt_header_size;
479 uint8_t mcr_opt_footer_size;
480 uint16_t msg_rings_ctrl_flags;
481 uint16_t prph_info_msi_vec;
482 uint64_t prph_scratch_base_addr;
483 uint32_t prph_scratch_size;
484 uint32_t reserved;
485 } __packed; /* IPC_CONTEXT_INFO_S */
486
487 #define IWX_MGMT_TID 15
488
489 #define IWX_MQ_RX_TABLE_SIZE 512
490
491 /* cb size is the exponent */
492 #define IWX_RX_QUEUE_CB_SIZE(x) ((sizeof(x) <= 4) ? (fls(x) - 1) : (flsl(x) - 1))
493
494 /*
495 * CSR (control and status registers)
496 *
497 * CSR registers are mapped directly into PCI bus space, and are accessible
498 * whenever platform supplies power to device, even when device is in
499 * low power states due to driver-invoked device resets
500 * (e.g. IWX_CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
501 *
502 * Use iwl_write32() and iwl_read32() family to access these registers;
503 * these provide simple PCI bus access, without waking up the MAC.
504 * Do not use iwl_write_direct32() family for these registers;
505 * no need to "grab nic access" via IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
506 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
507 * the CSR registers.
508 *
509 * NOTE: Device does need to be awake in order to read this memory
510 * via IWX_CSR_EEPROM and IWX_CSR_OTP registers
511 */
512 #define IWX_CSR_HW_IF_CONFIG_REG (0x000) /* hardware interface config */
513 #define IWX_CSR_INT_COALESCING (0x004) /* accum ints, 32-usec units */
514 #define IWX_CSR_INT (0x008) /* host interrupt status/ack */
515 #define IWX_CSR_INT_MASK (0x00c) /* host interrupt enable */
516 #define IWX_CSR_FH_INT_STATUS (0x010) /* busmaster int status/ack*/
517 #define IWX_CSR_GPIO_IN (0x018) /* read external chip pins */
518 #define IWX_CSR_RESET (0x020) /* busmaster enable, NMI, etc*/
519 #define IWX_CSR_GP_CNTRL (0x024)
520
521 /* 2nd byte of IWX_CSR_INT_COALESCING, not accessible via iwl_write32()! */
522 #define IWX_CSR_INT_PERIODIC_REG (0x005)
523
524 /*
525 * Hardware revision info
526 * Bit fields:
527 * 31-16: Reserved
528 * 15-4: Type of device: see IWX_CSR_HW_REV_TYPE_xxx definitions
529 * 3-2: Revision step: 0 = A, 1 = B, 2 = C, 3 = D
530 * 1-0: "Dash" (-) value, as in A-1, etc.
531 */
532 #define IWX_CSR_HW_REV (0x028)
533
534 /*
535 * RF ID revision info
536 * Bit fields:
537 * 31:24: Reserved (set to 0x0)
538 * 23:12: Type
539 * 11:8: Step (A - 0x0, B - 0x1, etc)
540 * 7:4: Dash
541 * 3:0: Flavor
542 */
543 #define IWX_CSR_HW_RF_ID (0x09c)
544
545
546 #define IWX_CSR_GIO_REG (0x03C)
547
548 /*
549 * UCODE-DRIVER GP (general purpose) mailbox registers.
550 * SET/CLR registers set/clear bit(s) if "1" is written.
551 */
552 #define IWX_CSR_UCODE_DRV_GP1 (0x054)
553 #define IWX_CSR_UCODE_DRV_GP1_SET (0x058)
554 #define IWX_CSR_UCODE_DRV_GP1_CLR (0x05c)
555 #define IWX_CSR_UCODE_DRV_GP2 (0x060)
556
557 #define IWX_CSR_MBOX_SET_REG (0x088)
558 #define IWX_CSR_MBOX_SET_REG_OS_ALIVE 0x20
559
560 #define IWX_CSR_DRAM_INT_TBL_REG (0x0A0)
561 #define IWX_CSR_MAC_SHADOW_REG_CTRL (0x0A8) /* 6000 and up */
562
563 /* LTR control */
564 #define IWX_CSR_LTR_LONG_VAL_AD (0x0d4)
565 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ 0x80000000
566 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_MASK 0x1c000000
567 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE_SHIFT 24
568 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_MASK 0x03ff0000
569 #define IWX_CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL_SHIFT 16
570 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_REQ 0x00008000
571 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_MASK 0x00001c00
572 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_SCALE_SHIFT 8
573 #define IWX_CSR_LTR_LONG_VAL_AD_SNOOP_VAL 0x000003ff
574 #define IWX_CSR_LTR_LONG_VAL_AD_SCALE_USEC 2
575
576 /* GIO Chicken Bits (PCI Express bus link power management) */
577 #define IWX_CSR_GIO_CHICKEN_BITS (0x100)
578
579 #define IWX_CSR_DBG_HPET_MEM_REG (0x240)
580 #define IWX_CSR_DBG_LINK_PWR_MGMT_REG (0x250)
581
582 /* Bits for IWX_CSR_HW_IF_CONFIG_REG */
583 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_DASH (0x00000003)
584 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP (0x0000000C)
585 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER (0x000000C0)
586 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_MAC_SI (0x00000100)
587 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI (0x00000200)
588 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE (0x00000C00)
589 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH (0x00003000)
590 #define IWX_CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP (0x0000C000)
591
592 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_DASH (0)
593 #define IWX_CSR_HW_IF_CONFIG_REG_POS_MAC_STEP (2)
594 #define IWX_CSR_HW_IF_CONFIG_REG_POS_BOARD_VER (6)
595 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE (10)
596 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_DASH (12)
597 #define IWX_CSR_HW_IF_CONFIG_REG_POS_PHY_STEP (14)
598
599 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A (0x00080000)
600 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
601 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY (0x00400000) /* PCI_OWN_SEM */
602 #define IWX_CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE (0x02000000) /* ME_OWN */
603 #define IWX_CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
604 #define IWX_CSR_HW_IF_CONFIG_REG_ENABLE_PME (0x10000000)
605 #define IWX_CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
606
607 #define IWX_CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
608 #define IWX_CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
609
610 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
611 * acknowledged (reset) by host writing "1" to flagged bits. */
612 #define IWX_CSR_INT_BIT_FH_RX (1U << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
613 #define IWX_CSR_INT_BIT_HW_ERR (1 << 29) /* DMA hardware error FH_INT[31] */
614 #define IWX_CSR_INT_BIT_RX_PERIODIC (1 << 28) /* Rx periodic */
615 #define IWX_CSR_INT_BIT_FH_TX (1 << 27) /* Tx DMA FH_INT[1:0] */
616 #define IWX_CSR_INT_BIT_SCD (1 << 26) /* TXQ pointer advanced */
617 #define IWX_CSR_INT_BIT_SW_ERR (1 << 25) /* uCode error */
618 #define IWX_CSR_INT_BIT_RF_KILL (1 << 7) /* HW RFKILL switch GP_CNTRL[27] toggled */
619 #define IWX_CSR_INT_BIT_CT_KILL (1 << 6) /* Critical temp (chip too hot) rfkill */
620 #define IWX_CSR_INT_BIT_SW_RX (1 << 3) /* Rx, command responses */
621 #define IWX_CSR_INT_BIT_WAKEUP (1 << 1) /* NIC controller waking up (pwr mgmt) */
622 #define IWX_CSR_INT_BIT_ALIVE (1 << 0) /* uCode interrupts once it initializes */
623
624 #define IWX_CSR_INI_SET_MASK (IWX_CSR_INT_BIT_FH_RX | \
625 IWX_CSR_INT_BIT_HW_ERR | \
626 IWX_CSR_INT_BIT_FH_TX | \
627 IWX_CSR_INT_BIT_SW_ERR | \
628 IWX_CSR_INT_BIT_RF_KILL | \
629 IWX_CSR_INT_BIT_SW_RX | \
630 IWX_CSR_INT_BIT_WAKEUP | \
631 IWX_CSR_INT_BIT_ALIVE | \
632 IWX_CSR_INT_BIT_RX_PERIODIC)
633
634 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
635 #define IWX_CSR_FH_INT_BIT_ERR (1U << 31) /* Error */
636 #define IWX_CSR_FH_INT_BIT_HI_PRIOR (1 << 30) /* High priority Rx, bypass coalescing */
637 #define IWX_CSR_FH_INT_BIT_RX_CHNL1 (1 << 17) /* Rx channel 1 */
638 #define IWX_CSR_FH_INT_BIT_RX_CHNL0 (1 << 16) /* Rx channel 0 */
639 #define IWX_CSR_FH_INT_BIT_TX_CHNL1 (1 << 1) /* Tx channel 1 */
640 #define IWX_CSR_FH_INT_BIT_TX_CHNL0 (1 << 0) /* Tx channel 0 */
641
642 #define IWX_CSR_FH_INT_RX_MASK (IWX_CSR_FH_INT_BIT_HI_PRIOR | \
643 IWX_CSR_FH_INT_BIT_RX_CHNL1 | \
644 IWX_CSR_FH_INT_BIT_RX_CHNL0)
645
646 #define IWX_CSR_FH_INT_TX_MASK (IWX_CSR_FH_INT_BIT_TX_CHNL1 | \
647 IWX_CSR_FH_INT_BIT_TX_CHNL0)
648
649 /**
650 * struct iwx_rx_transfer_desc - transfer descriptor AX210
651 * @addr: ptr to free buffer start address
652 * @rbid: unique tag of the buffer
653 * @reserved: reserved
654 */
655 struct iwx_rx_transfer_desc {
656 uint16_t rbid;
657 uint16_t reserved[3];
658 uint64_t addr;
659 };
660
661 #define IWX_RX_CD_FLAGS_FRAGMENTED (1 << 0)
662
663 /**
664 * struct iwx_rx_completion_desc - completion descriptor AX210
665 * @reserved1: reserved
666 * @rbid: unique tag of the received buffer
667 * @flags: flags (0: fragmented, all others: reserved)
668 * @reserved2: reserved
669 */
670 struct iwx_rx_completion_desc {
671 uint32_t reserved1;
672 uint16_t rbid;
673 uint8_t flags;
674 uint8_t reserved2[25];
675 };
676
677 /* RESET */
678 #define IWX_CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
679 #define IWX_CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
680 #define IWX_CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
681 #define IWX_CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
682 #define IWX_CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
683 #define IWX_CSR_RESET_LINK_PWR_MGMT_DISABLED (0x80000000)
684
685 /*
686 * GP (general purpose) CONTROL REGISTER
687 * Bit fields:
688 * 27: HW_RF_KILL_SW
689 * Indicates state of (platform's) hardware RF-Kill switch
690 * 26-24: POWER_SAVE_TYPE
691 * Indicates current power-saving mode:
692 * 000 -- No power saving
693 * 001 -- MAC power-down
694 * 010 -- PHY (radio) power-down
695 * 011 -- Error
696 * 9-6: SYS_CONFIG
697 * Indicates current system configuration, reflecting pins on chip
698 * as forced high/low by device circuit board.
699 * 4: GOING_TO_SLEEP
700 * Indicates MAC is entering a power-saving sleep power-down.
701 * Not a good time to access device-internal resources.
702 * 3: MAC_ACCESS_REQ
703 * Host sets this to request and maintain MAC wakeup, to allow host
704 * access to device-internal resources. Host must wait for
705 * MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
706 * device registers.
707 * 2: INIT_DONE
708 * Host sets this to put device into fully operational D0 power mode.
709 * Host resets this after SW_RESET to put device into low power mode.
710 * 0: MAC_CLOCK_READY
711 * Indicates MAC (ucode processor, etc.) is powered up and can run.
712 * Internal resources are accessible.
713 * NOTE: This does not indicate that the processor is actually running.
714 * NOTE: This does not indicate that device has completed
715 * init or post-power-down restore of internal SRAM memory.
716 * Use IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
717 * SRAM is restored and uCode is in normal operation mode.
718 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
719 * do not need to save/restore it.
720 * NOTE: After device reset, this bit remains "0" until host sets
721 * INIT_DONE
722 */
723 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
724 #define IWX_CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
725 #define IWX_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
726 #define IWX_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
727
728 #define IWX_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
729
730 #define IWX_CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
731 #define IWX_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN (0x04000000)
732 #define IWX_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
733
734
735 /* HW REV */
736 #define IWX_CSR_HW_REV_DASH(_val) (((_val) & 0x0000003) >> 0)
737 #define IWX_CSR_HW_REV_STEP(_val) (((_val) & 0x000000C) >> 2)
738 #define IWX_CSR_HW_REV_TYPE(_val) (((_val) & 0x000FFF0) >> 4)
739
740 #define IWX_CSR_HW_REV_TYPE_MSK (0x000FFF0)
741 #define IWX_CSR_HW_REV_TYPE_QU_B0 (0x0000334)
742 #define IWX_CSR_HW_REV_TYPE_QU_C0 (0x0000338)
743 #define IWX_CSR_HW_REV_TYPE_QUZ (0x0000354)
744 #define IWX_CSR_HW_REV_TYPE_SO (0x0000370)
745 #define IWX_CSR_HW_REV_TYPE_TY (0x0000420)
746
747 /* HW RFID */
748 #define IWX_CSR_HW_RFID_FLAVOR(_val) (((_val) & 0x000000F) >> 0)
749 #define IWX_CSR_HW_RFID_DASH(_val) (((_val) & 0x00000F0) >> 4)
750 #define IWX_CSR_HW_RFID_STEP(_val) (((_val) & 0x0000F00) >> 8)
751 #define IWX_CSR_HW_RFID_TYPE(_val) (((_val) & 0x0FFF000) >> 12)
752 #define IWX_CSR_HW_RFID_IS_CDB(_val) (((_val) & 0x10000000) >> 28)
753 #define IWX_CSR_HW_RFID_IS_JACKET(_val) (((_val) & 0x20000000) >> 29)
754
755 /* CSR GIO */
756 #define IWX_CSR_GIO_REG_VAL_L0S_DISABLED (0x00000002)
757
758 /*
759 * UCODE-DRIVER GP (general purpose) mailbox register 1
760 * Host driver and uCode write and/or read this register to communicate with
761 * each other.
762 * Bit fields:
763 * 4: UCODE_DISABLE
764 * Host sets this to request permanent halt of uCode, same as
765 * sending CARD_STATE command with "halt" bit set.
766 * 3: CT_KILL_EXIT
767 * Host sets this to request exit from CT_KILL state, i.e. host thinks
768 * device temperature is low enough to continue normal operation.
769 * 2: CMD_BLOCKED
770 * Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
771 * to release uCode to clear all Tx and command queues, enter
772 * unassociated mode, and power down.
773 * NOTE: Some devices also use HBUS_TARG_MBX_C register for this bit.
774 * 1: SW_BIT_RFKILL
775 * Host sets this when issuing CARD_STATE command to request
776 * device sleep.
777 * 0: MAC_SLEEP
778 * uCode sets this when preparing a power-saving power-down.
779 * uCode resets this when power-up is complete and SRAM is sane.
780 * NOTE: device saves internal SRAM data to host when powering down,
781 * and must restore this data after powering back up.
782 * MAC_SLEEP is the best indication that restore is complete.
783 * Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
784 * do not need to save/restore it.
785 */
786 #define IWX_CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
787 #define IWX_CSR_UCODE_SW_BIT_RFKILL (0x00000002)
788 #define IWX_CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
789 #define IWX_CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
790 #define IWX_CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE (0x00000020)
791
792 /* GIO Chicken Bits (PCI Express bus link power management) */
793 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
794 #define IWX_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
795
796 /* HPET MEM debug */
797 #define IWX_CSR_DBG_HPET_MEM_REG_VAL (0xFFFF0000)
798
799 /* DRAM INT TABLE */
800 #define IWX_CSR_DRAM_INT_TBL_ENABLE (1U << 31)
801 #define IWX_CSR_DRAM_INIT_TBL_WRITE_POINTER (1 << 28)
802 #define IWX_CSR_DRAM_INIT_TBL_WRAP_CHECK (1 << 27)
803
804 /* 22000 configuration registers */
805
806 /*
807 * TFH Configuration register.
808 *
809 * BIT fields:
810 *
811 * Bits 3:0:
812 * Define the maximum number of pending read requests.
813 * Maximum configuration value allowed is 0xC
814 * Bits 9:8:
815 * Define the maximum transfer size. (64 / 128 / 256)
816 * Bit 10:
817 * When bit is set and transfer size is set to 128B, the TFH will enable
818 * reading chunks of more than 64B only if the read address is aligned to 128B.
819 * In case of DRAM read address which is not aligned to 128B, the TFH will
820 * enable transfer size which doesn't cross 64B DRAM address boundary.
821 */
822 #define IWX_TFH_TRANSFER_MODE (0x1F40)
823 #define IWX_TFH_TRANSFER_MAX_PENDING_REQ 0xc
824 #define IWX_TFH_CHUNK_SIZE_128 (1 << 8)
825 #define IWX_TFH_CHUNK_SPLIT_MODE (1 << 10)
826
827 /*
828 * Defines the offset address in dwords referring from the beginning of the
829 * Tx CMD which will be updated in DRAM.
830 * Note that the TFH offset address for Tx CMD update is always referring to
831 * the start of the TFD first TB.
832 * In case of a DRAM Tx CMD update the TFH will update PN and Key ID
833 */
834 #define IWX_TFH_TXCMD_UPDATE_CFG (0x1F48)
835
836 /*
837 * Controls TX DMA operation
838 *
839 * BIT fields:
840 *
841 * Bits 31:30: Enable the SRAM DMA channel.
842 * Turning on bit 31 will kick the SRAM2DRAM DMA.
843 * Note that the sram2dram may be enabled only after configuring the DRAM and
844 * SRAM addresses registers and the byte count register.
845 * Bits 25:24: Defines the interrupt target upon dram2sram transfer done. When
846 * set to 1 - interrupt is sent to the driver
847 * Bit 0: Indicates the snoop configuration
848 */
849 #define IWX_TFH_SRV_DMA_CHNL0_CTRL (0x1F60)
850 #define IWX_TFH_SRV_DMA_SNOOP (1 << 0)
851 #define IWX_TFH_SRV_DMA_TO_DRIVER (1 << 24)
852 #define IWX_TFH_SRV_DMA_START (1U << 31)
853
854 /* Defines the DMA SRAM write start address to transfer a data block */
855 #define IWX_TFH_SRV_DMA_CHNL0_SRAM_ADDR (0x1F64)
856
857 /* Defines the 64bits DRAM start address to read the DMA data block from */
858 #define IWX_TFH_SRV_DMA_CHNL0_DRAM_ADDR (0x1F68)
859
860 /*
861 * Defines the number of bytes to transfer from DRAM to SRAM.
862 * Note that this register may be configured with non-dword aligned size.
863 */
864 #define IWX_TFH_SRV_DMA_CHNL0_BC (0x1F70)
865
866 /* 9000 rx series registers */
867
868 #define IWX_RFH_Q0_FRBDCB_BA_LSB 0xA08000 /* 64 bit address */
869 #define IWX_RFH_Q_FRBDCB_BA_LSB(q) (IWX_RFH_Q0_FRBDCB_BA_LSB + (q) * 8)
870 /* Write index table */
871 #define IWX_RFH_Q0_FRBDCB_WIDX 0xA08080
872 #define IWX_RFH_Q_FRBDCB_WIDX(q) (IWX_RFH_Q0_FRBDCB_WIDX + (q) * 4)
873 /* Write index table - shadow registers */
874 #define IWX_RFH_Q0_FRBDCB_WIDX_TRG 0x1C80
875 #define IWX_RFH_Q_FRBDCB_WIDX_TRG(q) (IWX_RFH_Q0_FRBDCB_WIDX_TRG + (q) * 4)
876 /* Read index table */
877 #define IWX_RFH_Q0_FRBDCB_RIDX 0xA080C0
878 #define IWX_RFH_Q_FRBDCB_RIDX(q) (IWX_RFH_Q0_FRBDCB_RIDX + (q) * 4)
879 /* Used list table */
880 #define IWX_RFH_Q0_URBDCB_BA_LSB 0xA08100 /* 64 bit address */
881 #define IWX_RFH_Q_URBDCB_BA_LSB(q) (IWX_RFH_Q0_URBDCB_BA_LSB + (q) * 8)
882 /* Write index table */
883 #define IWX_RFH_Q0_URBDCB_WIDX 0xA08180
884 #define IWX_RFH_Q_URBDCB_WIDX(q) (IWX_RFH_Q0_URBDCB_WIDX + (q) * 4)
885 #define IWX_RFH_Q0_URBDCB_VAID 0xA081C0
886 #define IWX_RFH_Q_URBDCB_VAID(q) (IWX_RFH_Q0_URBDCB_VAID + (q) * 4)
887 /* stts */
888 #define IWX_RFH_Q0_URBD_STTS_WPTR_LSB 0xA08200 /*64 bits address */
889 #define IWX_RFH_Q_URBD_STTS_WPTR_LSB(q) (IWX_RFH_Q0_URBD_STTS_WPTR_LSB + (q) * 8)
890
891 #define IWX_RFH_Q0_ORB_WPTR_LSB 0xA08280
892 #define IWX_RFH_Q_ORB_WPTR_LSB(q) (IWX_RFH_Q0_ORB_WPTR_LSB + (q) * 8)
893 #define IWX_RFH_RBDBUF_RBD0_LSB 0xA08300
894 #define IWX_RFH_RBDBUF_RBD_LSB(q) (IWX_RFH_RBDBUF_RBD0_LSB + (q) * 8)
895
896 /**
897 * RFH Status Register
898 *
899 * Bit fields:
900 *
901 * Bit 29: RBD_FETCH_IDLE
902 * This status flag is set by the RFH when there is no active RBD fetch from
903 * DRAM.
904 * Once the RFH RBD controller starts fetching (or when there is a pending
905 * RBD read response from DRAM), this flag is immediately turned off.
906 *
907 * Bit 30: SRAM_DMA_IDLE
908 * This status flag is set by the RFH when there is no active transaction from
909 * SRAM to DRAM.
910 * Once the SRAM to DRAM DMA is active, this flag is immediately turned off.
911 *
912 * Bit 31: RXF_DMA_IDLE
913 * This status flag is set by the RFH when there is no active transaction from
914 * RXF to DRAM.
915 * Once the RXF-to-DRAM DMA is active, this flag is immediately turned off.
916 */
917 #define IWX_RFH_GEN_STATUS 0xA09808
918 #define IWX_RFH_GEN_STATUS_GEN3 0xA07824
919 #define IWX_RBD_FETCH_IDLE (1 << 29)
920 #define IWX_SRAM_DMA_IDLE (1 << 30)
921 #define IWX_RXF_DMA_IDLE (1U << 31)
922
923 /* DMA configuration */
924 #define IWX_RFH_RXF_DMA_CFG 0xA09820
925 #define IWX_RFH_RXF_DMA_CFG_GEN3 0xA07880
926 /* RB size */
927 #define IWX_RFH_RXF_DMA_RB_SIZE_MASK (0x000F0000) /* bits 16-19 */
928 #define IWX_RFH_RXF_DMA_RB_SIZE_POS 16
929 #define IWX_RFH_RXF_DMA_RB_SIZE_1K (0x1 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
930 #define IWX_RFH_RXF_DMA_RB_SIZE_2K (0x2 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
931 #define IWX_RFH_RXF_DMA_RB_SIZE_4K (0x4 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
932 #define IWX_RFH_RXF_DMA_RB_SIZE_8K (0x8 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
933 #define IWX_RFH_RXF_DMA_RB_SIZE_12K (0x9 << IWX_RFH_RXF_DMA_RB_SIZE_POS)
934 #define IWX_RFH_RXF_DMA_RB_SIZE_16K (0xA << IWX_RFH_RXF_DMA_RB_SIZE_POS)
935 #define IWX_RFH_RXF_DMA_RB_SIZE_20K (0xB << IWX_RFH_RXF_DMA_RB_SIZE_POS)
936 #define IWX_RFH_RXF_DMA_RB_SIZE_24K (0xC << IWX_RFH_RXF_DMA_RB_SIZE_POS)
937 #define IWX_RFH_RXF_DMA_RB_SIZE_28K (0xD << IWX_RFH_RXF_DMA_RB_SIZE_POS)
938 #define IWX_RFH_RXF_DMA_RB_SIZE_32K (0xE << IWX_RFH_RXF_DMA_RB_SIZE_POS)
939 /* RB Circular Buffer size:defines the table sizes in RBD units */
940 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_MASK (0x00F00000) /* bits 20-23 */
941 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_POS 20
942 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_8 (0x3 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
943 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_16 (0x4 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
944 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_32 (0x5 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
945 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_64 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
946 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_128 (0x7 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
947 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_256 (0x8 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
948 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
949 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
950 #define IWX_RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << IWX_RFH_RXF_DMA_RBDCB_SIZE_POS)
951 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
952 #define IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS 24
953 #define IWX_RFH_RXF_DMA_MIN_RB_4_8 (3 << IWX_RFH_RXF_DMA_MIN_RB_SIZE_POS)
954 #define IWX_RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
955 #define IWX_RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
956 #define IWX_RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
957 #define IWX_RFH_DMA_EN_ENABLE_VAL (1U << 31)
958
959 #define IWX_RFH_RXF_RXQ_ACTIVE 0xA0980C
960
961 #define IWX_RFH_GEN_CFG 0xA09800
962 #define IWX_RFH_GEN_CFG_SERVICE_DMA_SNOOP (1 << 0)
963 #define IWX_RFH_GEN_CFG_RFH_DMA_SNOOP (1 << 1)
964 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_128 0x00000010
965 #define IWX_RFH_GEN_CFG_RB_CHUNK_SIZE_64 0x00000000
966 /* the driver assumes everywhere that the default RXQ is 0 */
967 #define IWX_RFH_GEN_CFG_DEFAULT_RXQ_NUM 0xF00
968
969 /* end of 9000 rx series registers */
970
971 /*
972 * This register is written by driver and is read by uCode during boot flow.
973 * Note this address is cleared after MAC reset.
974 */
975 #define IWX_UREG_UCODE_LOAD_STATUS (0xa05c40)
976 #define IWX_UREG_CPU_INIT_RUN (0xa05c44)
977
978 /*
979 * HBUS (Host-side Bus)
980 *
981 * HBUS registers are mapped directly into PCI bus space, but are used
982 * to indirectly access device's internal memory or registers that
983 * may be powered-down.
984 *
985 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
986 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
987 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
988 * internal resources.
989 *
990 * Do not use iwl_write32()/iwl_read32() family to access these registers;
991 * these provide only simple PCI bus access, without waking up the MAC.
992 */
993 #define IWX_HBUS_BASE (0x400)
994
995 /*
996 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
997 * structures, error log, event log, verifying uCode load).
998 * First write to address register, then read from or write to data register
999 * to complete the job. Once the address register is set up, accesses to
1000 * data registers auto-increment the address by one dword.
1001 * Bit usage for address registers (read or write):
1002 * 0-31: memory address within device
1003 */
1004 #define IWX_HBUS_TARG_MEM_RADDR (IWX_HBUS_BASE+0x00c)
1005 #define IWX_HBUS_TARG_MEM_WADDR (IWX_HBUS_BASE+0x010)
1006 #define IWX_HBUS_TARG_MEM_WDAT (IWX_HBUS_BASE+0x018)
1007 #define IWX_HBUS_TARG_MEM_RDAT (IWX_HBUS_BASE+0x01c)
1008
1009 /*
1010 * Registers for accessing device's internal peripheral registers
1011 * (e.g. SCD, BSM, etc.). First write to address register,
1012 * then read from or write to data register to complete the job.
1013 * Bit usage for address registers (read or write):
1014 * 0-15: register address (offset) within device
1015 * 24-25: (# bytes - 1) to read or write (e.g. 3 for dword)
1016 */
1017 #define IWX_HBUS_TARG_PRPH_WADDR (IWX_HBUS_BASE+0x044)
1018 #define IWX_HBUS_TARG_PRPH_RADDR (IWX_HBUS_BASE+0x048)
1019 #define IWX_HBUS_TARG_PRPH_WDAT (IWX_HBUS_BASE+0x04c)
1020 #define IWX_HBUS_TARG_PRPH_RDAT (IWX_HBUS_BASE+0x050)
1021
1022 /* enable the ID buf for read */
1023 #define IWX_WFPM_PS_CTL_CLR 0xa0300c
1024 #define IWX_WFMP_MAC_ADDR_0 0xa03080
1025 #define IWX_WFMP_MAC_ADDR_1 0xa03084
1026 #define IWX_LMPM_PMG_EN 0xa01cec
1027 #define IWX_RADIO_REG_SYS_MANUAL_DFT_0 0xad4078
1028 #define IWX_RFIC_REG_RD 0xad0470
1029 #define IWX_WFPM_CTRL_REG 0xa03030
1030 #define IWX_WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK 0x08000000
1031 #define IWX_ENABLE_WFPM 0x80000000
1032
1033 #define IWX_AUX_MISC_MASTER1_EN 0xa20818
1034 #define IWX_AUX_MISC_MASTER1_EN_SBE_MSK 0x1
1035 #define IWX_AUX_MISC_MASTER1_SMPHR_STATUS 0xa20800
1036 #define IWX_RSA_ENABLE 0xa24b08
1037 #define IWX_PREG_AUX_BUS_WPROT_0 0xa04cc0
1038 #define IWX_PREG_PRPH_WPROT_9000 0xa04ce0
1039 #define IWX_PREG_PRPH_WPROT_22000 0xa04d00
1040 #define IWX_SB_CFG_OVERRIDE_ADDR 0xa26c78
1041 #define IWX_SB_CFG_OVERRIDE_ENABLE 0x8000
1042 #define IWX_SB_CFG_BASE_OVERRIDE 0xa20000
1043 #define IWX_SB_MODIFY_CFG_FLAG 0xa03088
1044 #define IWX_UMAG_SB_CPU_1_STATUS 0xa038c0
1045 #define IWX_UMAG_SB_CPU_2_STATUS 0xa038c4
1046
1047 #define IWX_UREG_CHICK 0xa05c00
1048 #define IWX_UREG_CHICK_MSI_ENABLE (1 << 24)
1049 #define IWX_UREG_CHICK_MSIX_ENABLE (1 << 25)
1050
1051 #define IWX_HPM_DEBUG 0xa03440
1052 #define IWX_PERSISTENCE_BIT (1 << 12)
1053 #define IWX_PREG_WFPM_ACCESS (1 << 12)
1054
1055 #define IWX_HPM_HIPM_GEN_CFG 0xa03458
1056 #define IWX_HPM_HIPM_GEN_CFG_CR_PG_EN (1 << 0)
1057 #define IWX_HPM_HIPM_GEN_CFG_CR_SLP_EN (1 << 1)
1058 #define IWX_HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE (1 << 10)
1059
1060 #define IWX_UREG_DOORBELL_TO_ISR6 0xa05c04
1061 #define IWX_UREG_DOORBELL_TO_ISR6_NMI_BIT (1 << 0)
1062 #define IWX_UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE ((1 << 0) | (1 << 1))
1063 #define IWX_UREG_DOORBELL_TO_ISR6_SUSPEND (1 << 18)
1064 #define IWX_UREG_DOORBELL_TO_ISR6_RESUME (1 << 19)
1065 #define IWX_UREG_DOORBELL_TO_ISR6_PNVM (1 << 20)
1066
1067 /* LTR control (Qu only) */
1068 #define IWX_HPM_MAC_LTR_CSR 0xa0348c
1069 #define IWX_HPM_MAC_LRT_ENABLE_ALL 0xf
1070 /* also uses CSR_LTR_* for values */
1071 #define IWX_HPM_UMAC_LTR 0xa03480
1072
1073 /*
1074 * Per-Tx-queue write pointer (index, really!)
1075 * Indicates index to next TFD that driver will fill (1 past latest filled).
1076 * Bit usage:
1077 * 0-7: queue write index
1078 * 11-8: queue selector
1079 */
1080 #define IWX_HBUS_TARG_WRPTR (IWX_HBUS_BASE+0x060)
1081
1082 /**********************************************************
1083 * CSR values
1084 **********************************************************/
1085 /*
1086 * host interrupt timeout value
1087 * used with setting interrupt coalescing timer
1088 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
1089 *
1090 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
1091 */
1092 #define IWX_HOST_INT_TIMEOUT_MAX (0xFF)
1093 #define IWX_HOST_INT_TIMEOUT_DEF (0x40)
1094 #define IWX_HOST_INT_TIMEOUT_MIN (0x0)
1095 #define IWX_HOST_INT_OPER_MODE (1U << 31)
1096
1097 /*****************************************************************************
1098 * MSIX related registers *
1099 *****************************************************************************/
1100
1101 #define IWX_CSR_MSIX_BASE (0x2000)
1102 #define IWX_CSR_MSIX_FH_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x800)
1103 #define IWX_CSR_MSIX_FH_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x804)
1104 #define IWX_CSR_MSIX_HW_INT_CAUSES_AD (IWX_CSR_MSIX_BASE + 0x808)
1105 #define IWX_CSR_MSIX_HW_INT_MASK_AD (IWX_CSR_MSIX_BASE + 0x80C)
1106 #define IWX_CSR_MSIX_AUTOMASK_ST_AD (IWX_CSR_MSIX_BASE + 0x810)
1107 #define IWX_CSR_MSIX_RX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x880)
1108 #define IWX_CSR_MSIX_IVAR_AD_REG (IWX_CSR_MSIX_BASE + 0x890)
1109 #define IWX_CSR_MSIX_PENDING_PBA_AD (IWX_CSR_MSIX_BASE + 0x1000)
1110 #define IWX_CSR_MSIX_RX_IVAR(cause) (IWX_CSR_MSIX_RX_IVAR_AD_REG + (cause))
1111 #define IWX_CSR_MSIX_IVAR(cause) (IWX_CSR_MSIX_IVAR_AD_REG + (cause))
1112
1113 /*
1114 * Causes for the FH register interrupts
1115 */
1116 enum msix_fh_int_causes {
1117 IWX_MSIX_FH_INT_CAUSES_Q0 = (1 << 0),
1118 IWX_MSIX_FH_INT_CAUSES_Q1 = (1 << 1),
1119 IWX_MSIX_FH_INT_CAUSES_D2S_CH0_NUM = (1 << 16),
1120 IWX_MSIX_FH_INT_CAUSES_D2S_CH1_NUM = (1 << 17),
1121 IWX_MSIX_FH_INT_CAUSES_S2D = (1 << 19),
1122 IWX_MSIX_FH_INT_CAUSES_FH_ERR = (1 << 21),
1123 };
1124
1125 /*
1126 * Causes for the HW register interrupts
1127 */
1128 enum mix_hw_int_causes {
1129 IWX_MSIX_HW_INT_CAUSES_REG_ALIVE = (1 << 0),
1130 IWX_MSIX_HW_INT_CAUSES_REG_WAKEUP = (1 << 1),
1131 IWX_MSIX_HW_INT_CAUSES_REG_RESET_DONE = (1 << 2),
1132 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR_V2 = (1 << 5),
1133 IWX_MSIX_HW_INT_CAUSES_REG_CT_KILL = (1 << 6),
1134 IWX_MSIX_HW_INT_CAUSES_REG_RF_KILL = (1 << 7),
1135 IWX_MSIX_HW_INT_CAUSES_REG_PERIODIC = (1 << 8),
1136 IWX_MSIX_HW_INT_CAUSES_REG_SW_ERR = (1 << 25),
1137 IWX_MSIX_HW_INT_CAUSES_REG_SCD = (1 << 26),
1138 IWX_MSIX_HW_INT_CAUSES_REG_FH_TX = (1 << 27),
1139 IWX_MSIX_HW_INT_CAUSES_REG_HW_ERR = (1 << 29),
1140 IWX_MSIX_HW_INT_CAUSES_REG_HAP = (1 << 30),
1141 };
1142
1143 /*
1144 * Registers to map causes to vectors
1145 */
1146 enum msix_ivar_for_cause {
1147 IWX_MSIX_IVAR_CAUSE_D2S_CH0_NUM = 0x0,
1148 IWX_MSIX_IVAR_CAUSE_D2S_CH1_NUM = 0x1,
1149 IWX_MSIX_IVAR_CAUSE_S2D = 0x3,
1150 IWX_MSIX_IVAR_CAUSE_FH_ERR = 0x5,
1151 IWX_MSIX_IVAR_CAUSE_REG_ALIVE = 0x10,
1152 IWX_MSIX_IVAR_CAUSE_REG_WAKEUP = 0x11,
1153 IWX_MSIX_IVAR_CAUSE_REG_RESET_DONE = 0x12,
1154 IWX_MSIX_IVAR_CAUSE_REG_CT_KILL = 0x16,
1155 IWX_MSIX_IVAR_CAUSE_REG_RF_KILL = 0x17,
1156 IWX_MSIX_IVAR_CAUSE_REG_PERIODIC = 0x18,
1157 IWX_MSIX_IVAR_CAUSE_REG_SW_ERR = 0x29,
1158 IWX_MSIX_IVAR_CAUSE_REG_SCD = 0x2a,
1159 IWX_MSIX_IVAR_CAUSE_REG_FH_TX = 0x2b,
1160 IWX_MSIX_IVAR_CAUSE_REG_HW_ERR = 0x2d,
1161 IWX_MSIX_IVAR_CAUSE_REG_HAP = 0x2e,
1162 };
1163
1164 #define IWX_MSIX_AUTO_CLEAR_CAUSE (0 << 7)
1165 #define IWX_MSIX_NON_AUTO_CLEAR_CAUSE (1 << 7)
1166
1167 #define IWX_CSR_ADDR_BASE(sc) ((sc)->mac_addr_from_csr)
1168 #define IWX_CSR_MAC_ADDR0_OTP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x00)
1169 #define IWX_CSR_MAC_ADDR1_OTP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x04)
1170 #define IWX_CSR_MAC_ADDR0_STRAP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x08)
1171 #define IWX_CSR_MAC_ADDR1_STRAP(sc) (IWX_CSR_ADDR_BASE(sc) + 0x0c)
1172
1173 /**
1174 * uCode API flags
1175 * @IWX_UCODE_TLV_FLAGS_PAN: This is PAN capable microcode; this previously
1176 * was a separate TLV but moved here to save space.
1177 * @IWX_UCODE_TLV_FLAGS_NEWSCAN: new uCode scan behaviour on hidden SSID,
1178 * treats good CRC threshold as a boolean
1179 * @IWX_UCODE_TLV_FLAGS_MFP: This uCode image supports MFP (802.11w).
1180 * @IWX_UCODE_TLV_FLAGS_P2P: This uCode image supports P2P.
1181 * @IWX_UCODE_TLV_FLAGS_DW_BC_TABLE: The SCD byte count table is in DWORDS
1182 * @IWX_UCODE_TLV_FLAGS_UAPSD: This uCode image supports uAPSD
1183 * @IWX_UCODE_TLV_FLAGS_SHORT_BL: 16 entries of black list instead of 64 in scan
1184 * offload profile config command.
1185 * @IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS: D3 image supports up to six
1186 * (rather than two) IPv6 addresses
1187 * @IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID: not sending a probe with the SSID element
1188 * from the probe request template.
1189 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL: new NS offload (small version)
1190 * @IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE: new NS offload (large version)
1191 * @IWX_UCODE_TLV_FLAGS_P2P_PS: P2P client power save is supported (only on a
1192 * single bound interface).
1193 * @IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT: General support for uAPSD
1194 * @IWX_UCODE_TLV_FLAGS_EBS_SUPPORT: this uCode image supports EBS.
1195 * @IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD: P2P client supports uAPSD power save
1196 * @IWX_UCODE_TLV_FLAGS_BCAST_FILTERING: uCode supports broadcast filtering.
1197 * @IWX_UCODE_TLV_FLAGS_GO_UAPSD: AP/GO interfaces support uAPSD clients
1198 *
1199 */
1200 #define IWX_UCODE_TLV_FLAGS_PAN (1 << 0)
1201 #define IWX_UCODE_TLV_FLAGS_NEWSCAN (1 << 1)
1202 #define IWX_UCODE_TLV_FLAGS_MFP (1 << 2)
1203 #define IWX_UCODE_TLV_FLAGS_P2P (1 << 3)
1204 #define IWX_UCODE_TLV_FLAGS_DW_BC_TABLE (1 << 4)
1205 #define IWX_UCODE_TLV_FLAGS_SHORT_BL (1 << 7)
1206 #define IWX_UCODE_TLV_FLAGS_D3_6_IPV6_ADDRS (1 << 10)
1207 #define IWX_UCODE_TLV_FLAGS_NO_BASIC_SSID (1 << 12)
1208 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_SMALL (1 << 15)
1209 #define IWX_UCODE_TLV_FLAGS_NEW_NSOFFL_LARGE (1 << 16)
1210 #define IWX_UCODE_TLV_FLAGS_P2P_PS (1 << 21)
1211 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_DCM (1 << 22)
1212 #define IWX_UCODE_TLV_FLAGS_BSS_P2P_PS_SCM (1 << 23)
1213 #define IWX_UCODE_TLV_FLAGS_UAPSD_SUPPORT (1 << 24)
1214 #define IWX_UCODE_TLV_FLAGS_EBS_SUPPORT (1 << 25)
1215 #define IWX_UCODE_TLV_FLAGS_P2P_PS_UAPSD (1 << 26)
1216 #define IWX_UCODE_TLV_FLAGS_BCAST_FILTERING (1 << 29)
1217 #define IWX_UCODE_TLV_FLAGS_GO_UAPSD (1 << 30)
1218 #define IWX_UCODE_TLV_FLAGS_LTE_COEX (1U << 31)
1219
1220 #define IWX_UCODE_TLV_FLAG_BITS \
1221 "\020\1PAN\2NEWSCAN\3MFP\4P2P\5DW_BC_TABLE\6NEWBT_COEX\7PM_CMD\10SHORT_BL\11RX_ENERGY\12TIME_EVENT_V2\13D3_6_IPV6\14BF_UPDATED\15NO_BASIC_SSID\17D3_CONTINUITY\20NEW_NSOFFL_S\21NEW_NSOFFL_L\22SCHED_SCAN\24STA_KEY_CMD\25DEVICE_PS_CMD\26P2P_PS\27P2P_PS_DCM\30P2P_PS_SCM\31UAPSD_SUPPORT\32EBS\33P2P_PS_UAPSD\36BCAST_FILTERING\37GO_UAPSD\40LTE_COEX"
1222
1223 /**
1224 * uCode TLV api
1225 * @IWX_UCODE_TLV_API_FRAGMENTED_SCAN: This ucode supports active dwell time
1226 * longer than the passive one, which is essential for fragmented scan.
1227 * @IWX_UCODE_TLV_API_WIFI_MCC_UPDATE: ucode supports MCC updates with source.
1228 * @IWX_UCODE_TLV_API_WIDE_CMD_HDR: ucode supports wide command header
1229 * @IWX_UCODE_TLV_API_LQ_SS_PARAMS: Configure STBC/BFER via LQ CMD ss_params
1230 * @IWX_UCODE_TLV_API_NEW_VERSION: new versioning format
1231 * @IWX_UCODE_TLV_API_TX_POWER_CHAIN: TX power API has larger command size
1232 * (command version 3) that supports per-chain limits
1233 * @IWX_UCODE_TLV_API_SCAN_TSF_REPORT: Scan start time reported in scan
1234 * iteration complete notification, and the timestamp reported for RX
1235 * received during scan, are reported in TSF of the mac specified in the
1236 * scan request.
1237 * @IWX_UCODE_TLV_API_TKIP_MIC_KEYS: This ucode supports version 2 of
1238 * ADD_MODIFY_STA_KEY_API_S_VER_2.
1239 * @IWX_UCODE_TLV_API_STA_TYPE: This ucode supports station type assignment.
1240 * @IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY: scan APIs use 8-level priority
1241 * instead of 3.
1242 * @IWX_UCODE_TLV_API_NEW_RX_STATS: should new RX STATISTICS API be used
1243 * @IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG: This ucode supports v3 of
1244 * SCAN_CONFIG_DB_CMD_API_S.
1245 *
1246 * @IWX_NUM_UCODE_TLV_API: number of bits used
1247 */
1248 #define IWX_UCODE_TLV_API_FRAGMENTED_SCAN 8
1249 #define IWX_UCODE_TLV_API_WIFI_MCC_UPDATE 9
1250 #define IWX_UCODE_TLV_API_WIDE_CMD_HDR 14
1251 #define IWX_UCODE_TLV_API_LQ_SS_PARAMS 18
1252 #define IWX_UCODE_TLV_API_NEW_VERSION 20
1253 #define IWX_UCODE_TLV_API_EXT_SCAN_PRIORITY 24
1254 #define IWX_UCODE_TLV_API_TX_POWER_CHAIN 27
1255 #define IWX_UCODE_TLV_API_SCAN_TSF_REPORT 28
1256 #define IWX_UCODE_TLV_API_TKIP_MIC_KEYS 29
1257 #define IWX_UCODE_TLV_API_STA_TYPE 30
1258 #define IWX_UCODE_TLV_API_NAN2_VER2 31
1259 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL 32
1260 #define IWX_UCODE_TLV_API_NEW_RX_STATS 35
1261 #define IWX_UCODE_TLV_API_WOWLAN_KEY_MATERIAL 36
1262 #define IWX_UCODE_TLV_API_QUOTA_LOW_LATENCY 38
1263 #define IWX_UCODE_TLV_API_DEPRECATE_TTAK 41
1264 #define IWX_UCODE_TLV_API_ADAPTIVE_DWELL_V2 42
1265 #define IWX_UCODE_TLV_API_NAN_NOTIF_V2 43
1266 #define IWX_UCODE_TLV_API_FRAG_EBS 44
1267 #define IWX_UCODE_TLV_API_REDUCE_TX_POWER 45
1268 #define IWX_UCODE_TLV_API_SHORT_BEACON_NOTIF 46
1269 #define IWX_UCODE_TLV_API_BEACON_FILTER_V4 47
1270 #define IWX_UCODE_TLV_API_REGULATORY_NVM_INFO 48
1271 #define IWX_UCODE_TLV_API_FTM_NEW_RANGE_REQ 49
1272 #define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56
1273 #define IWX_UCODE_TLV_API_SCAN_OFFLOAD_CHANS 50
1274 #define IWX_UCODE_TLV_API_MBSSID_HE 52
1275 #define IWX_UCODE_TLV_API_WOWLAN_TCP_SYN_WAKE 53
1276 #define IWX_UCODE_TLV_API_FTM_RTT_ACCURACY 54
1277 #define IWX_UCODE_TLV_API_SAR_TABLE_VER 55
1278 #define IWX_UCODE_TLV_API_REDUCED_SCAN_CONFIG 56
1279 #define IWX_UCODE_TLV_API_ADWELL_HB_DEF_N_AP 57
1280 #define IWX_UCODE_TLV_API_SCAN_EXT_CHAN_VER 58
1281 #define IWX_UCODE_TLV_API_BAND_IN_RX_DATA 59
1282 #define IWX_NUM_UCODE_TLV_API 128
1283
1284 #define IWX_UCODE_TLV_API_BITS \
1285 "\020\10FRAGMENTED_SCAN\11WIFI_MCC_UPDATE\16WIDE_CMD_HDR\22LQ_SS_PARAMS\30EXT_SCAN_PRIO\33TX_POWER_CHAIN\35TKIP_MIC_KEYS"
1286
1287 /**
1288 * uCode capabilities
1289 * @IWX_UCODE_TLV_CAPA_D0I3_SUPPORT: supports D0i3
1290 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT: supports Location Aware Regulatory
1291 * @IWX_UCODE_TLV_CAPA_UMAC_SCAN: supports UMAC scan.
1292 * @IWX_UCODE_TLV_CAPA_BEAMFORMER: supports Beamformer
1293 * @IWX_UCODE_TLV_CAPA_TOF_SUPPORT: supports Time of Flight (802.11mc FTM)
1294 * @IWX_UCODE_TLV_CAPA_TDLS_SUPPORT: support basic TDLS functionality
1295 * @IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT: supports insertion of current
1296 * tx power value into TPC Report action frame and Link Measurement Report
1297 * action frame
1298 * @IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT: supports updating current
1299 * channel in DS parameter set element in probe requests.
1300 * @IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT: supports adding TPC Report IE in
1301 * probe requests.
1302 * @IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT: supports Quiet Period requests
1303 * @IWX_UCODE_TLV_CAPA_DQA_SUPPORT: supports dynamic queue allocation (DQA),
1304 * which also implies support for the scheduler configuration command
1305 * @IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH: supports TDLS channel switching
1306 * @IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG: Consolidated D3-D0 image
1307 * @IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT: supports Hot Spot Command
1308 * @IWX_UCODE_TLV_CAPA_DC2DC_SUPPORT: supports DC2DC Command
1309 * @IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT: supports 2G coex Command
1310 * @IWX_UCODE_TLV_CAPA_CSUM_SUPPORT: supports TCP Checksum Offload
1311 * @IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS: support radio and beacon statistics
1312 * @IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD: support p2p standalone U-APSD
1313 * @IWX_UCODE_TLV_CAPA_BT_COEX_PLCR: enabled BT Coex packet level co-running
1314 * @IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC: ucode supports LAR updates with different
1315 * sources for the MCC. This TLV bit is a future replacement to
1316 * IWX_UCODE_TLV_API_WIFI_MCC_UPDATE. When either is set, multi-source LAR
1317 * is supported.
1318 * @IWX_UCODE_TLV_CAPA_BT_COEX_RRC: supports BT Coex RRC
1319 * @IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT: supports gscan
1320 * @IWX_UCODE_TLV_CAPA_NAN_SUPPORT: supports NAN
1321 * @IWX_UCODE_TLV_CAPA_UMAC_UPLOAD: supports upload mode in umac (1=supported,
1322 * 0=no support)
1323 * @IWx_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS: firmware supports ultra high band
1324 * (6 GHz).
1325 * @IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE: extended DTS measurement
1326 * @IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS: supports short PM timeouts
1327 * @IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT: supports bt-coex Multi-priority LUT
1328 * @IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION: firmware will decide on what
1329 * antenna the beacon should be transmitted
1330 * @IWX_UCODE_TLV_CAPA_BEACON_STORING: firmware will store the latest beacon
1331 * from AP and will send it upon d0i3 exit.
1332 * @IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V2: support LAR API V2
1333 * @IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW: firmware responsible for CT-kill
1334 * @IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT: supports temperature
1335 * thresholds reporting
1336 * @IWX_UCODE_TLV_CAPA_CTDP_SUPPORT: supports cTDP command
1337 * @IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED: supports usniffer enabled in
1338 * regular image.
1339 * @IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG: support getting more shared
1340 * memory addresses from the firmware.
1341 * @IWX_UCODE_TLV_CAPA_LQM_SUPPORT: supports Link Quality Measurement
1342 * @IWX_UCODE_TLV_CAPA_LMAC_UPLOAD: supports upload mode in lmac (1=supported,
1343 * 0=no support)
1344 *
1345 * @IWX_NUM_UCODE_TLV_CAPA: number of bits used
1346 */
1347 #define IWX_UCODE_TLV_CAPA_D0I3_SUPPORT 0
1348 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT 1
1349 #define IWX_UCODE_TLV_CAPA_UMAC_SCAN 2
1350 #define IWX_UCODE_TLV_CAPA_BEAMFORMER 3
1351 #define IWX_UCODE_TLV_CAPA_TOF_SUPPORT 5
1352 #define IWX_UCODE_TLV_CAPA_TDLS_SUPPORT 6
1353 #define IWX_UCODE_TLV_CAPA_TXPOWER_INSERTION_SUPPORT 8
1354 #define IWX_UCODE_TLV_CAPA_DS_PARAM_SET_IE_SUPPORT 9
1355 #define IWX_UCODE_TLV_CAPA_WFA_TPC_REP_IE_SUPPORT 10
1356 #define IWX_UCODE_TLV_CAPA_QUIET_PERIOD_SUPPORT 11
1357 #define IWX_UCODE_TLV_CAPA_DQA_SUPPORT 12
1358 #define IWX_UCODE_TLV_CAPA_TDLS_CHANNEL_SWITCH 13
1359 #define IWX_UCODE_TLV_CAPA_CNSLDTD_D3_D0_IMG 17
1360 #define IWX_UCODE_TLV_CAPA_HOTSPOT_SUPPORT 18
1361 #define IWX_UCODE_TLV_CAPA_DC2DC_CONFIG_SUPPORT 19
1362 #define IWX_UCODE_TLV_CAPA_2G_COEX_SUPPORT 20
1363 #define IWX_UCODE_TLV_CAPA_CSUM_SUPPORT 21
1364 #define IWX_UCODE_TLV_CAPA_RADIO_BEACON_STATS 22
1365 #define IWX_UCODE_TLV_CAPA_P2P_STANDALONE_UAPSD 26
1366 #define IWX_UCODE_TLV_CAPA_BT_COEX_PLCR 28
1367 #define IWX_UCODE_TLV_CAPA_LAR_MULTI_MCC 29
1368 #define IWX_UCODE_TLV_CAPA_BT_COEX_RRC 30
1369 #define IWX_UCODE_TLV_CAPA_GSCAN_SUPPORT 31
1370 #define IWX_UCODE_TLV_CAPA_NAN_SUPPORT 34
1371 #define IWX_UCODE_TLV_CAPA_UMAC_UPLOAD 35
1372 #define IWM_UCODE_TLV_CAPA_SOC_LATENCY_SUPPORT 37
1373 #define IWX_UCODE_TLV_CAPA_STA_PM_NOTIF 38
1374 #define IWX_UCODE_TLV_CAPA_BINDING_CDB_SUPPORT 39
1375 #define IWX_UCODE_TLV_CAPA_CDB_SUPPORT 40
1376 #define IWX_UCODE_TLV_CAPA_D0I3_END_FIRST 41
1377 #define IWX_UCODE_TLV_CAPA_TLC_OFFLOAD 43
1378 #define IWX_UCODE_TLV_CAPA_DYNAMIC_QUOTA 44
1379 #define IWX_UCODE_TLV_CAPA_COEX_SCHEMA_2 45
1380 #define IWX_UCODE_TLV_CAPA_CHANNEL_SWITCH_CMD 46
1381 #define IWX_UCODE_TLV_CAPA_FTM_CALIBRATED 47
1382 #define IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS 48
1383 #define IWX_UCODE_TLV_CAPA_CS_MODIFY 49
1384 #define IWX_UCODE_TLV_CAPA_SET_LTR_GEN2 50
1385 #define IWX_UCODE_TLV_CAPA_SET_PPAG 52
1386 #define IWX_UCODE_TLV_CAPA_TAS_CFG 53
1387 #define IWX_UCODE_TLV_CAPA_SESSION_PROT_CMD 54
1388 #define IWX_UCODE_TLV_CAPA_PROTECTED_TWT 56
1389 #define IWX_UCODE_TLV_CAPA_FW_RESET_HANDSHAKE 57
1390 #define IWX_UCODE_TLV_CAPA_PASSIVE_6GHZ_SCAN 58
1391 #define IWX_UCODE_TLV_CAPA_PROTECTED_TWT 56
1392 #define IWX_UCODE_TLV_CAPA_FW_RESET_HANDSHAKE 57
1393 #define IWX_UCODE_TLV_CAPA_PASSIVE_6GHZ_SCAN 58
1394 #define IWX_UCODE_TLV_CAPA_BAID_ML_SUPPORT 63
1395 #define IWX_UCODE_TLV_CAPA_EXTENDED_DTS_MEASURE 64
1396 #define IWX_UCODE_TLV_CAPA_SHORT_PM_TIMEOUTS 65
1397 #define IWX_UCODE_TLV_CAPA_BT_MPLUT_SUPPORT 67
1398 #define IWX_UCODE_TLV_CAPA_MULTI_QUEUE_RX_SUPPORT 68
1399 #define IWX_UCODE_TLV_CAPA_CSA_AND_TBTT_OFFLOAD 70
1400 #define IWX_UCODE_TLV_CAPA_BEACON_ANT_SELECTION 71
1401 #define IWX_UCODE_TLV_CAPA_BEACON_STORING 72
1402 #define IWX_UCODE_TLV_CAPA_LAR_SUPPORT_V3 73
1403 #define IWX_UCODE_TLV_CAPA_CT_KILL_BY_FW 74
1404 #define IWX_UCODE_TLV_CAPA_TEMP_THS_REPORT_SUPPORT 75
1405 #define IWX_UCODE_TLV_CAPA_CTDP_SUPPORT 76
1406 #define IWX_UCODE_TLV_CAPA_USNIFFER_UNIFIED 77
1407 #define IWX_UCODE_TLV_CAPA_LMAC_UPLOAD 79
1408 #define IWX_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 80
1409 #define IWX_UCODE_TLV_CAPA_LQM_SUPPORT 81
1410 #define IWX_UCODE_TLV_CAPA_TX_POWER_ACK 84
1411 #define IWX_UCODE_TLV_CAPA_D3_DEBUG 87
1412 #define IWX_UCODE_TLV_CAPA_LED_CMD_SUPPORT 88
1413 #define IWX_UCODE_TLV_CAPA_MCC_UPDATE_11AX_SUPPORT 89
1414 #define IWX_UCODE_TLV_CAPA_CSI_REPORTING 90
1415 #define IWX_UCODE_TLV_CAPA_CSI_REPORTING_V2 91
1416 #define IWX_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP 92
1417 #define IWX_UCODE_TLV_CAPA_DBG_BUF_ALLOC_CMD_SUPP 93
1418 #define IWX_UCODE_TLV_CAPA_MLME_OFFLOAD 96
1419 #define IWX_UCODE_TLV_CAPA_BIGTK_SUPPORT 100
1420 #define IWX_UCODE_TLV_CAPA_RFIM_SUPPORT 102
1421
1422 #define IWX_NUM_UCODE_TLV_CAPA 128
1423
1424 /*
1425 * For 16.0 uCode and above, there is no differentiation between sections,
1426 * just an offset to the HW address.
1427 */
1428 #define IWX_CPU1_CPU2_SEPARATOR_SECTION 0xFFFFCCCC
1429 #define IWX_PAGING_SEPARATOR_SECTION 0xAAAABBBB
1430
1431 /* uCode version contains 4 values: Major/Minor/API/Serial */
1432 #define IWX_UCODE_MAJOR(ver) (((ver) & 0xFF000000) >> 24)
1433 #define IWX_UCODE_MINOR(ver) (((ver) & 0x00FF0000) >> 16)
1434 #define IWX_UCODE_API(ver) (((ver) & 0x0000FF00) >> 8)
1435 #define IWX_UCODE_SERIAL(ver) ((ver) & 0x000000FF)
1436
1437 /*
1438 * Calibration control struct.
1439 * Sent as part of the phy configuration command.
1440 * @flow_trigger: bitmap for which calibrations to perform according to
1441 * flow triggers.
1442 * @event_trigger: bitmap for which calibrations to perform according to
1443 * event triggers.
1444 */
1445 struct iwx_tlv_calib_ctrl {
1446 uint32_t flow_trigger;
1447 uint32_t event_trigger;
1448 } __packed;
1449
1450 #define IWX_FW_PHY_CFG_RADIO_TYPE_POS 0
1451 #define IWX_FW_PHY_CFG_RADIO_TYPE (0x3 << IWX_FW_PHY_CFG_RADIO_TYPE_POS)
1452 #define IWX_FW_PHY_CFG_RADIO_STEP_POS 2
1453 #define IWX_FW_PHY_CFG_RADIO_STEP (0x3 << IWX_FW_PHY_CFG_RADIO_STEP_POS)
1454 #define IWX_FW_PHY_CFG_RADIO_DASH_POS 4
1455 #define IWX_FW_PHY_CFG_RADIO_DASH (0x3 << IWX_FW_PHY_CFG_RADIO_DASH_POS)
1456 #define IWX_FW_PHY_CFG_TX_CHAIN_POS 16
1457 #define IWX_FW_PHY_CFG_TX_CHAIN (0xf << IWX_FW_PHY_CFG_TX_CHAIN_POS)
1458 #define IWX_FW_PHY_CFG_RX_CHAIN_POS 20
1459 #define IWX_FW_PHY_CFG_RX_CHAIN (0xf << IWX_FW_PHY_CFG_RX_CHAIN_POS)
1460
1461 /**
1462 * struct iwx_fw_cipher_scheme - a cipher scheme supported by FW.
1463 * @cipher: a cipher suite selector
1464 * @flags: cipher scheme flags (currently reserved for a future use)
1465 * @hdr_len: a size of MPDU security header
1466 * @pn_len: a size of PN
1467 * @pn_off: an offset of pn from the beginning of the security header
1468 * @key_idx_off: an offset of key index byte in the security header
1469 * @key_idx_mask: a bit mask of key_idx bits
1470 * @key_idx_shift: bit shift needed to get key_idx
1471 * @mic_len: mic length in bytes
1472 * @hw_cipher: a HW cipher index used in host commands
1473 */
1474 struct iwx_fw_cipher_scheme {
1475 uint32_t cipher;
1476 uint8_t flags;
1477 uint8_t hdr_len;
1478 uint8_t pn_len;
1479 uint8_t pn_off;
1480 uint8_t key_idx_off;
1481 uint8_t key_idx_mask;
1482 uint8_t key_idx_shift;
1483 uint8_t mic_len;
1484 uint8_t hw_cipher;
1485 } __packed;
1486
1487 /**
1488 * struct iwx_fw_cscheme_list - a cipher scheme list
1489 * @size: a number of entries
1490 * @cs: cipher scheme entries
1491 */
1492 struct iwx_fw_cscheme_list {
1493 uint8_t size;
1494 struct iwx_fw_cipher_scheme cs[];
1495 } __packed;
1496
1497 /* v1/v2 uCode file layout */
1498 struct iwx_ucode_header {
1499 uint32_t ver; /* major/minor/API/serial */
1500 union {
1501 struct {
1502 uint32_t inst_size; /* bytes of runtime code */
1503 uint32_t data_size; /* bytes of runtime data */
1504 uint32_t init_size; /* bytes of init code */
1505 uint32_t init_data_size; /* bytes of init data */
1506 uint32_t boot_size; /* bytes of bootstrap code */
1507 uint8_t data[0]; /* in same order as sizes */
1508 } v1;
1509 struct {
1510 uint32_t build; /* build number */
1511 uint32_t inst_size; /* bytes of runtime code */
1512 uint32_t data_size; /* bytes of runtime data */
1513 uint32_t init_size; /* bytes of init code */
1514 uint32_t init_data_size; /* bytes of init data */
1515 uint32_t boot_size; /* bytes of bootstrap code */
1516 uint8_t data[0]; /* in same order as sizes */
1517 } v2;
1518 } u;
1519 };
1520
1521 /*
1522 * new TLV uCode file layout
1523 *
1524 * The new TLV file format contains TLVs, that each specify
1525 * some piece of data.
1526 */
1527
1528 #define IWX_UCODE_TLV_INVALID 0 /* unused */
1529 #define IWX_UCODE_TLV_INST 1
1530 #define IWX_UCODE_TLV_DATA 2
1531 #define IWX_UCODE_TLV_INIT 3
1532 #define IWX_UCODE_TLV_INIT_DATA 4
1533 #define IWX_UCODE_TLV_BOOT 5
1534 #define IWX_UCODE_TLV_PROBE_MAX_LEN 6 /* a uint32_t value */
1535 #define IWX_UCODE_TLV_PAN 7
1536 #define IWX_UCODE_TLV_RUNT_EVTLOG_PTR 8
1537 #define IWX_UCODE_TLV_RUNT_EVTLOG_SIZE 9
1538 #define IWX_UCODE_TLV_RUNT_ERRLOG_PTR 10
1539 #define IWX_UCODE_TLV_INIT_EVTLOG_PTR 11
1540 #define IWX_UCODE_TLV_INIT_EVTLOG_SIZE 12
1541 #define IWX_UCODE_TLV_INIT_ERRLOG_PTR 13
1542 #define IWX_UCODE_TLV_ENHANCE_SENS_TBL 14
1543 #define IWX_UCODE_TLV_PHY_CALIBRATION_SIZE 15
1544 #define IWX_UCODE_TLV_WOWLAN_INST 16
1545 #define IWX_UCODE_TLV_WOWLAN_DATA 17
1546 #define IWX_UCODE_TLV_FLAGS 18
1547 #define IWX_UCODE_TLV_SEC_RT 19
1548 #define IWX_UCODE_TLV_SEC_INIT 20
1549 #define IWX_UCODE_TLV_SEC_WOWLAN 21
1550 #define IWX_UCODE_TLV_DEF_CALIB 22
1551 #define IWX_UCODE_TLV_PHY_SKU 23
1552 #define IWX_UCODE_TLV_SECURE_SEC_RT 24
1553 #define IWX_UCODE_TLV_SECURE_SEC_INIT 25
1554 #define IWX_UCODE_TLV_SECURE_SEC_WOWLAN 26
1555 #define IWX_UCODE_TLV_NUM_OF_CPU 27
1556 #define IWX_UCODE_TLV_CSCHEME 28
1557 #define IWX_UCODE_TLV_API_CHANGES_SET 29
1558 #define IWX_UCODE_TLV_ENABLED_CAPABILITIES 30
1559 #define IWX_UCODE_TLV_N_SCAN_CHANNELS 31
1560 #define IWX_UCODE_TLV_PAGING 32
1561 #define IWX_UCODE_TLV_SEC_RT_USNIFFER 34
1562 #define IWX_UCODE_TLV_SDIO_ADMA_ADDR 35
1563 #define IWX_UCODE_TLV_FW_VERSION 36
1564 #define IWX_UCODE_TLV_FW_DBG_DEST 38
1565 #define IWX_UCODE_TLV_FW_DBG_CONF 39
1566 #define IWX_UCODE_TLV_FW_DBG_TRIGGER 40
1567 #define IWX_UCODE_TLV_CMD_VERSIONS 48
1568 #define IWX_UCODE_TLV_FW_GSCAN_CAPA 50
1569 #define IWX_UCODE_TLV_FW_MEM_SEG 51
1570 #define IWX_UCODE_TLV_IML 52
1571 #define IWX_UCODE_TLV_FW_FMAC_API_VERSION 53
1572 #define IWX_UCODE_TLV_UMAC_DEBUG_ADDRS 54
1573 #define IWX_UCODE_TLV_LMAC_DEBUG_ADDRS 55
1574 #define IWX_UCODE_TLV_FW_RECOVERY_INFO 57
1575 #define IWX_UCODE_TLV_HW_TYPE 58
1576 #define IWX_UCODE_TLV_FW_FMAC_RECOVERY_INFO 59
1577 #define IWX_UCODE_TLV_FW_FSEQ_VERSION 60
1578 #define IWX_UCODE_TLV_PHY_INTEGRATION_VERSION 61
1579 #define IWX_UCODE_TLV_PNVM_VERSION 62
1580 #define IWX_UCODE_TLV_PNVM_SKU 64
1581
1582 #define IWX_UCODE_TLV_SEC_TABLE_ADDR 66
1583 #define IWX_UCODE_TLV_D3_KEK_KCK_ADDR 67
1584 #define IWX_UCODE_TLV_CURRENT_PC 68
1585
1586 #define IWX_UCODE_TLV_CONST_BASE 0x100
1587 #define IWX_UCODE_TLV_FW_NUM_STATIONS (IWX_UCODE_TLV_CONST_BASE + 0)
1588 #define IWX_UCODE_TLV_FW_NUM_BEACONS (IWX_UCODE_TLV_CONST_BASE + 2)
1589
1590 #define IWX_UCODE_TLV_DEBUG_BASE 0x1000005
1591 #define IWX_UCODE_TLV_TYPE_DEBUG_INFO (IWX_UCODE_TLV_DEBUG_BASE + 0)
1592 #define IWX_UCODE_TLV_TYPE_BUFFER_ALLOCATION (IWX_UCODE_TLV_DEBUG_BASE + 1)
1593 #define IWX_UCODE_TLV_TYPE_HCMD (IWX_UCODE_TLV_DEBUG_BASE + 2)
1594 #define IWX_UCODE_TLV_TYPE_REGIONS (IWX_UCODE_TLV_DEBUG_BASE + 3)
1595 #define IWX_UCODE_TLV_TYPE_TRIGGERS (IWX_UCODE_TLV_DEBUG_BASE + 4)
1596 #define IWX_UCODE_TLV_TYPE_CONF_SET (IWX_UCODE_TLV_DEBUG_BASE + 5)
1597 #define IWX_UCODE_TLV_DEBUG_MAX IWX_UCODE_TLV_TYPE_CONF_SET
1598
1599
1600 struct iwx_ucode_tlv {
1601 uint32_t type; /* see above */
1602 uint32_t length; /* not including type/length fields */
1603 uint8_t data[0];
1604 };
1605
1606 struct iwx_ucode_api {
1607 uint32_t api_index;
1608 uint32_t api_flags;
1609 } __packed;
1610
1611 struct iwx_ucode_capa {
1612 uint32_t api_index;
1613 uint32_t api_capa;
1614 } __packed;
1615
1616 #define IWX_TLV_UCODE_MAGIC 0x0a4c5749
1617
1618 struct iwx_tlv_ucode_header {
1619 /*
1620 * The TLV style ucode header is distinguished from
1621 * the v1/v2 style header by first four bytes being
1622 * zero, as such is an invalid combination of
1623 * major/minor/API/serial versions.
1624 */
1625 uint32_t zero;
1626 uint32_t magic;
1627 uint8_t human_readable[64];
1628 uint32_t ver; /* major/minor/API/serial */
1629 uint32_t build;
1630 uint64_t ignore;
1631 /*
1632 * The data contained herein has a TLV layout,
1633 * see above for the TLV header and types.
1634 * Note that each TLV is padded to a length
1635 * that is a multiple of 4 for alignment.
1636 */
1637 uint8_t data[0];
1638 };
1639
1640 /*
1641 * Registers in this file are internal, not PCI bus memory mapped.
1642 * Driver accesses these via IWX_HBUS_TARG_PRPH_* registers.
1643 */
1644 #define IWX_PRPH_BASE (0x00000)
1645 #define IWX_PRPH_END (0xFFFFF)
1646
1647 /****************************/
1648 /* Flow Handler Definitions */
1649 /****************************/
1650
1651 /**
1652 * struct iwx_rb_status - receive buffer status
1653 * host memory mapped FH registers
1654 * @closed_rb_num [0:11] - Indicates the index of the RB which was closed
1655 * @closed_fr_num [0:11] - Indicates the index of the RX Frame which was closed
1656 * @finished_rb_num [0:11] - Indicates the index of the current RB
1657 * in which the last frame was written to
1658 * @finished_fr_num [0:11] - Indicates the index of the RX Frame
1659 * which was transferred
1660 */
1661 struct iwx_rb_status {
1662 uint16_t closed_rb_num;
1663 uint16_t closed_fr_num;
1664 uint16_t finished_rb_num;
1665 uint16_t finished_fr_nam;
1666 uint32_t unused;
1667 } __packed;
1668
1669
1670 #define IWX_TFD_QUEUE_SIZE_MAX (256)
1671 #define IWX_TFD_QUEUE_SIZE_MAX_GEN3 (65536)
1672 /* cb size is the exponent - 3 */
1673 #define IWX_TFD_QUEUE_CB_SIZE(x) (IWX_RX_QUEUE_CB_SIZE(x) - 3)
1674 #define IWX_TFD_QUEUE_SIZE_BC_DUP (64)
1675 #define IWX_TFD_QUEUE_BC_SIZE (IWX_TFD_QUEUE_SIZE_MAX + \
1676 IWX_TFD_QUEUE_SIZE_BC_DUP)
1677 #define IWX_TFD_QUEUE_BC_SIZE_GEN3_AX210 1024
1678 #define IWX_TFD_QUEUE_BC_SIZE_GEN3_BZ (1024 * 4)
1679 #define IWX_TFH_NUM_TBS 25
1680
1681 /**
1682 * struct iwx_tfh_tb transmit buffer descriptor within transmit frame descriptor
1683 *
1684 * This structure contains dma address and length of transmission address
1685 *
1686 * @tb_len length of the tx buffer
1687 * @addr 64 bits dma address
1688 */
1689 struct iwx_tfh_tb {
1690 uint16_t tb_len;
1691 uint64_t addr;
1692 } __packed;
1693
1694 /**
1695 * Each Tx queue uses a circular buffer of 256 TFDs stored in host DRAM.
1696 * Both driver and device share these circular buffers, each of which must be
1697 * contiguous 256 TFDs.
1698 * For pre 22000 HW it is 256 x 128 bytes-per-TFD = 32 KBytes
1699 * For 22000 HW and on it is 256 x 256 bytes-per-TFD = 65 KBytes
1700 *
1701 * Each TFD contains pointer/size information for up to 25 data buffers
1702 * in host DRAM. These buffers collectively contain the (one) frame described
1703 * by the TFD. Each buffer must be a single contiguous block of memory within
1704 * itself, but buffers may be scattered in host DRAM. Each buffer has max size
1705 * of (4K - 4). The concatenates all of a TFD's buffers into a single
1706 * Tx frame, up to 8 KBytes in size.
1707 *
1708 * A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
1709 */
1710
1711 /**
1712 * struct iwx_tfh_tfd - Transmit Frame Descriptor (TFD)
1713 * @ num_tbs 0-4 number of active tbs
1714 * 5 -15 reserved
1715 * @ tbs[25] transmit frame buffer descriptors
1716 * @ __pad padding
1717 */
1718 struct iwx_tfh_tfd {
1719 uint16_t num_tbs;
1720 struct iwx_tfh_tb tbs[IWX_TFH_NUM_TBS];
1721 uint32_t __pad;
1722 } __packed;
1723
1724 /* Fixed (non-configurable) rx data from phy */
1725
1726 /**
1727 * struct iwx_agn_schedq_bc_tbl scheduler byte count table
1728 * base physical address provided by IWX_SCD_DRAM_BASE_ADDR
1729 * @tfd_offset 0-11 - tx command byte count
1730 * 12-13 - number of 64 byte chunks
1731 * 14-15 - reserved
1732 */
1733 struct iwx_agn_scd_bc_tbl {
1734 uint16_t tfd_offset[IWX_TFD_QUEUE_BC_SIZE];
1735 } __packed;
1736
1737 /**
1738 * struct iwx_gen3_bc_tbl_entry scheduler byte count table entry gen3
1739 * For AX210 and up, the table no longer needs to be contiguous in memory.
1740 * @tfd_offset: 0-13 - tx command byte count
1741 * 14-15 - number of 64 byte chunks
1742 */
1743 struct iwx_gen3_bc_tbl_entry {
1744 uint16_t tfd_offset;
1745 } __packed;
1746
1747 /**
1748 * DQA - Dynamic Queue Allocation -introduction
1749 *
1750 * Dynamic Queue Allocation (AKA "DQA") is a feature implemented in iwlwifi
1751 * to allow dynamic allocation of queues on-demand, rather than allocate them
1752 * statically ahead of time. Ideally, we would like to allocate one queue
1753 * per RA/TID, thus allowing an AP - for example - to send BE traffic to STA2
1754 * even if it also needs to send traffic to a sleeping STA1, without being
1755 * blocked by the sleeping station.
1756 *
1757 * Although the queues in DQA mode are dynamically allocated, there are still
1758 * some queues that are statically allocated:
1759 * TXQ #0 - command queue
1760 * TXQ #1 - aux frames
1761 */
1762
1763 /* static DQA Tx queue numbers */
1764 #define IWX_DQA_CMD_QUEUE 0
1765 #define IWX_DQA_AUX_QUEUE 1
1766
1767 #define IWX_DQA_INJECT_MONITOR_QUEUE 2 /* used in monitor mode only */
1768 #define IWX_DQA_MGMT_QUEUE 1 /* default queue other modes */
1769
1770 /* Reserve 8 DQA Tx queues for QoS data frames. */
1771 #define IWX_MAX_TID_COUNT 8
1772 #define IWX_FIRST_AGG_TX_QUEUE (IWX_DQA_MGMT_QUEUE + 1)
1773 #define IWX_LAST_AGG_TX_QUEUE (IWX_FIRST_AGG_TX_QUEUE + IWX_MAX_TID_COUNT - 1)
1774 #define IWX_NUM_TX_QUEUES (IWX_LAST_AGG_TX_QUEUE + 1)
1775
1776 /**
1777 * Max Tx window size is the max number of contiguous TFDs that the scheduler
1778 * can keep track of at one time when creating block-ack chains of frames.
1779 * Note that "64" matches the number of ack bits in a block-ack packet.
1780 */
1781 #define IWX_FRAME_LIMIT 64
1782
1783 #define IWX_TX_FIFO_BK 0
1784 #define IWX_TX_FIFO_BE 1
1785 #define IWX_TX_FIFO_VI 2
1786 #define IWX_TX_FIFO_VO 3
1787 #define IWX_TX_FIFO_MCAST 5
1788 #define IWX_TX_FIFO_CMD 7
1789
1790 enum iwx_gen2_tx_fifo {
1791 IWX_GEN2_TX_FIFO_CMD = 0,
1792 IWX_GEN2_EDCA_TX_FIFO_BK,
1793 IWX_GEN2_EDCA_TX_FIFO_BE,
1794 IWX_GEN2_EDCA_TX_FIFO_VI,
1795 IWX_GEN2_EDCA_TX_FIFO_VO,
1796 IWX_GEN2_TRIG_TX_FIFO_BK,
1797 IWX_GEN2_TRIG_TX_FIFO_BE,
1798 IWX_GEN2_TRIG_TX_FIFO_VI,
1799 IWX_GEN2_TRIG_TX_FIFO_VO,
1800 };
1801
1802 /**
1803 * TXQ config options
1804 * @TX_QUEUE_CFG_ENABLE_QUEUE: enable a queue
1805 * @TX_QUEUE_CFG_TFD_SHORT_FORMAT: use short TFD format
1806 */
1807 #define IWX_TX_QUEUE_CFG_ENABLE_QUEUE (1 << 0)
1808 #define IWX_TX_QUEUE_CFG_TFD_SHORT_FORMAT (1 << 1)
1809
1810 #define IWX_DEFAULT_QUEUE_SIZE IWX_TFD_QUEUE_SIZE_MAX
1811
1812 /**
1813 * struct iwx_tx_queue_cfg_cmd - txq hw scheduler config command
1814 * @sta_id: station id
1815 * @tid: tid of the queue
1816 * @flags: see &enum iwl_tx_queue_cfg_actions
1817 * @cb_size: size of TFD cyclic buffer. Value is exponent - 3.
1818 * Minimum value 0 (8 TFDs), maximum value 5 (256 TFDs)
1819 * @byte_cnt_addr: address of byte count table
1820 * @tfdq_addr: address of TFD circular buffer
1821 */
1822 struct iwx_tx_queue_cfg_cmd {
1823 uint8_t sta_id;
1824 uint8_t tid;
1825 uint16_t flags;
1826 uint32_t cb_size;
1827 uint64_t byte_cnt_addr;
1828 uint64_t tfdq_addr;
1829 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_2 */
1830
1831 /**
1832 * struct iwx_tx_queue_cfg_rsp - response to txq hw scheduler config
1833 * @queue_number: queue number assigned to this RA -TID
1834 * @flags: set on failure
1835 * @write_pointer: initial value for write pointer
1836 * @reserved: reserved
1837 */
1838 struct iwx_tx_queue_cfg_rsp {
1839 uint16_t queue_number;
1840 uint16_t flags;
1841 uint16_t write_pointer;
1842 uint16_t reserved;
1843 } __packed; /* TX_QUEUE_CFG_RSP_API_S_VER_2 */
1844
1845
1846 /*
1847 * Commands
1848 */
1849 #define IWX_ALIVE 0x1
1850 #define IWX_REPLY_ERROR 0x2
1851 #define IWX_INIT_COMPLETE_NOTIF 0x4
1852
1853 /* PHY context commands */
1854 #define IWX_PHY_CONTEXT_CMD 0x8
1855 #define IWX_DBG_CFG 0x9
1856
1857 /* UMAC scan commands */
1858 #define IWX_SCAN_ITERATION_COMPLETE_UMAC 0xb5
1859 #define IWX_SCAN_CFG_CMD 0xc
1860 #define IWX_SCAN_REQ_UMAC 0xd
1861 #define IWX_SCAN_ABORT_UMAC 0xe
1862 #define IWX_SCAN_COMPLETE_UMAC 0xf
1863
1864 /* station table */
1865 #define IWX_ADD_STA_KEY 0x17
1866 #define IWX_ADD_STA 0x18
1867 #define IWX_REMOVE_STA 0x19
1868
1869 /* TX */
1870 #define IWX_TX_CMD 0x1c
1871 #define IWX_TXPATH_FLUSH 0x1e
1872 #define IWX_MGMT_MCAST_KEY 0x1f
1873
1874 /* scheduler config */
1875 #define IWX_SCD_QUEUE_CFG 0x1d
1876
1877 /* global key */
1878 #define IWX_WEP_KEY 0x20
1879
1880 /* MAC and Binding commands */
1881 #define IWX_MAC_CONTEXT_CMD 0x28
1882 #define IWX_TIME_EVENT_CMD 0x29 /* both CMD and response */
1883 #define IWX_TIME_EVENT_NOTIFICATION 0x2a
1884 #define IWX_BINDING_CONTEXT_CMD 0x2b
1885 #define IWX_TIME_QUOTA_CMD 0x2c
1886 #define IWX_NON_QOS_TX_COUNTER_CMD 0x2d
1887
1888 /* Calibration */
1889 #define IWX_TEMPERATURE_NOTIFICATION 0x62
1890 #define IWX_CALIBRATION_CFG_CMD 0x65
1891 #define IWX_CALIBRATION_RES_NOTIFICATION 0x66
1892 #define IWX_CALIBRATION_COMPLETE_NOTIFICATION 0x67
1893 #define IWX_RADIO_VERSION_NOTIFICATION 0x68
1894
1895 /* Phy */
1896 #define IWX_PHY_CONFIGURATION_CMD 0x6a
1897
1898 /* Power - legacy power table command */
1899 #define IWX_POWER_TABLE_CMD 0x77
1900 #define IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION 0x78
1901 #define IWX_LTR_CONFIG 0xee
1902
1903 /* NVM */
1904 #define IWX_NVM_ACCESS_CMD 0x88
1905
1906 #define IWX_SET_CALIB_DEFAULT_CMD 0x8e
1907
1908 #define IWX_BEACON_NOTIFICATION 0x90
1909 #define IWX_BEACON_TEMPLATE_CMD 0x91
1910 #define IWX_TX_ANT_CONFIGURATION_CMD 0x98
1911 #define IWX_BT_CONFIG 0x9b
1912 #define IWX_STATISTICS_CMD 0x9c
1913 #define IWX_STATISTICS_NOTIFICATION 0x9d
1914 #define IWX_REDUCE_TX_POWER_CMD 0x9f
1915
1916 /* RF-KILL commands and notifications */
1917 #define IWX_CARD_STATE_CMD 0xa0
1918 #define IWX_CARD_STATE_NOTIFICATION 0xa1
1919
1920 #define IWX_MISSED_BEACONS_NOTIFICATION 0xa2
1921
1922 #define IWX_MFUART_LOAD_NOTIFICATION 0xb1
1923
1924 /* Power - new power table command */
1925 #define IWX_MAC_PM_POWER_TABLE 0xa9
1926
1927 #define IWX_REPLY_RX_PHY_CMD 0xc0
1928 #define IWX_REPLY_RX_MPDU_CMD 0xc1
1929 #define IWX_BAR_FRAME_RELEASE 0xc2
1930 #define IWX_FRAME_RELEASE 0xc3
1931 #define IWX_BA_NOTIF 0xc5
1932
1933 /* Location Aware Regulatory */
1934 #define IWX_MCC_UPDATE_CMD 0xc8
1935 #define IWX_MCC_CHUB_UPDATE_CMD 0xc9
1936
1937 /* BT Coex */
1938 #define IWX_BT_COEX_PRIO_TABLE 0xcc
1939 #define IWX_BT_COEX_PROT_ENV 0xcd
1940 #define IWX_BT_PROFILE_NOTIFICATION 0xce
1941 #define IWX_BT_COEX_CI 0x5d
1942
1943 #define IWX_REPLY_SF_CFG_CMD 0xd1
1944 #define IWX_REPLY_BEACON_FILTERING_CMD 0xd2
1945
1946 /* DTS measurements */
1947 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER 0xdc
1948 #define IWX_DTS_MEASUREMENT_NOTIFICATION 0xdd
1949
1950 #define IWX_REPLY_DEBUG_CMD 0xf0
1951 #define IWX_DEBUG_LOG_MSG 0xf7
1952
1953 #define IWX_MCAST_FILTER_CMD 0xd0
1954
1955 /* D3 commands/notifications */
1956 #define IWX_D3_CONFIG_CMD 0xd3
1957 #define IWX_PROT_OFFLOAD_CONFIG_CMD 0xd4
1958 #define IWX_OFFLOADS_QUERY_CMD 0xd5
1959 #define IWX_REMOTE_WAKE_CONFIG_CMD 0xd6
1960
1961 /* for WoWLAN in particular */
1962 #define IWX_WOWLAN_PATTERNS 0xe0
1963 #define IWX_WOWLAN_CONFIGURATION 0xe1
1964 #define IWX_WOWLAN_TSC_RSC_PARAM 0xe2
1965 #define IWX_WOWLAN_TKIP_PARAM 0xe3
1966 #define IWX_WOWLAN_KEK_KCK_MATERIAL 0xe4
1967 #define IWX_WOWLAN_GET_STATUSES 0xe5
1968 #define IWX_WOWLAN_TX_POWER_PER_DB 0xe6
1969
1970 /* and for NetDetect */
1971 #define IWX_NET_DETECT_CONFIG_CMD 0x54
1972 #define IWX_NET_DETECT_PROFILES_QUERY_CMD 0x56
1973 #define IWX_NET_DETECT_PROFILES_CMD 0x57
1974 #define IWX_NET_DETECT_HOTSPOTS_CMD 0x58
1975 #define IWX_NET_DETECT_HOTSPOTS_QUERY_CMD 0x59
1976
1977 /* system group command IDs */
1978 #define IWX_FSEQ_VER_MISMATCH_NOTIFICATION 0xff
1979
1980 #define IWX_REPLY_MAX 0xff
1981
1982 /* PHY_OPS subcommand IDs */
1983 #define IWX_CMD_DTS_MEASUREMENT_TRIGGER_WIDE 0x0
1984 #define IWX_CTDP_CONFIG_CMD 0x03
1985 #define IWX_TEMP_REPORTING_THRESHOLDS_CMD 0x04
1986 #define IWX_CT_KILL_NOTIFICATION 0xFE
1987 #define IWX_DTS_MEASUREMENT_NOTIF_WIDE 0xFF
1988
1989 /* command groups */
1990 #define IWX_LEGACY_GROUP 0x0
1991 #define IWX_LONG_GROUP 0x1
1992 #define IWX_SYSTEM_GROUP 0x2
1993 #define IWX_MAC_CONF_GROUP 0x3
1994 #define IWX_PHY_OPS_GROUP 0x4
1995 #define IWX_DATA_PATH_GROUP 0x5
1996 #define IWX_PROT_OFFLOAD_GROUP 0xb
1997 #define IWX_REGULATORY_AND_NVM_GROUP 0xc
1998
1999 /* SYSTEM_GROUP group subcommand IDs */
2000
2001 #define IWX_SHARED_MEM_CFG_CMD 0x00
2002 #define IWX_SOC_CONFIGURATION_CMD 0x01
2003 #define IWX_INIT_EXTENDED_CFG_CMD 0x03
2004 #define IWX_FW_ERROR_RECOVERY_CMD 0x07
2005
2006 /* MAC_CONF group subcommand IDs */
2007 #define IWX_SESSION_PROTECTION_CMD 0x05
2008 #define IWX_SESSION_PROTECTION_NOTIF 0xfb
2009
2010 /* DATA_PATH group subcommand IDs */
2011 #define IWX_DQA_ENABLE_CMD 0x00
2012 #define IWX_RLC_CONFIG_CMD 0x08
2013 #define IWX_TLC_MNG_CONFIG_CMD 0x0f
2014 #define IWX_RX_BAID_ALLOCATION_CONFIG_CMD 0x16
2015 #define IWX_SCD_QUEUE_CONFIG_CMD 0x17
2016 #define IWX_RX_NO_DATA_NOTIF 0xf5
2017 #define IWX_TLC_MNG_UPDATE_NOTIF 0xf7
2018
2019 /* REGULATORY_AND_NVM group subcommand IDs */
2020 #define IWX_NVM_ACCESS_COMPLETE 0x00
2021 #define IWX_NVM_GET_INFO 0x02
2022 #define IWX_NVM_GET_INFO 0x02
2023 #define IWX_PNVM_INIT_COMPLETE 0xfe
2024
2025 /*
2026 * struct iwx_dqa_enable_cmd
2027 * @cmd_queue: the TXQ number of the command queue
2028 */
2029 struct iwx_dqa_enable_cmd {
2030 uint32_t cmd_queue;
2031 } __packed; /* DQA_CONTROL_CMD_API_S_VER_1 */
2032
2033 /**
2034 * struct iwx_cmd_response - generic response struct for most commands
2035 * @status: status of the command asked, changes for each one
2036 */
2037 struct iwx_cmd_response {
2038 uint32_t status;
2039 };
2040
2041 /*
2042 * struct iwx_tx_ant_cfg_cmd
2043 * @valid: valid antenna configuration
2044 */
2045 struct iwx_tx_ant_cfg_cmd {
2046 uint32_t valid;
2047 } __packed;
2048
2049 /*
2050 * Calibration control struct.
2051 * Sent as part of the phy configuration command.
2052 * @flow_trigger: bitmap for which calibrations to perform according to
2053 * flow triggers.
2054 * @event_trigger: bitmap for which calibrations to perform according to
2055 * event triggers.
2056 */
2057 struct iwx_calib_ctrl {
2058 uint32_t flow_trigger;
2059 uint32_t event_trigger;
2060 } __packed;
2061
2062 /* This defines the bitmap of various calibrations to enable in both
2063 * init ucode and runtime ucode through IWX_CALIBRATION_CFG_CMD.
2064 */
2065 #define IWX_CALIB_CFG_XTAL_IDX (1 << 0)
2066 #define IWX_CALIB_CFG_TEMPERATURE_IDX (1 << 1)
2067 #define IWX_CALIB_CFG_VOLTAGE_READ_IDX (1 << 2)
2068 #define IWX_CALIB_CFG_PAPD_IDX (1 << 3)
2069 #define IWX_CALIB_CFG_TX_PWR_IDX (1 << 4)
2070 #define IWX_CALIB_CFG_DC_IDX (1 << 5)
2071 #define IWX_CALIB_CFG_BB_FILTER_IDX (1 << 6)
2072 #define IWX_CALIB_CFG_LO_LEAKAGE_IDX (1 << 7)
2073 #define IWX_CALIB_CFG_TX_IQ_IDX (1 << 8)
2074 #define IWX_CALIB_CFG_TX_IQ_SKEW_IDX (1 << 9)
2075 #define IWX_CALIB_CFG_RX_IQ_IDX (1 << 10)
2076 #define IWX_CALIB_CFG_RX_IQ_SKEW_IDX (1 << 11)
2077 #define IWX_CALIB_CFG_SENSITIVITY_IDX (1 << 12)
2078 #define IWX_CALIB_CFG_CHAIN_NOISE_IDX (1 << 13)
2079 #define IWX_CALIB_CFG_DISCONNECTED_ANT_IDX (1 << 14)
2080 #define IWX_CALIB_CFG_ANT_COUPLING_IDX (1 << 15)
2081 #define IWX_CALIB_CFG_DAC_IDX (1 << 16)
2082 #define IWX_CALIB_CFG_ABS_IDX (1 << 17)
2083 #define IWX_CALIB_CFG_AGC_IDX (1 << 18)
2084
2085 /*
2086 * Phy configuration command.
2087 */
2088 struct iwx_phy_cfg_cmd {
2089 uint32_t phy_cfg;
2090 struct iwx_calib_ctrl calib_control;
2091 } __packed;
2092
2093 #define IWX_PHY_CFG_RADIO_TYPE ((1 << 0) | (1 << 1))
2094 #define IWX_PHY_CFG_RADIO_STEP ((1 << 2) | (1 << 3))
2095 #define IWX_PHY_CFG_RADIO_DASH ((1 << 4) | (1 << 5))
2096 #define IWX_PHY_CFG_PRODUCT_NUMBER ((1 << 6) | (1 << 7))
2097 #define IWX_PHY_CFG_TX_CHAIN_A (1 << 8)
2098 #define IWX_PHY_CFG_TX_CHAIN_B (1 << 9)
2099 #define IWX_PHY_CFG_TX_CHAIN_C (1 << 10)
2100 #define IWX_PHY_CFG_RX_CHAIN_A (1 << 12)
2101 #define IWX_PHY_CFG_RX_CHAIN_B (1 << 13)
2102 #define IWX_PHY_CFG_RX_CHAIN_C (1 << 14)
2103
2104 #define IWX_MAX_DTS_TRIPS 8
2105
2106 /**
2107 * struct iwx_ct_kill_notif - CT-kill entry notification
2108 *
2109 * @temperature: the current temperature in celsius
2110 * @reserved: reserved
2111 */
2112 struct iwx_ct_kill_notif {
2113 uint16_t temperature;
2114 uint16_t reserved;
2115 } __packed; /* GRP_PHY_CT_KILL_NTF */
2116
2117 /**
2118 * struct iwx_temp_report_ths_cmd - set temperature thresholds
2119 * (IWX_TEMP_REPORTING_THRESHOLDS_CMD)
2120 *
2121 * @num_temps: number of temperature thresholds passed
2122 * @thresholds: array with the thresholds to be configured
2123 */
2124 struct iwx_temp_report_ths_cmd {
2125 uint32_t num_temps;
2126 uint16_t thresholds[IWX_MAX_DTS_TRIPS];
2127 } __packed; /* GRP_PHY_TEMP_REPORTING_THRESHOLDS_CMD */
2128
2129 /*
2130 * channel flags in NVM
2131 * @IWX_NVM_CHANNEL_VALID: channel is usable for this SKU/geo
2132 * @IWX_NVM_CHANNEL_IBSS: usable as an IBSS channel
2133 * @IWX_NVM_CHANNEL_ACTIVE: active scanning allowed
2134 * @IWX_NVM_CHANNEL_RADAR: radar detection required
2135 * @IWX_NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
2136 * @IWX_NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
2137 * on same channel on 2.4 or same UNII band on 5.2
2138 * @IWX_NVM_CHANNEL_DFS: dynamic freq selection candidate
2139 * @IWX_NVM_CHANNEL_WIDE: 20 MHz channel okay (?)
2140 * @IWX_NVM_CHANNEL_40MHZ: 40 MHz channel okay (?)
2141 * @IWX_NVM_CHANNEL_80MHZ: 80 MHz channel okay (?)
2142 * @IWX_NVM_CHANNEL_160MHZ: 160 MHz channel okay (?)
2143 * @IWX_NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
2144 */
2145 #define IWX_NVM_CHANNEL_VALID (1 << 0)
2146 #define IWX_NVM_CHANNEL_IBSS (1 << 1)
2147 #define IWX_NVM_CHANNEL_ACTIVE (1 << 3)
2148 #define IWX_NVM_CHANNEL_RADAR (1 << 4)
2149 #define IWX_NVM_CHANNEL_INDOOR_ONLY (1 << 5)
2150 #define IWX_NVM_CHANNEL_GO_CONCURRENT (1 << 6)
2151 #define IWX_NVM_CHANNEL_DFS (1 << 7)
2152 #define IWX_NVM_CHANNEL_WIDE (1 << 8)
2153 #define IWX_NVM_CHANNEL_40MHZ (1 << 9)
2154 #define IWX_NVM_CHANNEL_80MHZ (1 << 10)
2155 #define IWX_NVM_CHANNEL_160MHZ (1 << 11)
2156 #define IWX_NVM_CHANNEL_DC_HIGH (1 << 12)
2157
2158 /**
2159 * struct iwx_nvm_access_complete_cmd - NVM_ACCESS commands are completed
2160 * @reserved: reserved
2161 */
2162 struct iwx_nvm_access_complete_cmd {
2163 uint32_t reserved;
2164 } __packed; /* NVM_ACCESS_COMPLETE_CMD_API_S_VER_1 */
2165
2166 /*
2167 * struct iwx_nvm_get_info - request to get NVM data
2168 */
2169 struct iwx_nvm_get_info {
2170 uint32_t reserved;
2171 } __packed; /* REGULATORY_NVM_GET_INFO_CMD_API_S_VER_1 */
2172
2173 /**
2174 * enum iwx_nvm_info_general_flags - flags in NVM_GET_INFO resp
2175 * @NVM_GENERAL_FLAGS_EMPTY_OTP: 1 if OTP is empty
2176 */
2177 #define IWX_NVM_GENERAL_FLAGS_EMPTY_OTP (1 << 0)
2178
2179 /**
2180 * struct iwx_nvm_get_info_general - general NVM data
2181 * @flags: bit 0: 1 - empty, 0 - non-empty
2182 * @nvm_version: nvm version
2183 * @board_type: board type
2184 * @n_hw_addrs: number of reserved MAC addresses
2185 */
2186 struct iwx_nvm_get_info_general {
2187 uint32_t flags;
2188 uint16_t nvm_version;
2189 uint8_t board_type;
2190 uint8_t n_hw_addrs;
2191 } __packed; /* REGULATORY_NVM_GET_INFO_GENERAL_S_VER_2 */
2192
2193 /**
2194 * iwx_nvm_mac_sku_flags - flags in &iwl_nvm_get_info_sku
2195 * @NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED: true if 2.4 band enabled
2196 * @NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED: true if 5.2 band enabled
2197 * @NVM_MAC_SKU_FLAGS_802_11N_ENABLED: true if 11n enabled
2198 * @NVM_MAC_SKU_FLAGS_802_11AC_ENABLED: true if 11ac enabled
2199 * @NVM_MAC_SKU_FLAGS_802_11AX_ENABLED: true if 11ax enabled
2200 * @NVM_MAC_SKU_FLAGS_MIMO_DISABLED: true if MIMO disabled
2201 * @NVM_MAC_SKU_FLAGS_WAPI_ENABLED: true if WAPI enabled
2202 * @NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED: true if regulatory checker enabled
2203 * @NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED: true if API lock enabled
2204 */
2205 #define IWX_NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED (1 << 0)
2206 #define IWX_NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED (1 << 1)
2207 #define IWX_NVM_MAC_SKU_FLAGS_802_11N_ENABLED (1 << 2)
2208 #define IWX_NVM_MAC_SKU_FLAGS_802_11AC_ENABLED (1 << 3)
2209 #define IWX_NVM_MAC_SKU_FLAGS_802_11AX_ENABLED (1 << 4)
2210 #define IWX_NVM_MAC_SKU_FLAGS_MIMO_DISABLED (1 << 5)
2211 #define IWX_NVM_MAC_SKU_FLAGS_WAPI_ENABLED (1 << 8)
2212 #define IWX_NVM_MAC_SKU_FLAGS_REG_CHECK_ENABLED (1 << 14)
2213 #define IWX_NVM_MAC_SKU_FLAGS_API_LOCK_ENABLED (1 << 15)
2214
2215 /**
2216 * struct iwx_nvm_get_info_sku - mac information
2217 * @mac_sku_flags: flags for SKU, see &enum iwl_nvm_mac_sku_flags
2218 */
2219 struct iwx_nvm_get_info_sku {
2220 uint32_t mac_sku_flags;
2221 } __packed; /* REGULATORY_NVM_GET_INFO_MAC_SKU_SECTION_S_VER_2 */
2222
2223 /**
2224 * struct iwx_nvm_get_info_phy - phy information
2225 * @tx_chains: BIT 0 chain A, BIT 1 chain B
2226 * @rx_chains: BIT 0 chain A, BIT 1 chain B
2227 */
2228 struct iwx_nvm_get_info_phy {
2229 uint32_t tx_chains;
2230 uint32_t rx_chains;
2231 } __packed; /* REGULATORY_NVM_GET_INFO_PHY_SKU_SECTION_S_VER_1 */
2232
2233 #define IWX_NUM_CHANNELS_V1 51
2234 #define IWX_NUM_CHANNELS 110
2235
2236 /**
2237 * struct iwx_nvm_get_info_regulatory - regulatory information
2238 * @lar_enabled: is LAR enabled
2239 * @channel_profile: regulatory data of this channel
2240 * @reserved: reserved
2241 */
2242 struct iwx_nvm_get_info_regulatory_v1 {
2243 uint32_t lar_enabled;
2244 uint16_t channel_profile[IWX_NUM_CHANNELS_V1];
2245 uint16_t reserved;
2246 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_1 */
2247
2248 /**
2249 * struct iwx_nvm_get_info_regulatory - regulatory information
2250 * @lar_enabled: is LAR enabled
2251 * @n_channels: number of valid channels in the array
2252 * @channel_profile: regulatory data of this channel
2253 */
2254 struct iwx_nvm_get_info_regulatory {
2255 uint32_t lar_enabled;
2256 uint32_t n_channels;
2257 uint32_t channel_profile[IWX_NUM_CHANNELS];
2258 } __packed; /* REGULATORY_NVM_GET_INFO_REGULATORY_S_VER_2 */
2259
2260 /**
2261 * struct iwx_nvm_get_info_rsp_v3 - response to get NVM data
2262 * @general: general NVM data
2263 * @mac_sku: data relating to MAC sku
2264 * @phy_sku: data relating to PHY sku
2265 * @regulatory: regulatory data
2266 */
2267 struct iwx_nvm_get_info_rsp_v3 {
2268 struct iwx_nvm_get_info_general general;
2269 struct iwx_nvm_get_info_sku mac_sku;
2270 struct iwx_nvm_get_info_phy phy_sku;
2271 struct iwx_nvm_get_info_regulatory_v1 regulatory;
2272 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_3 */
2273
2274 /**
2275 * struct iwx_nvm_get_info_rsp - response to get NVM data
2276 * @general: general NVM data
2277 * @mac_sku: data relating to MAC sku
2278 * @phy_sku: data relating to PHY sku
2279 * @regulatory: regulatory data
2280 */
2281 struct iwx_nvm_get_info_rsp {
2282 struct iwx_nvm_get_info_general general;
2283 struct iwx_nvm_get_info_sku mac_sku;
2284 struct iwx_nvm_get_info_phy phy_sku;
2285 struct iwx_nvm_get_info_regulatory regulatory;
2286 } __packed; /* REGULATORY_NVM_GET_INFO_RSP_API_S_VER_4 */
2287
2288
2289 #define IWX_ALIVE_STATUS_ERR 0xDEAD
2290 #define IWX_ALIVE_STATUS_OK 0xCAFE
2291
2292 struct iwx_lmac_debug_addrs {
2293 uint32_t error_event_table_ptr; /* SRAM address for error log */
2294 uint32_t log_event_table_ptr; /* SRAM address for LMAC event log */
2295 uint32_t cpu_register_ptr;
2296 uint32_t dbgm_config_ptr;
2297 uint32_t alive_counter_ptr;
2298 uint32_t scd_base_ptr; /* SRAM address for SCD */
2299 uint32_t st_fwrd_addr; /* pointer to Store and forward */
2300 uint32_t st_fwrd_size;
2301 } __packed; /* UCODE_DEBUG_ADDRS_API_S_VER_2 */
2302
2303 struct iwx_lmac_alive {
2304 uint32_t ucode_major;
2305 uint32_t ucode_minor;
2306 uint8_t ver_subtype;
2307 uint8_t ver_type;
2308 uint8_t mac;
2309 uint8_t opt;
2310 uint32_t timestamp;
2311 struct iwx_lmac_debug_addrs dbg_ptrs;
2312 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_3 */
2313
2314 struct iwx_umac_debug_addrs {
2315 uint32_t error_info_addr; /* SRAM address for UMAC error log */
2316 uint32_t dbg_print_buff_addr;
2317 } __packed; /* UMAC_DEBUG_ADDRS_API_S_VER_1 */
2318
2319 struct iwx_umac_alive {
2320 uint32_t umac_major; /* UMAC version: major */
2321 uint32_t umac_minor; /* UMAC version: minor */
2322 struct iwx_umac_debug_addrs dbg_ptrs;
2323 } __packed; /* UMAC_ALIVE_DATA_API_S_VER_2 */
2324
2325 struct iwx_alive_resp_v4 {
2326 uint16_t status;
2327 uint16_t flags;
2328 struct iwx_lmac_alive lmac_data[2];
2329 struct iwx_umac_alive umac_data;
2330 } __packed; /* ALIVE_RES_API_S_VER_4 */
2331
2332 struct iwx_sku_id {
2333 uint32_t data[3];
2334 } __packed; /* SKU_ID_API_S_VER_1 */
2335
2336 struct iwx_alive_resp_v5 {
2337 uint16_t status;
2338 uint16_t flags;
2339 struct iwx_lmac_alive lmac_data[2];
2340 struct iwx_umac_alive umac_data;
2341 struct iwx_sku_id sku_id;
2342 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_5 */
2343
2344 struct iwx_imr_alive_info {
2345 uint64_t base_addr;
2346 uint32_t size;
2347 uint32_t enabled;
2348 } __packed; /* IMR_ALIVE_INFO_API_S_VER_1 */
2349
2350 struct iwx_alive_resp_v6 {
2351 uint16_t status;
2352 uint16_t flags;
2353 struct iwx_lmac_alive lmac_data[2];
2354 struct iwx_umac_alive umac_data;
2355 struct iwx_sku_id sku_id;
2356 struct iwx_imr_alive_info imr;
2357 } __packed; /* UCODE_ALIVE_NTFY_API_S_VER_6 */
2358
2359
2360 #define IWX_SOC_CONFIG_CMD_FLAGS_DISCRETE (1 << 0)
2361 #define IWX_SOC_CONFIG_CMD_FLAGS_LOW_LATENCY (1 << 1)
2362
2363 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_MASK 0xc
2364 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_NONE 0
2365 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_200 1
2366 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_2500 2
2367 #define IWX_SOC_FLAGS_LTR_APPLY_DELAY_1820 3
2368
2369 /**
2370 * struct iwx_soc_configuration_cmd - Set device stabilization latency
2371 *
2372 * @flags: soc settings flags. In VER_1, we can only set the DISCRETE
2373 * flag, because the FW treats the whole value as an integer. In
2374 * VER_2, we can set the bits independently.
2375 * @latency: time for SOC to ensure stable power & XTAL
2376 */
2377 struct iwx_soc_configuration_cmd {
2378 uint32_t flags;
2379 uint32_t latency;
2380 } __packed; /*
2381 * SOC_CONFIGURATION_CMD_S_VER_1 (see description above)
2382 * SOC_CONFIGURATION_CMD_S_VER_2
2383 */
2384
2385 /**
2386 * commands driver may send before finishing init flow
2387 * @IWX_INIT_DEBUG_CFG: driver is going to send debug config command
2388 * @IWX_INIT_NVM: driver is going to send NVM_ACCESS commands
2389 */
2390 #define IWX_INIT_DEBUG_CFG (1 << 0)
2391 #define IWX_INIT_NVM (1 << 1)
2392
2393 /**
2394 * struct iwx_extended_cfg_cmd - mark what commands ucode should wait for
2395 * before finishing init flows
2396 * @init_flags: IWX_INIT_* flag bits
2397 */
2398 struct iwx_init_extended_cfg_cmd {
2399 uint32_t init_flags;
2400 } __packed; /* INIT_EXTENDED_CFG_CMD_API_S_VER_1 */
2401
2402 /* Error response/notification */
2403 #define IWX_FW_ERR_UNKNOWN_CMD 0x0
2404 #define IWX_FW_ERR_INVALID_CMD_PARAM 0x1
2405 #define IWX_FW_ERR_SERVICE 0x2
2406 #define IWX_FW_ERR_ARC_MEMORY 0x3
2407 #define IWX_FW_ERR_ARC_CODE 0x4
2408 #define IWX_FW_ERR_WATCH_DOG 0x5
2409 #define IWX_FW_ERR_WEP_GRP_KEY_INDX 0x10
2410 #define IWX_FW_ERR_WEP_KEY_SIZE 0x11
2411 #define IWX_FW_ERR_OBSOLETE_FUNC 0x12
2412 #define IWX_FW_ERR_UNEXPECTED 0xFE
2413 #define IWX_FW_ERR_FATAL 0xFF
2414
2415 /**
2416 * struct iwx_error_resp - FW error indication
2417 * ( IWX_REPLY_ERROR = 0x2 )
2418 * @error_type: one of IWX_FW_ERR_*
2419 * @cmd_id: the command ID for which the error occurred
2420 * @bad_cmd_seq_num: sequence number of the erroneous command
2421 * @error_service: which service created the error, applicable only if
2422 * error_type = 2, otherwise 0
2423 * @timestamp: TSF in usecs.
2424 */
2425 struct iwx_error_resp {
2426 uint32_t error_type;
2427 uint8_t cmd_id;
2428 uint8_t reserved1;
2429 uint16_t bad_cmd_seq_num;
2430 uint32_t error_service;
2431 uint64_t timestamp;
2432 } __packed;
2433
2434 enum iwx_fw_dbg_reg_operator {
2435 CSR_ASSIGN,
2436 CSR_SETBIT,
2437 CSR_CLEARBIT,
2438
2439 PRPH_ASSIGN,
2440 PRPH_SETBIT,
2441 PRPH_CLEARBIT,
2442
2443 INDIRECT_ASSIGN,
2444 INDIRECT_SETBIT,
2445 INDIRECT_CLEARBIT,
2446
2447 PRPH_BLOCKBIT,
2448 };
2449
2450 /**
2451 * struct iwx_fw_dbg_reg_op - an operation on a register
2452 *
2453 * @op: &enum iwx_fw_dbg_reg_operator
2454 * @addr: offset of the register
2455 * @val: value
2456 */
2457 struct iwx_fw_dbg_reg_op {
2458 uint8_t op;
2459 uint8_t reserved[3];
2460 uint32_t addr;
2461 uint32_t val;
2462 } __packed;
2463
2464 /**
2465 * enum iwx_fw_dbg_monitor_mode - available monitor recording modes
2466 *
2467 * @SMEM_MODE: monitor stores the data in SMEM
2468 * @EXTERNAL_MODE: monitor stores the data in allocated DRAM
2469 * @MARBH_MODE: monitor stores the data in MARBH buffer
2470 * @MIPI_MODE: monitor outputs the data through the MIPI interface
2471 */
2472 enum iwx_fw_dbg_monitor_mode {
2473 SMEM_MODE = 0,
2474 EXTERNAL_MODE = 1,
2475 MARBH_MODE = 2,
2476 MIPI_MODE = 3,
2477 };
2478
2479 /**
2480 * struct iwx_fw_dbg_mem_seg_tlv - configures the debug data memory segments
2481 *
2482 * @data_type: the memory segment type to record
2483 * @ofs: the memory segment offset
2484 * @len: the memory segment length, in bytes
2485 *
2486 * This parses IWX_UCODE_TLV_FW_MEM_SEG
2487 */
2488 struct iwx_fw_dbg_mem_seg_tlv {
2489 uint32_t data_type;
2490 uint32_t ofs;
2491 uint32_t len;
2492 } __packed;
2493
2494 /**
2495 * struct iwx_fw_dbg_dest_tlv_v1 - configures the destination of the debug data
2496 *
2497 * @version: version of the TLV - currently 0
2498 * @monitor_mode: &enum iwx_fw_dbg_monitor_mode
2499 * @size_power: buffer size will be 2^(size_power + 11)
2500 * @base_reg: addr of the base addr register (PRPH)
2501 * @end_reg: addr of the end addr register (PRPH)
2502 * @write_ptr_reg: the addr of the reg of the write pointer
2503 * @wrap_count: the addr of the reg of the wrap_count
2504 * @base_shift: shift right of the base addr reg
2505 * @end_shift: shift right of the end addr reg
2506 * @reg_ops: array of registers operations
2507 *
2508 * This parses IWX_UCODE_TLV_FW_DBG_DEST
2509 */
2510 struct iwx_fw_dbg_dest_tlv_v1 {
2511 uint8_t version;
2512 uint8_t monitor_mode;
2513 uint8_t size_power;
2514 uint8_t reserved;
2515 uint32_t base_reg;
2516 uint32_t end_reg;
2517 uint32_t write_ptr_reg;
2518 uint32_t wrap_count;
2519 uint8_t base_shift;
2520 uint8_t end_shift;
2521 struct iwx_fw_dbg_reg_op reg_ops[0];
2522 } __packed;
2523
2524 /* Mask of the register for defining the LDBG MAC2SMEM buffer SMEM size */
2525 #define IWX_LDBG_M2S_BUF_SIZE_MSK 0x0fff0000
2526 /* Mask of the register for defining the LDBG MAC2SMEM SMEM base address */
2527 #define IWX_LDBG_M2S_BUF_BA_MSK 0x00000fff
2528 /* The smem buffer chunks are in units of 256 bits */
2529 #define IWX_M2S_UNIT_SIZE 0x100
2530
2531 struct iwx_fw_dbg_dest_tlv {
2532 uint8_t version;
2533 uint8_t monitor_mode;
2534 uint8_t size_power;
2535 uint8_t reserved;
2536 uint32_t cfg_reg;
2537 uint32_t write_ptr_reg;
2538 uint32_t wrap_count;
2539 uint8_t base_shift;
2540 uint8_t size_shift;
2541 struct iwx_fw_dbg_reg_op reg_ops[0];
2542 } __packed;
2543
2544 struct iwx_fw_dbg_conf_hcmd {
2545 uint8_t id;
2546 uint8_t reserved;
2547 uint16_t len;
2548 uint8_t data[0];
2549 } __packed;
2550
2551 /**
2552 * enum iwx_fw_dbg_trigger_mode - triggers functionalities
2553 *
2554 * @IWX_FW_DBG_TRIGGER_START: when trigger occurs re-conf the dbg mechanism
2555 * @IWX_FW_DBG_TRIGGER_STOP: when trigger occurs pull the dbg data
2556 * @IWX_FW_DBG_TRIGGER_MONITOR_ONLY: when trigger occurs trigger is set to
2557 * collect only monitor data
2558 */
2559 enum iwx_fw_dbg_trigger_mode {
2560 IWX_FW_DBG_TRIGGER_START = (1 << 0),
2561 IWX_FW_DBG_TRIGGER_STOP = (1 << 1),
2562 IWX_FW_DBG_TRIGGER_MONITOR_ONLY = (1 << 2),
2563 };
2564
2565 /**
2566 * enum iwx_fw_dbg_trigger_flags - the flags supported by wrt triggers
2567 * @IWX_FW_DBG_FORCE_RESTART: force a firmware restart
2568 */
2569 enum iwx_fw_dbg_trigger_flags {
2570 IWX_FW_DBG_FORCE_RESTART = (1 << 0),
2571 };
2572
2573 /**
2574 * enum iwx_fw_dbg_trigger_vif_type - define the VIF type for a trigger
2575 * @IWX_FW_DBG_CONF_VIF_ANY: any vif type
2576 * @IWX_FW_DBG_CONF_VIF_IBSS: IBSS mode
2577 * @IWX_FW_DBG_CONF_VIF_STATION: BSS mode
2578 * @IWX_FW_DBG_CONF_VIF_AP: AP mode
2579 * @IWX_FW_DBG_CONF_VIF_P2P_CLIENT: P2P Client mode
2580 * @IWX_FW_DBG_CONF_VIF_P2P_GO: P2P GO mode
2581 * @IWX_FW_DBG_CONF_VIF_P2P_DEVICE: P2P device
2582 * @IWX_FW_DBG_CONF_VIF_NAN: NAN device
2583 */
2584 enum iwx_fw_dbg_trigger_vif_type {
2585 IWX_FW_DBG_CONF_VIF_ANY = 0,
2586 IWX_FW_DBG_CONF_VIF_IBSS = 1,
2587 IWX_FW_DBG_CONF_VIF_STATION = 2,
2588 IWX_FW_DBG_CONF_VIF_AP = 3,
2589 IWX_FW_DBG_CONF_VIF_P2P_CLIENT = 8,
2590 IWX_FW_DBG_CONF_VIF_P2P_GO = 9,
2591 IWX_FW_DBG_CONF_VIF_P2P_DEVICE = 10,
2592 IWX_FW_DBG_CONF_VIF_NAN = 12,
2593 };
2594
2595 /**
2596 * enum iwl_fw_dbg_trigger - triggers available
2597 *
2598 * @FW_DBG_TRIGGER_USER: trigger log collection by user
2599 * This should not be defined as a trigger to the driver, but a value the
2600 * driver should set to indicate that the trigger was initiated by the
2601 * user.
2602 * @FW_DBG_TRIGGER_FW_ASSERT: trigger log collection when the firmware asserts
2603 * @FW_DBG_TRIGGER_MISSED_BEACONS: trigger log collection when beacons are
2604 * missed.
2605 * @FW_DBG_TRIGGER_CHANNEL_SWITCH: trigger log collection upon channel switch.
2606 * @FW_DBG_TRIGGER_FW_NOTIF: trigger log collection when the firmware sends a
2607 * command response or a notification.
2608 * @FW_DBG_TRIGGER_MLME: trigger log collection upon MLME event.
2609 * @FW_DBG_TRIGGER_STATS: trigger log collection upon statistics threshold.
2610 * @FW_DBG_TRIGGER_RSSI: trigger log collection when the rssi of the beacon
2611 * goes below a threshold.
2612 * @FW_DBG_TRIGGER_TXQ_TIMERS: configures the timers for the Tx queue hang
2613 * detection.
2614 * @FW_DBG_TRIGGER_TIME_EVENT: trigger log collection upon time events related
2615 * events.
2616 * @FW_DBG_TRIGGER_BA: trigger log collection upon BlockAck related events.
2617 * @FW_DBG_TX_LATENCY: trigger log collection when the tx latency goes above a
2618 * threshold.
2619 * @FW_DBG_TDLS: trigger log collection upon TDLS related events.
2620 * @FW_DBG_TRIGGER_TX_STATUS: trigger log collection upon tx status when
2621 * the firmware sends a tx reply.
2622 * @FW_DBG_TRIGGER_USER_EXTENDED: trigger log collection upon user space
2623 * request.
2624 * @FW_DBG_TRIGGER_ALIVE_TIMEOUT: trigger log collection if alive flow timeouts
2625 * @FW_DBG_TRIGGER_DRIVER: trigger log collection upon a flow failure
2626 * in the driver.
2627 */
2628 enum iwx_fw_dbg_trigger {
2629 IWX_FW_DBG_TRIGGER_INVALID = 0,
2630 IWX_FW_DBG_TRIGGER_USER,
2631 IWX_FW_DBG_TRIGGER_FW_ASSERT,
2632 IWX_FW_DBG_TRIGGER_MISSED_BEACONS,
2633 IWX_FW_DBG_TRIGGER_CHANNEL_SWITCH,
2634 IWX_FW_DBG_TRIGGER_FW_NOTIF,
2635 IWX_FW_DBG_TRIGGER_MLME,
2636 IWX_FW_DBG_TRIGGER_STATS,
2637 IWX_FW_DBG_TRIGGER_RSSI,
2638 IWX_FW_DBG_TRIGGER_TXQ_TIMERS,
2639 IWX_FW_DBG_TRIGGER_TIME_EVENT,
2640 IWX_FW_DBG_TRIGGER_BA,
2641 IWX_FW_DBG_TRIGGER_TX_LATENCY,
2642 IWX_FW_DBG_TRIGGER_TDLS,
2643 IWX_FW_DBG_TRIGGER_TX_STATUS,
2644 IWX_FW_DBG_TRIGGER_USER_EXTENDED,
2645 IWX_FW_DBG_TRIGGER_ALIVE_TIMEOUT,
2646 IWX_FW_DBG_TRIGGER_DRIVER,
2647
2648 /* must be last */
2649 IWX_FW_DBG_TRIGGER_MAX,
2650 };
2651
2652
2653 /**
2654 * struct iwx_fw_dbg_trigger_tlv - a TLV that describes the trigger
2655 * @id: &enum iwx_fw_dbg_trigger
2656 * @vif_type: &enum iwx_fw_dbg_trigger_vif_type
2657 * @stop_conf_ids: bitmap of configurations this trigger relates to.
2658 * if the mode is %IWX_FW_DBG_TRIGGER_STOP, then if the bit corresponding
2659 * to the currently running configuration is set, the data should be
2660 * collected.
2661 * @stop_delay: how many milliseconds to wait before collecting the data
2662 * after the STOP trigger fires.
2663 * @mode: &enum iwx_fw_dbg_trigger_mode - can be stop / start of both
2664 * @start_conf_id: if mode is %IWX_FW_DBG_TRIGGER_START, this defines what
2665 * configuration should be applied when the triggers kicks in.
2666 * @occurrences: number of occurrences. 0 means the trigger will never fire.
2667 * @trig_dis_ms: the time, in milliseconds, after an occurrence of this
2668 * trigger in which another occurrence should be ignored.
2669 * @flags: &enum iwx_fw_dbg_trigger_flags
2670 */
2671 struct iwx_fw_dbg_trigger_tlv {
2672 uint32_t id;
2673 uint32_t vif_type;
2674 uint32_t stop_conf_ids;
2675 uint32_t stop_delay;
2676 uint8_t mode;
2677 uint8_t start_conf_id;
2678 uint16_t occurrences;
2679 uint16_t trig_dis_ms;
2680 uint8_t flags;
2681 uint8_t reserved[5];
2682
2683 uint8_t data[0];
2684 } __packed;
2685
2686 #define IWX_FW_DBG_START_FROM_ALIVE 0
2687 #define IWX_FW_DBG_CONF_MAX 32
2688 #define IWX_FW_DBG_INVALID 0xff
2689
2690 /**
2691 * struct iwx_fw_dbg_trigger_missed_bcon - configures trigger for missed beacons
2692 * @stop_consec_missed_bcon: stop recording if threshold is crossed.
2693 * @stop_consec_missed_bcon_since_rx: stop recording if threshold is crossed.
2694 * @start_consec_missed_bcon: start recording if threshold is crossed.
2695 * @start_consec_missed_bcon_since_rx: start recording if threshold is crossed.
2696 * @reserved1: reserved
2697 * @reserved2: reserved
2698 */
2699 struct iwx_fw_dbg_trigger_missed_bcon {
2700 uint32_t stop_consec_missed_bcon;
2701 uint32_t stop_consec_missed_bcon_since_rx;
2702 uint32_t reserved2[2];
2703 uint32_t start_consec_missed_bcon;
2704 uint32_t start_consec_missed_bcon_since_rx;
2705 uint32_t reserved1[2];
2706 } __packed;
2707
2708 /**
2709 * struct iwx_fw_dbg_trigger_cmd - configures trigger for messages from FW.
2710 * cmds: the list of commands to trigger the collection on
2711 */
2712 struct iwx_fw_dbg_trigger_cmd {
2713 struct cmd {
2714 uint8_t cmd_id;
2715 uint8_t group_id;
2716 } __packed cmds[16];
2717 } __packed;
2718
2719 /**
2720 * iwx_fw_dbg_trigger_stats - configures trigger for statistics
2721 * @stop_offset: the offset of the value to be monitored
2722 * @stop_threshold: the threshold above which to collect
2723 * @start_offset: the offset of the value to be monitored
2724 * @start_threshold: the threshold above which to start recording
2725 */
2726 struct iwx_fw_dbg_trigger_stats {
2727 uint32_t stop_offset;
2728 uint32_t stop_threshold;
2729 uint32_t start_offset;
2730 uint32_t start_threshold;
2731 } __packed;
2732
2733 /**
2734 * struct iwx_fw_dbg_trigger_low_rssi - trigger for low beacon RSSI
2735 * @rssi: RSSI value to trigger at
2736 */
2737 struct iwx_fw_dbg_trigger_low_rssi {
2738 uint32_t rssi;
2739 } __packed;
2740
2741 /**
2742 * struct iwx_fw_dbg_trigger_mlme - configures trigger for mlme events
2743 * @stop_auth_denied: number of denied authentication to collect
2744 * @stop_auth_timeout: number of authentication timeout to collect
2745 * @stop_rx_deauth: number of Rx deauth before to collect
2746 * @stop_tx_deauth: number of Tx deauth before to collect
2747 * @stop_assoc_denied: number of denied association to collect
2748 * @stop_assoc_timeout: number of association timeout to collect
2749 * @stop_connection_loss: number of connection loss to collect
2750 * @start_auth_denied: number of denied authentication to start recording
2751 * @start_auth_timeout: number of authentication timeout to start recording
2752 * @start_rx_deauth: number of Rx deauth to start recording
2753 * @start_tx_deauth: number of Tx deauth to start recording
2754 * @start_assoc_denied: number of denied association to start recording
2755 * @start_assoc_timeout: number of association timeout to start recording
2756 * @start_connection_loss: number of connection loss to start recording
2757 */
2758 struct iwx_fw_dbg_trigger_mlme {
2759 uint8_t stop_auth_denied;
2760 uint8_t stop_auth_timeout;
2761 uint8_t stop_rx_deauth;
2762 uint8_t stop_tx_deauth;
2763
2764 uint8_t stop_assoc_denied;
2765 uint8_t stop_assoc_timeout;
2766 uint8_t stop_connection_loss;
2767 uint8_t reserved;
2768
2769 uint8_t start_auth_denied;
2770 uint8_t start_auth_timeout;
2771 uint8_t start_rx_deauth;
2772 uint8_t start_tx_deauth;
2773
2774 uint8_t start_assoc_denied;
2775 uint8_t start_assoc_timeout;
2776 uint8_t start_connection_loss;
2777 uint8_t reserved2;
2778 } __packed;
2779
2780 /**
2781 * struct iwx_fw_dbg_trigger_txq_timer - configures the Tx queue's timer
2782 * @command_queue: timeout for the command queue in ms
2783 * @bss: timeout for the queues of a BSS (except for TDLS queues) in ms
2784 * @softap: timeout for the queues of a softAP in ms
2785 * @p2p_go: timeout for the queues of a P2P GO in ms
2786 * @p2p_client: timeout for the queues of a P2P client in ms
2787 * @p2p_device: timeout for the queues of a P2P device in ms
2788 * @ibss: timeout for the queues of an IBSS in ms
2789 * @tdls: timeout for the queues of a TDLS station in ms
2790 */
2791 struct iwx_fw_dbg_trigger_txq_timer {
2792 uint32_t command_queue;
2793 uint32_t bss;
2794 uint32_t softap;
2795 uint32_t p2p_go;
2796 uint32_t p2p_client;
2797 uint32_t p2p_device;
2798 uint32_t ibss;
2799 uint32_t tdls;
2800 uint32_t reserved[4];
2801 } __packed;
2802
2803 /**
2804 * struct iwx_fw_dbg_trigger_time_event - configures a time event trigger
2805 * time_Events: a list of tuples <id, action_bitmap>. The driver will issue a
2806 * trigger each time a time event notification that relates to time event
2807 * id with one of the actions in the bitmap is received and
2808 * BIT(notif->status) is set in status_bitmap.
2809 *
2810 */
2811 struct iwx_fw_dbg_trigger_time_event {
2812 struct {
2813 uint32_t id;
2814 uint32_t action_bitmap;
2815 uint32_t status_bitmap;
2816 } __packed time_events[16];
2817 } __packed;
2818
2819 /**
2820 * struct iwx_fw_dbg_trigger_ba - configures BlockAck related trigger
2821 * rx_ba_start: tid bitmap to configure on what tid the trigger should occur
2822 * when an Rx BlockAck session is started.
2823 * rx_ba_stop: tid bitmap to configure on what tid the trigger should occur
2824 * when an Rx BlockAck session is stopped.
2825 * tx_ba_start: tid bitmap to configure on what tid the trigger should occur
2826 * when a Tx BlockAck session is started.
2827 * tx_ba_stop: tid bitmap to configure on what tid the trigger should occur
2828 * when a Tx BlockAck session is stopped.
2829 * rx_bar: tid bitmap to configure on what tid the trigger should occur
2830 * when a BAR is received (for a Tx BlockAck session).
2831 * tx_bar: tid bitmap to configure on what tid the trigger should occur
2832 * when a BAR is send (for an Rx BlocAck session).
2833 * frame_timeout: tid bitmap to configure on what tid the trigger should occur
2834 * when a frame times out in the reordering buffer.
2835 */
2836 struct iwx_fw_dbg_trigger_ba {
2837 uint16_t rx_ba_start;
2838 uint16_t rx_ba_stop;
2839 uint16_t tx_ba_start;
2840 uint16_t tx_ba_stop;
2841 uint16_t rx_bar;
2842 uint16_t tx_bar;
2843 uint16_t frame_timeout;
2844 } __packed;
2845
2846 /**
2847 * struct iwx_fw_dbg_trigger_tx_latency - configures tx latency related trigger
2848 * @thrshold: the wanted threshold.
2849 * @tid_bitmap: the tid to apply the threshold on
2850 * @mode: recording mode (Internal buffer or continues recording)
2851 * @window: the size of the window before collecting.
2852 * @reserved: reserved.
2853 */
2854 struct iwx_fw_dbg_trigger_tx_latency {
2855 uint32_t thrshold;
2856 uint16_t tid_bitmap;
2857 uint16_t mode;
2858 uint32_t window;
2859 uint32_t reserved[4];
2860 } __packed;
2861
2862 /**
2863 * struct iwx_fw_dbg_trigger_tdls - configures trigger for TDLS events.
2864 * @action_bitmap: the TDLS action to trigger the collection upon
2865 * @peer_mode: trigger on specific peer or all
2866 * @peer: the TDLS peer to trigger the collection on
2867 */
2868 struct iwx_fw_dbg_trigger_tdls {
2869 uint8_t action_bitmap;
2870 uint8_t peer_mode;
2871 uint8_t peer[ETHER_ADDR_LEN];
2872 uint8_t reserved[4];
2873 } __packed;
2874
2875 /**
2876 * struct iwx_fw_dbg_trigger_tx_status - configures trigger for tx response
2877 * status.
2878 * @statuses: the list of statuses to trigger the collection on
2879 */
2880 struct iwx_fw_dbg_trigger_tx_status {
2881 struct tx_status {
2882 uint8_t status;
2883 uint8_t reserved[3];
2884 } __packed statuses[16];
2885 uint32_t reserved[2];
2886 } __packed;
2887
2888 /**
2889 * struct iwx_fw_dbg_conf_tlv - a TLV that describes a debug configuration.
2890 * @id: conf id
2891 * @usniffer: should the uSniffer image be used
2892 * @num_of_hcmds: how many HCMDs to send are present here
2893 * @hcmd: a variable length host command to be sent to apply the configuration.
2894 * If there is more than one HCMD to send, they will appear one after the
2895 * other and be sent in the order that they appear in.
2896 * This parses IWX_UCODE_TLV_FW_DBG_CONF. The user can add up-to
2897 * %IWX_FW_DBG_CONF_MAX configuration per run.
2898 */
2899 struct iwx_fw_dbg_conf_tlv {
2900 uint8_t id;
2901 uint8_t usniffer;
2902 uint8_t reserved;
2903 uint8_t num_of_hcmds;
2904 struct iwx_fw_dbg_conf_hcmd hcmd;
2905 } __packed;
2906
2907 #define IWX_FW_CMD_VER_UNKNOWN 99
2908
2909 /**
2910 * struct iwx_fw_cmd_version - firmware command version entry
2911 * @cmd: command ID
2912 * @group: group ID
2913 * @cmd_ver: command version
2914 * @notif_ver: notification version
2915 */
2916 struct iwx_fw_cmd_version {
2917 uint8_t cmd;
2918 uint8_t group;
2919 uint8_t cmd_ver;
2920 uint8_t notif_ver;
2921 } __packed;
2922
2923 /* Common PHY, MAC and Bindings definitions */
2924
2925 #define IWX_MAX_MACS_IN_BINDING (3)
2926 #define IWX_MAX_BINDINGS (4)
2927 #define IWX_AUX_BINDING_INDEX (3)
2928 #define IWX_MAX_PHYS (4)
2929
2930 /* Used to extract ID and color from the context dword */
2931 #define IWX_FW_CTXT_ID_POS (0)
2932 #define IWX_FW_CTXT_ID_MSK (0xff << IWX_FW_CTXT_ID_POS)
2933 #define IWX_FW_CTXT_COLOR_POS (8)
2934 #define IWX_FW_CTXT_COLOR_MSK (0xff << IWX_FW_CTXT_COLOR_POS)
2935 #define IWX_FW_CTXT_INVALID (0xffffffff)
2936
2937 #define IWX_FW_CMD_ID_AND_COLOR(_id, _color) ((_id << IWX_FW_CTXT_ID_POS) |\
2938 (_color << IWX_FW_CTXT_COLOR_POS))
2939
2940 /* Possible actions on PHYs, MACs and Bindings */
2941 #define IWX_FW_CTXT_ACTION_STUB 0
2942 #define IWX_FW_CTXT_ACTION_ADD 1
2943 #define IWX_FW_CTXT_ACTION_MODIFY 2
2944 #define IWX_FW_CTXT_ACTION_REMOVE 3
2945 #define IWX_FW_CTXT_ACTION_NUM 4
2946 /* COMMON_CONTEXT_ACTION_API_E_VER_1 */
2947
2948 /* Time Events */
2949
2950 /* Time Event types, according to MAC type */
2951
2952 /* BSS Station Events */
2953 #define IWX_TE_BSS_STA_AGGRESSIVE_ASSOC 0
2954 #define IWX_TE_BSS_STA_ASSOC 1
2955 #define IWX_TE_BSS_EAP_DHCP_PROT 2
2956 #define IWX_TE_BSS_QUIET_PERIOD 3
2957
2958 /* P2P Device Events */
2959 #define IWX_TE_P2P_DEVICE_DISCOVERABLE 4
2960 #define IWX_TE_P2P_DEVICE_LISTEN 5
2961 #define IWX_TE_P2P_DEVICE_ACTION_SCAN 6
2962 #define IWX_TE_P2P_DEVICE_FULL_SCAN 7
2963
2964 /* P2P Client Events */
2965 #define IWX_TE_P2P_CLIENT_AGGRESSIVE_ASSOC 8
2966 #define IWX_TE_P2P_CLIENT_ASSOC 9
2967 #define IWX_TE_P2P_CLIENT_QUIET_PERIOD 10
2968
2969 /* P2P GO Events */
2970 #define IWX_TE_P2P_GO_ASSOC_PROT 11
2971 #define IWX_TE_P2P_GO_REPETITIVE_NOA 12
2972 #define IWX_TE_P2P_GO_CT_WINDOW 13
2973
2974 /* WiDi Sync Events */
2975 #define IWX_TE_WIDI_TX_SYNC 14
2976
2977 /* Time event - defines for command API */
2978
2979 /**
2980 * DOC: Time Events - what is it?
2981 *
2982 * Time Events are a fw feature that allows the driver to control the presence
2983 * of the device on the channel. Since the fw supports multiple channels
2984 * concurrently, the fw may choose to jump to another channel at any time.
2985 * In order to make sure that the fw is on a specific channel at a certain time
2986 * and for a certain duration, the driver needs to issue a time event.
2987 *
2988 * The simplest example is for BSS association. The driver issues a time event,
2989 * waits for it to start, and only then tells mac80211 that we can start the
2990 * association. This way, we make sure that the association will be done
2991 * smoothly and won't be interrupted by channel switch decided within the fw.
2992 */
2993
2994 /**
2995 * DOC: The flow against the fw
2996 *
2997 * When the driver needs to make sure we are in a certain channel, at a certain
2998 * time and for a certain duration, it sends a Time Event. The flow against the
2999 * fw goes like this:
3000 * 1) Driver sends a TIME_EVENT_CMD to the fw
3001 * 2) Driver gets the response for that command. This response contains the
3002 * Unique ID (UID) of the event.
3003 * 3) The fw sends notification when the event starts.
3004 *
3005 * Of course the API provides various options that allow to cover parameters
3006 * of the flow.
3007 * What is the duration of the event?
3008 * What is the start time of the event?
3009 * Is there an end-time for the event?
3010 * How much can the event be delayed?
3011 * Can the event be split?
3012 * If yes what is the maximal number of chunks?
3013 * etc...
3014 */
3015
3016 /*
3017 * @IWX_TE_V2_FRAG_NONE: fragmentation of the time event is NOT allowed.
3018 * @IWX_TE_V2_FRAG_SINGLE: fragmentation of the time event is allowed, but only
3019 * the first fragment is scheduled.
3020 * @IWX_TE_V2_FRAG_DUAL: fragmentation of the time event is allowed, but only
3021 * the first 2 fragments are scheduled.
3022 * @IWX_TE_V2_FRAG_ENDLESS: fragmentation of the time event is allowed, and any
3023 * number of fragments are valid.
3024 *
3025 * Other than the constant defined above, specifying a fragmentation value 'x'
3026 * means that the event can be fragmented but only the first 'x' will be
3027 * scheduled.
3028 */
3029 #define IWX_TE_V2_FRAG_NONE 0
3030 #define IWX_TE_V2_FRAG_SINGLE 1
3031 #define IWX_TE_V2_FRAG_DUAL 2
3032 #define IWX_TE_V2_FRAG_MAX 0xfe
3033 #define IWX_TE_V2_FRAG_ENDLESS 0xff
3034
3035 /* Repeat the time event endlessly (until removed) */
3036 #define IWX_TE_V2_REPEAT_ENDLESS 0xff
3037 /* If a Time Event has bounded repetitions, this is the maximal value */
3038 #define IWX_TE_V2_REPEAT_MAX 0xfe
3039
3040 #define IWX_TE_V2_PLACEMENT_POS 12
3041 #define IWX_TE_V2_ABSENCE_POS 15
3042
3043 /* Time event policy values
3044 * A notification (both event and fragment) includes a status indicating weather
3045 * the FW was able to schedule the event or not. For fragment start/end
3046 * notification the status is always success. There is no start/end fragment
3047 * notification for monolithic events.
3048 *
3049 * @IWX_TE_V2_DEFAULT_POLICY: independent, social, present, unoticable
3050 * @IWX_TE_V2_NOTIF_HOST_EVENT_START: request/receive notification on event start
3051 * @IWX_TE_V2_NOTIF_HOST_EVENT_END:request/receive notification on event end
3052 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_START: internal FW use
3053 * @IWX_TE_V2_NOTIF_INTERNAL_EVENT_END: internal FW use.
3054 * @IWX_TE_V2_NOTIF_HOST_FRAG_START: request/receive notification on frag start
3055 * @IWX_TE_V2_NOTIF_HOST_FRAG_END:request/receive notification on frag end
3056 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_START: internal FW use.
3057 * @IWX_TE_V2_NOTIF_INTERNAL_FRAG_END: internal FW use.
3058 * @IWX_TE_V2_DEP_OTHER: depends on another time event
3059 * @IWX_TE_V2_DEP_TSF: depends on a specific time
3060 * @IWX_TE_V2_EVENT_SOCIOPATHIC: can't co-exist with other events of the same MAC
3061 * @IWX_TE_V2_ABSENCE: are we present or absent during the Time Event.
3062 */
3063 #define IWX_TE_V2_DEFAULT_POLICY 0x0
3064
3065 /* notifications (event start/stop, fragment start/stop) */
3066 #define IWX_TE_V2_NOTIF_HOST_EVENT_START (1 << 0)
3067 #define IWX_TE_V2_NOTIF_HOST_EVENT_END (1 << 1)
3068 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_START (1 << 2)
3069 #define IWX_TE_V2_NOTIF_INTERNAL_EVENT_END (1 << 3)
3070
3071 #define IWX_TE_V2_NOTIF_HOST_FRAG_START (1 << 4)
3072 #define IWX_TE_V2_NOTIF_HOST_FRAG_END (1 << 5)
3073 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_START (1 << 6)
3074 #define IWX_TE_V2_NOTIF_INTERNAL_FRAG_END (1 << 7)
3075 #define IWX_T2_V2_START_IMMEDIATELY (1 << 11)
3076
3077 #define IWX_TE_V2_NOTIF_MSK 0xff
3078
3079 /* placement characteristics */
3080 #define IWX_TE_V2_DEP_OTHER (1 << IWX_TE_V2_PLACEMENT_POS)
3081 #define IWX_TE_V2_DEP_TSF (1 << (IWX_TE_V2_PLACEMENT_POS + 1))
3082 #define IWX_TE_V2_EVENT_SOCIOPATHIC (1 << (IWX_TE_V2_PLACEMENT_POS + 2))
3083
3084 /* are we present or absent during the Time Event. */
3085 #define IWX_TE_V2_ABSENCE (1 << IWX_TE_V2_ABSENCE_POS)
3086
3087 /**
3088 * struct iwx_time_event_cmd_api - configuring Time Events
3089 * with struct IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 (see also
3090 * with version 1. determined by IWX_UCODE_TLV_FLAGS)
3091 * ( IWX_TIME_EVENT_CMD = 0x29 )
3092 * @id_and_color: ID and color of the relevant MAC
3093 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
3094 * @id: this field has two meanings, depending on the action:
3095 * If the action is ADD, then it means the type of event to add.
3096 * For all other actions it is the unique event ID assigned when the
3097 * event was added by the FW.
3098 * @apply_time: When to start the Time Event (in GP2)
3099 * @max_delay: maximum delay to event's start (apply time), in TU
3100 * @depends_on: the unique ID of the event we depend on (if any)
3101 * @interval: interval between repetitions, in TU
3102 * @duration: duration of event in TU
3103 * @repeat: how many repetitions to do, can be IWX_TE_REPEAT_ENDLESS
3104 * @max_frags: maximal number of fragments the Time Event can be divided to
3105 * @policy: defines whether uCode shall notify the host or other uCode modules
3106 * on event and/or fragment start and/or end
3107 * using one of IWX_TE_INDEPENDENT, IWX_TE_DEP_OTHER, IWX_TE_DEP_TSF
3108 * IWX_TE_EVENT_SOCIOPATHIC
3109 * using IWX_TE_ABSENCE and using IWX_TE_NOTIF_*
3110 */
3111 struct iwx_time_event_cmd {
3112 /* COMMON_INDEX_HDR_API_S_VER_1 */
3113 uint32_t id_and_color;
3114 uint32_t action;
3115 uint32_t id;
3116 /* IWX_MAC_TIME_EVENT_DATA_API_S_VER_2 */
3117 uint32_t apply_time;
3118 uint32_t max_delay;
3119 uint32_t depends_on;
3120 uint32_t interval;
3121 uint32_t duration;
3122 uint8_t repeat;
3123 uint8_t max_frags;
3124 uint16_t policy;
3125 } __packed; /* IWX_MAC_TIME_EVENT_CMD_API_S_VER_2 */
3126
3127 /**
3128 * struct iwx_time_event_resp - response structure to iwx_time_event_cmd
3129 * @status: bit 0 indicates success, all others specify errors
3130 * @id: the Time Event type
3131 * @unique_id: the unique ID assigned (in ADD) or given (others) to the TE
3132 * @id_and_color: ID and color of the relevant MAC
3133 */
3134 struct iwx_time_event_resp {
3135 uint32_t status;
3136 uint32_t id;
3137 uint32_t unique_id;
3138 uint32_t id_and_color;
3139 } __packed; /* IWX_MAC_TIME_EVENT_RSP_API_S_VER_1 */
3140
3141 /**
3142 * struct iwx_time_event_notif - notifications of time event start/stop
3143 * ( IWX_TIME_EVENT_NOTIFICATION = 0x2a )
3144 * @timestamp: action timestamp in GP2
3145 * @session_id: session's unique id
3146 * @unique_id: unique id of the Time Event itself
3147 * @id_and_color: ID and color of the relevant MAC
3148 * @action: one of IWX_TE_NOTIF_START or IWX_TE_NOTIF_END
3149 * @status: true if scheduled, false otherwise (not executed)
3150 */
3151 struct iwx_time_event_notif {
3152 uint32_t timestamp;
3153 uint32_t session_id;
3154 uint32_t unique_id;
3155 uint32_t id_and_color;
3156 uint32_t action;
3157 uint32_t status;
3158 } __packed; /* IWX_MAC_TIME_EVENT_NTFY_API_S_VER_1 */
3159
3160 /**
3161 * enum iwx_session_prot_conf_id - session protection's configurations
3162 * @SESSION_PROTECT_CONF_ASSOC: Start a session protection for association.
3163 * The firmware will allocate two events.
3164 * Valid for BSS_STA and P2P_STA.
3165 * * A rather short event that can't be fragmented and with a very
3166 * high priority. If every goes well (99% of the cases) the
3167 * association should complete within this first event. During
3168 * that event, no other activity will happen in the firmware,
3169 * which is why it can't be too long.
3170 * The length of this event is hard-coded in the firmware: 300TUs.
3171 * * Another event which can be much longer (its duration is
3172 * configurable by the driver) which has a slightly lower
3173 * priority and that can be fragmented allowing other activities
3174 * to run while this event is running.
3175 * The firmware will automatically remove both events once the driver sets
3176 * the BSS MAC as associated. Neither of the events will be removed
3177 * for the P2P_STA MAC.
3178 * Only the duration is configurable for this protection.
3179 * @SESSION_PROTECT_CONF_GO_CLIENT_ASSOC: not used
3180 * @SESSION_PROTECT_CONF_P2P_DEVICE_DISCOV: Schedule the P2P Device to be in
3181 * listen mode. Will be fragmented. Valid only on the P2P Device MAC.
3182 * Valid only on the P2P Device MAC. The firmware will take into account
3183 * the duration, the interval and the repetition count.
3184 * @SESSION_PROTECT_CONF_P2P_GO_NEGOTIATION: Schedule the P2P Device to be be
3185 * able to run the GO Negotiation. Will not be fragmented and not
3186 * repetitive. Valid only on the P2P Device MAC. Only the duration will
3187 * be taken into account.
3188 * @SESSION_PROTECT_CONF_MAX_ID: not used
3189 */
3190 enum iwx_session_prot_conf_id {
3191 IWX_SESSION_PROTECT_CONF_ASSOC,
3192 IWX_SESSION_PROTECT_CONF_GO_CLIENT_ASSOC,
3193 IWX_SESSION_PROTECT_CONF_P2P_DEVICE_DISCOV,
3194 IWX_SESSION_PROTECT_CONF_P2P_GO_NEGOTIATION,
3195 IWX_SESSION_PROTECT_CONF_MAX_ID,
3196 }; /* SESSION_PROTECTION_CONF_ID_E_VER_1 */
3197
3198 /**
3199 * struct iwx_session_prot_cmd - configure a session protection
3200 * @id_and_color: the id and color of the mac for which this session protection
3201 * is sent
3202 * @action: can be either FW_CTXT_ACTION_ADD or FW_CTXT_ACTION_REMOVE
3203 * @conf_id: see &enum iwx_mvm_session_prot_conf_id
3204 * @duration_tu: the duration of the whole protection in TUs.
3205 * @repetition_count: not used
3206 * @interval: not used
3207 *
3208 * Note: the session protection will always be scheduled to start as
3209 * early as possible, but the maximum delay is configuration dependent.
3210 * The firmware supports only one concurrent session protection per vif.
3211 * Adding a new session protection will remove any currently running session.
3212 */
3213 struct iwx_session_prot_cmd {
3214 /* COMMON_INDEX_HDR_API_S_VER_1 hdr */
3215 uint32_t id_and_color;
3216 uint32_t action;
3217 uint32_t conf_id;
3218 uint32_t duration_tu;
3219 uint32_t repetition_count;
3220 uint32_t interval;
3221 } __packed; /* SESSION_PROTECTION_CMD_API_S_VER_1 */
3222
3223 /**
3224 * struct iwx_session_prot_notif - session protection started / ended
3225 * @mac_id: the mac id for which the session protection started / ended
3226 * @status: 1 means success, 0 means failure
3227 * @start: 1 means the session protection started, 0 means it ended
3228 * @conf_id: see &enum iwx_mvm_session_prot_conf_id
3229 *
3230 * Note that any session protection will always get two notifications: start
3231 * and end even the firmware could not schedule it.
3232 */
3233 struct iwx_session_prot_notif {
3234 uint32_t mac_id;
3235 uint32_t status;
3236 uint32_t start;
3237 uint32_t conf_id;
3238 } __packed; /* SESSION_PROTECTION_NOTIFICATION_API_S_VER_2 */
3239
3240
3241 /* Bindings and Time Quota */
3242
3243 /**
3244 * struct iwx_binding_cmd - configuring bindings
3245 * ( IWX_BINDING_CONTEXT_CMD = 0x2b )
3246 * @id_and_color: ID and color of the relevant Binding
3247 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
3248 * @macs: array of MAC id and colors which belong to the binding
3249 * @phy: PHY id and color which belongs to the binding
3250 * @lmac_id: the lmac id the binding belongs to
3251 */
3252 struct iwx_binding_cmd {
3253 /* COMMON_INDEX_HDR_API_S_VER_1 */
3254 uint32_t id_and_color;
3255 uint32_t action;
3256 /* IWX_BINDING_DATA_API_S_VER_1 */
3257 uint32_t macs[IWX_MAX_MACS_IN_BINDING];
3258 uint32_t phy;
3259 uint32_t lmac_id;
3260 } __packed; /* IWX_BINDING_CMD_API_S_VER_2 */
3261
3262 #define IWX_LMAC_24G_INDEX 0
3263 #define IWX_LMAC_5G_INDEX 1
3264
3265 /* The maximal number of fragments in the FW's schedule session */
3266 #define IWX_MAX_QUOTA 128
3267
3268 /**
3269 * struct iwx_time_quota_data - configuration of time quota per binding
3270 * @id_and_color: ID and color of the relevant Binding
3271 * @quota: absolute time quota in TU. The scheduler will try to divide the
3272 * remaining quota (after Time Events) according to this quota.
3273 * @max_duration: max uninterrupted context duration in TU
3274 */
3275 struct iwx_time_quota_data {
3276 uint32_t id_and_color;
3277 uint32_t quota;
3278 uint32_t max_duration;
3279 } __packed; /* IWX_TIME_QUOTA_DATA_API_S_VER_1 */
3280
3281 /**
3282 * struct iwx_time_quota_cmd - configuration of time quota between bindings
3283 * ( IWX_TIME_QUOTA_CMD = 0x2c )
3284 * @quotas: allocations per binding
3285 */
3286 struct iwx_time_quota_cmd {
3287 struct iwx_time_quota_data quotas[IWX_MAX_BINDINGS];
3288 } __packed; /* IWX_TIME_QUOTA_ALLOCATION_CMD_API_S_VER_1 */
3289
3290
3291 /* PHY context */
3292
3293 /* Supported bands */
3294 #define IWX_PHY_BAND_5 (0)
3295 #define IWX_PHY_BAND_24 (1)
3296
3297 /* Supported channel width, vary if there is VHT support */
3298 #define IWX_PHY_VHT_CHANNEL_MODE20 (0x0)
3299 #define IWX_PHY_VHT_CHANNEL_MODE40 (0x1)
3300 #define IWX_PHY_VHT_CHANNEL_MODE80 (0x2)
3301 #define IWX_PHY_VHT_CHANNEL_MODE160 (0x3)
3302
3303 /*
3304 * Control channel position:
3305 * For legacy set bit means upper channel, otherwise lower.
3306 * For VHT - bit-2 marks if the control is lower/upper relative to center-freq
3307 * bits-1:0 mark the distance from the center freq. for 20Mhz, offset is 0.
3308 * center_freq
3309 * |
3310 * 40Mhz |_______|_______|
3311 * 80Mhz |_______|_______|_______|_______|
3312 * 160Mhz |_______|_______|_______|_______|_______|_______|_______|_______|
3313 * code 011 010 001 000 | 100 101 110 111
3314 */
3315 #define IWX_PHY_VHT_CTRL_POS_1_BELOW (0x0)
3316 #define IWX_PHY_VHT_CTRL_POS_2_BELOW (0x1)
3317 #define IWX_PHY_VHT_CTRL_POS_3_BELOW (0x2)
3318 #define IWX_PHY_VHT_CTRL_POS_4_BELOW (0x3)
3319 #define IWX_PHY_VHT_CTRL_POS_1_ABOVE (0x4)
3320 #define IWX_PHY_VHT_CTRL_POS_2_ABOVE (0x5)
3321 #define IWX_PHY_VHT_CTRL_POS_3_ABOVE (0x6)
3322 #define IWX_PHY_VHT_CTRL_POS_4_ABOVE (0x7)
3323
3324 /*
3325 * @band: IWX_PHY_BAND_*
3326 * @channel: channel number
3327 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
3328 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
3329 */
3330 struct iwx_fw_channel_info_v1 {
3331 uint8_t band;
3332 uint8_t channel;
3333 uint8_t width;
3334 uint8_t ctrl_pos;
3335 } __packed; /* CHANNEL_CONFIG_API_S_VER_1 */
3336
3337 /*
3338 * struct iwx_fw_channel_info - channel information
3339 *
3340 * @channel: channel number
3341 * @band: PHY_BAND_*
3342 * @width: PHY_[VHT|LEGACY]_CHANNEL_*
3343 * @ctrl channel: PHY_[VHT|LEGACY]_CTRL_*
3344 * @reserved: for future use and alignment
3345 */
3346 struct iwx_fw_channel_info {
3347 uint32_t channel;
3348 uint8_t band;
3349 uint8_t width;
3350 uint8_t ctrl_pos;
3351 uint8_t reserved;
3352 } __packed; /*CHANNEL_CONFIG_API_S_VER_2 */
3353
3354 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS (0)
3355 #define IWX_PHY_RX_CHAIN_DRIVER_FORCE_MSK \
3356 (0x1 << IWX_PHY_RX_CHAIN_DRIVER_FORCE_POS)
3357 #define IWX_PHY_RX_CHAIN_VALID_POS (1)
3358 #define IWX_PHY_RX_CHAIN_VALID_MSK \
3359 (0x7 << IWX_PHY_RX_CHAIN_VALID_POS)
3360 #define IWX_PHY_RX_CHAIN_FORCE_SEL_POS (4)
3361 #define IWX_PHY_RX_CHAIN_FORCE_SEL_MSK \
3362 (0x7 << IWX_PHY_RX_CHAIN_FORCE_SEL_POS)
3363 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
3364 #define IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_MSK \
3365 (0x7 << IWX_PHY_RX_CHAIN_FORCE_MIMO_SEL_POS)
3366 #define IWX_PHY_RX_CHAIN_CNT_POS (10)
3367 #define IWX_PHY_RX_CHAIN_CNT_MSK \
3368 (0x3 << IWX_PHY_RX_CHAIN_CNT_POS)
3369 #define IWX_PHY_RX_CHAIN_MIMO_CNT_POS (12)
3370 #define IWX_PHY_RX_CHAIN_MIMO_CNT_MSK \
3371 (0x3 << IWX_PHY_RX_CHAIN_MIMO_CNT_POS)
3372 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_POS (14)
3373 #define IWX_PHY_RX_CHAIN_MIMO_FORCE_MSK \
3374 (0x1 << IWX_PHY_RX_CHAIN_MIMO_FORCE_POS)
3375
3376 /* TODO: fix the value, make it depend on firmware at runtime? */
3377 #define IWX_NUM_PHY_CTX 3
3378
3379 /**
3380 * struct iwl_phy_context_cmd - config of the PHY context
3381 * ( IWX_PHY_CONTEXT_CMD = 0x8 )
3382 * @id_and_color: ID and color of the relevant Binding
3383 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
3384 * @lmac_id: the lmac id the phy context belongs to
3385 * @ci: channel info
3386 * @rxchain_info: ???
3387 * @dsp_cfg_flags: set to 0
3388 * @reserved: reserved to align to 64 bit
3389 */
3390 struct iwx_phy_context_cmd_uhb {
3391 /* COMMON_INDEX_HDR_API_S_VER_1 */
3392 uint32_t id_and_color;
3393 uint32_t action;
3394 /* PHY_CONTEXT_DATA_API_S_VER_3 */
3395 struct iwx_fw_channel_info ci;
3396 uint32_t lmac_id;
3397 uint32_t rxchain_info;
3398 uint32_t dsp_cfg_flags;
3399 uint32_t reserved;
3400 } __packed; /* PHY_CONTEXT_CMD_API_VER_3 */
3401 struct iwx_phy_context_cmd {
3402 /* COMMON_INDEX_HDR_API_S_VER_1 */
3403 uint32_t id_and_color;
3404 uint32_t action;
3405 /* PHY_CONTEXT_DATA_API_S_VER_3, PHY_CONTEXT_DATA_API_S_VER_4 */
3406 struct iwx_fw_channel_info_v1 ci;
3407 uint32_t lmac_id;
3408 uint32_t rxchain_info; /* reserved in _VER_4 */
3409 uint32_t dsp_cfg_flags;
3410 uint32_t reserved;
3411 } __packed; /* PHY_CONTEXT_CMD_API_VER_3, PHY_CONTEXT_CMD_API_VER_4 */
3412
3413 /* TODO: complete missing documentation */
3414 /**
3415 * struct iwx_phy_context_cmd - config of the PHY context
3416 * ( IWX_PHY_CONTEXT_CMD = 0x8 )
3417 * @id_and_color: ID and color of the relevant Binding
3418 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
3419 * @apply_time: 0 means immediate apply and context switch.
3420 * other value means apply new params after X usecs
3421 * @tx_param_color: ???
3422 * @channel_info:
3423 * @txchain_info: ???
3424 * @rxchain_info: ???
3425 * @acquisition_data: ???
3426 * @dsp_cfg_flags: set to 0
3427 */
3428 /*
3429 * XXX Intel forgot to bump the PHY_CONTEXT command API when they increased
3430 * the size of fw_channel_info from v1 to v2.
3431 * To keep things simple we define two versions of this struct, and both
3432 * are labeled as CMD_API_VER_1. (The Linux iwlwifi driver performs dark
3433 * magic with pointers to struct members instead.)
3434 */
3435 /* This version must be used if IWX_UCODE_TLV_CAPA_ULTRA_HB_CHANNELS is set: */
3436 struct iwx_phy_context_cmd_uhb_v1 {
3437 /* COMMON_INDEX_HDR_API_S_VER_1 */
3438 uint32_t id_and_color;
3439 uint32_t action;
3440 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */
3441 uint32_t apply_time;
3442 uint32_t tx_param_color;
3443 struct iwx_fw_channel_info ci;
3444 uint32_t txchain_info;
3445 uint32_t rxchain_info;
3446 uint32_t acquisition_data;
3447 uint32_t dsp_cfg_flags;
3448 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */
3449 /* This version must be used otherwise: */
3450 struct iwx_phy_context_cmd_v1 {
3451 /* COMMON_INDEX_HDR_API_S_VER_1 */
3452 uint32_t id_and_color;
3453 uint32_t action;
3454 /* IWX_PHY_CONTEXT_DATA_API_S_VER_1 */
3455 uint32_t apply_time;
3456 uint32_t tx_param_color;
3457 struct iwx_fw_channel_info_v1 ci;
3458 uint32_t txchain_info;
3459 uint32_t rxchain_info;
3460 uint32_t acquisition_data;
3461 uint32_t dsp_cfg_flags;
3462 } __packed; /* IWX_PHY_CONTEXT_CMD_API_VER_1 */
3463
3464
3465 #define IWX_RX_INFO_PHY_CNT 8
3466 #define IWX_RX_INFO_ENERGY_ANT_ABC_IDX 1
3467 #define IWX_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
3468 #define IWX_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
3469 #define IWX_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
3470 #define IWX_RX_INFO_ENERGY_ANT_A_POS 0
3471 #define IWX_RX_INFO_ENERGY_ANT_B_POS 8
3472 #define IWX_RX_INFO_ENERGY_ANT_C_POS 16
3473
3474 #define IWX_RX_INFO_AGC_IDX 1
3475 #define IWX_RX_INFO_RSSI_AB_IDX 2
3476 #define IWX_OFDM_AGC_A_MSK 0x0000007f
3477 #define IWX_OFDM_AGC_A_POS 0
3478 #define IWX_OFDM_AGC_B_MSK 0x00003f80
3479 #define IWX_OFDM_AGC_B_POS 7
3480 #define IWX_OFDM_AGC_CODE_MSK 0x3fe00000
3481 #define IWX_OFDM_AGC_CODE_POS 20
3482 #define IWX_OFDM_RSSI_INBAND_A_MSK 0x00ff
3483 #define IWX_OFDM_RSSI_A_POS 0
3484 #define IWX_OFDM_RSSI_ALLBAND_A_MSK 0xff00
3485 #define IWX_OFDM_RSSI_ALLBAND_A_POS 8
3486 #define IWX_OFDM_RSSI_INBAND_B_MSK 0xff0000
3487 #define IWX_OFDM_RSSI_B_POS 16
3488 #define IWX_OFDM_RSSI_ALLBAND_B_MSK 0xff000000
3489 #define IWX_OFDM_RSSI_ALLBAND_B_POS 24
3490
3491 /**
3492 * struct iwx_rx_phy_info - phy info
3493 * (IWX_REPLY_RX_PHY_CMD = 0xc0)
3494 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
3495 * @cfg_phy_cnt: configurable DSP phy data byte count
3496 * @stat_id: configurable DSP phy data set ID
3497 * @reserved1:
3498 * @system_timestamp: GP2 at on air rise
3499 * @timestamp: TSF at on air rise
3500 * @beacon_time_stamp: beacon at on-air rise
3501 * @phy_flags: general phy flags: band, modulation, ...
3502 * @channel: channel number
3503 * @non_cfg_phy_buf: for various implementations of non_cfg_phy
3504 * @rate_n_flags: IWX_RATE_MCS_*
3505 * @byte_count: frame's byte-count
3506 * @frame_time: frame's time on the air, based on byte count and frame rate
3507 * calculation
3508 * @mac_active_msk: what MACs were active when the frame was received
3509 *
3510 * Before each Rx, the device sends this data. It contains PHY information
3511 * about the reception of the packet.
3512 */
3513 struct iwx_rx_phy_info {
3514 uint8_t non_cfg_phy_cnt;
3515 uint8_t cfg_phy_cnt;
3516 uint8_t stat_id;
3517 uint8_t reserved1;
3518 uint32_t system_timestamp;
3519 uint64_t timestamp;
3520 uint32_t beacon_time_stamp;
3521 uint16_t phy_flags;
3522 #define IWX_PHY_INFO_FLAG_SHPREAMBLE (1 << 2)
3523 uint16_t channel;
3524 uint32_t non_cfg_phy[IWX_RX_INFO_PHY_CNT];
3525 uint32_t rate_n_flags;
3526 uint32_t byte_count;
3527 uint16_t mac_active_msk;
3528 uint16_t frame_time;
3529 } __packed;
3530
3531 struct iwx_rx_mpdu_res_start {
3532 uint16_t byte_count;
3533 uint16_t reserved;
3534 } __packed;
3535
3536 /**
3537 * Values to parse %iwx_rx_phy_info phy_flags
3538 * @IWX_RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
3539 * @IWX_RX_RES_PHY_FLAGS_MOD_CCK:
3540 * @IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
3541 * @IWX_RX_RES_PHY_FLAGS_NARROW_BAND:
3542 * @IWX_RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
3543 * @IWX_RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
3544 * @IWX_RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
3545 * @IWX_RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
3546 * @IWX_RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
3547 */
3548 #define IWX_RX_RES_PHY_FLAGS_BAND_24 (1 << 0)
3549 #define IWX_RX_RES_PHY_FLAGS_MOD_CCK (1 << 1)
3550 #define IWX_RX_RES_PHY_FLAGS_SHORT_PREAMBLE (1 << 2)
3551 #define IWX_RX_RES_PHY_FLAGS_NARROW_BAND (1 << 3)
3552 #define IWX_RX_RES_PHY_FLAGS_ANTENNA (0x7 << 4)
3553 #define IWX_RX_RES_PHY_FLAGS_ANTENNA_POS 4
3554 #define IWX_RX_RES_PHY_FLAGS_AGG (1 << 7)
3555 #define IWX_RX_RES_PHY_FLAGS_OFDM_HT (1 << 8)
3556 #define IWX_RX_RES_PHY_FLAGS_OFDM_GF (1 << 9)
3557 #define IWX_RX_RES_PHY_FLAGS_OFDM_VHT (1 << 10)
3558
3559 /**
3560 * Values written by fw for each Rx packet
3561 * @IWX_RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
3562 * @IWX_RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
3563 * @IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND:
3564 * @IWX_RX_MPDU_RES_STATUS_KEY_VALID:
3565 * @IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK:
3566 * @IWX_RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
3567 * @IWX_RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
3568 * in the driver.
3569 * @IWX_RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
3570 * @IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
3571 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
3572 * %IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
3573 * @IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
3574 * @IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
3575 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
3576 * @IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
3577 * @IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
3578 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
3579 * @IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
3580 * @IWX_RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
3581 * @IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP:
3582 * @IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP:
3583 * @IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT:
3584 * @IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
3585 * @IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK:
3586 * @IWX_RX_MPDU_RES_STATUS_STA_ID_MSK:
3587 * @IWX_RX_MPDU_RES_STATUS_RRF_KILL:
3588 * @IWX_RX_MPDU_RES_STATUS_FILTERING_MSK:
3589 * @IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK:
3590 */
3591 #define IWX_RX_MPDU_RES_STATUS_CRC_OK (1 << 0)
3592 #define IWX_RX_MPDU_RES_STATUS_OVERRUN_OK (1 << 1)
3593 #define IWX_RX_MPDU_RES_STATUS_SRC_STA_FOUND (1 << 2)
3594 #define IWX_RX_MPDU_RES_STATUS_KEY_VALID (1 << 3)
3595 #define IWX_RX_MPDU_RES_STATUS_KEY_PARAM_OK (1 << 4)
3596 #define IWX_RX_MPDU_RES_STATUS_ICV_OK (1 << 5)
3597 #define IWX_RX_MPDU_RES_STATUS_MIC_OK (1 << 6)
3598 #define IWX_RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
3599 #define IWX_RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR (1 << 7)
3600 #define IWX_RX_MPDU_RES_STATUS_SEC_NO_ENC (0 << 8)
3601 #define IWX_RX_MPDU_RES_STATUS_SEC_WEP_ENC (1 << 8)
3602 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_ENC (2 << 8)
3603 #define IWX_RX_MPDU_RES_STATUS_SEC_TKIP_ENC (3 << 8)
3604 #define IWX_RX_MPDU_RES_STATUS_SEC_EXT_ENC (4 << 8)
3605 #define IWX_RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC (6 << 8)
3606 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_ERR (7 << 8)
3607 #define IWX_RX_MPDU_RES_STATUS_SEC_ENC_MSK (7 << 8)
3608 #define IWX_RX_MPDU_RES_STATUS_DEC_DONE (1 << 11)
3609 #define IWX_RX_MPDU_RES_STATUS_PROTECT_FRAME_BIT_CMP (1 << 12)
3610 #define IWX_RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP (1 << 13)
3611 #define IWX_RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT (1 << 14)
3612 #define IWX_RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME (1 << 15)
3613 #define IWX_RX_MPDU_RES_STATUS_HASH_INDEX_MSK (0x3F0000)
3614 #define IWX_RX_MPDU_RES_STATUS_STA_ID_MSK (0x1f000000)
3615 #define IWX_RX_MPDU_RES_STATUS_RRF_KILL (1 << 29)
3616 #define IWX_RX_MPDU_RES_STATUS_FILTERING_MSK (0xc00000)
3617 #define IWX_RX_MPDU_RES_STATUS2_FILTERING_MSK (0xc0000000)
3618
3619 #define IWX_RX_MPDU_MFLG1_ADDRTYPE_MASK 0x03
3620 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK 0xf0
3621 #define IWX_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT 3
3622
3623 #define IWX_RX_MPDU_MFLG2_HDR_LEN_MASK 0x1f
3624 #define IWX_RX_MPDU_MFLG2_PAD 0x20
3625 #define IWX_RX_MPDU_MFLG2_AMSDU 0x40
3626
3627 #define IWX_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK 0x7f
3628 #define IWX_RX_MPDU_AMSDU_LAST_SUBFRAME 0x80
3629
3630 #define IWX_RX_MPDU_PHY_AMPDU (1 << 5)
3631 #define IWX_RX_MPDU_PHY_AMPDU_TOGGLE (1 << 6)
3632 #define IWX_RX_MPDU_PHY_SHORT_PREAMBLE (1 << 7)
3633 #define IWX_RX_MPDU_PHY_NCCK_ADDTL_NTFY (1 << 7)
3634 #define IWX_RX_MPDU_PHY_TSF_OVERLOAD (1 << 8)
3635
3636 struct iwx_rx_mpdu_desc_v3 {
3637 union {
3638 uint32_t filter_match;
3639 uint32_t phy_data3;
3640 };
3641 union {
3642 uint32_t rss_hash;
3643 uint32_t phy_data2;
3644 };
3645 uint32_t partial_hash; /* ip/tcp header hash w/o some fields */
3646 uint16_t raw_xsum;
3647 uint16_t reserved_xsum;
3648 uint32_t rate_n_flags;
3649 uint8_t energy_a;
3650 uint8_t energy_b;
3651 uint8_t channel;
3652 uint8_t mac_context;
3653 uint32_t gp2_on_air_rise;
3654 union {
3655 /*
3656 * TSF value on air rise (INA), only valid if
3657 * IWX_RX_MPDU_PHY_TSF_OVERLOAD isn't set
3658 */
3659 struct {
3660 uint32_t tsf_on_air_rise0;
3661 uint32_t tsf_on_air_rise1;
3662 };
3663
3664 struct {
3665 uint32_t phy_data0;
3666
3667 /* Only valid if IWX_RX_MPDU_PHY_TSF_OVERLOAD is set. */
3668 uint32_t phy_data1;
3669 };
3670 };
3671 uint32_t reserved[2];
3672 } __packed; /* RX_MPDU_RES_START_API_S_VER_3,
3673 RX_MPDU_RES_START_API_S_VER_5 */
3674
3675 struct iwx_rx_mpdu_desc_v1 {
3676 union {
3677 uint32_t rss_hash;
3678 uint32_t phy_data2;
3679 };
3680 union {
3681 uint32_t filter_match;
3682 uint32_t phy_data3;
3683 };
3684 uint32_t rate_n_flags;
3685 uint8_t energy_a;
3686 uint8_t energy_b;
3687 uint8_t channel;
3688 uint8_t mac_context;
3689 uint32_t gp2_on_air_rise;
3690 union {
3691 struct {
3692 uint32_t tsf_on_air_rise0;
3693 uint32_t tsf_on_air_rise1;
3694 };
3695 struct {
3696 uint32_t phy_data0;
3697 uint32_t phy_data1;
3698 };
3699 };
3700 } __packed;
3701
3702 #define IWX_RX_REORDER_DATA_INVALID_BAID 0x7f
3703
3704 #define IWX_RX_MPDU_REORDER_NSSN_MASK 0x00000fff
3705 #define IWX_RX_MPDU_REORDER_SN_MASK 0x00fff000
3706 #define IWX_RX_MPDU_REORDER_SN_SHIFT 12
3707 #define IWX_RX_MPDU_REORDER_BAID_MASK 0x7f000000
3708 #define IWX_RX_MPDU_REORDER_BAID_SHIFT 24
3709 #define IWX_RX_MPDU_REORDER_BA_OLD_SN 0x80000000
3710
3711 struct iwx_rx_mpdu_desc {
3712 uint16_t mpdu_len;
3713 uint8_t mac_flags1;
3714 uint8_t mac_flags2;
3715 uint8_t amsdu_info;
3716 uint16_t phy_info;
3717 uint8_t mac_phy_idx;
3718 uint16_t raw_csum;
3719 union {
3720 uint16_t l3l4_flags;
3721 uint16_t phy_data4;
3722 };
3723 uint16_t status;
3724 uint8_t hash_filter;
3725 uint8_t sta_id_flags;
3726 uint32_t reorder_data;
3727 union {
3728 struct iwx_rx_mpdu_desc_v1 v1;
3729 struct iwx_rx_mpdu_desc_v3 v3;
3730 };
3731 } __packed; /* RX_MPDU_RES_START_API_S_VER_3,
3732 RX_MPDU_RES_START_API_S_VER_4,
3733 RX_MPDU_RES_START_API_S_VER_5 */
3734
3735 #define IWX_RX_DESC_SIZE_V1 ((sizeof(struct iwx_rx_mpdu_desc) - \
3736 sizeof(struct iwx_rx_mpdu_desc_v3)) + sizeof(struct iwx_rx_mpdu_desc_v1))
3737
3738 struct iwx_frame_release {
3739 uint8_t baid;
3740 uint8_t reserved;
3741 uint16_t nssn;
3742 };
3743
3744 /**
3745 * enum iwx_bar_frame_release_sta_tid - STA/TID information for BAR release
3746 * @IWX_BAR_FRAME_RELEASE_TID_MASK: TID mask
3747 * @IWX_BAR_FRAME_RELEASE_STA_MASK: STA mask
3748 */
3749 #define IWX_BAR_FRAME_RELEASE_TID_MASK 0x0000000f
3750 #define IWX_BAR_FRAME_RELEASE_STA_MASK 0x000001f0
3751 #define IWX_BAR_FRAME_RELEASE_STA_SHIFT 4
3752
3753 /**
3754 * enum iwx_bar_frame_release_ba_info - BA information for BAR release
3755 * @IWL_BAR_FRAME_RELEASE_NSSN_MASK: NSSN mask
3756 * @IWL_BAR_FRAME_RELEASE_SN_MASK: SN mask (ignored by driver)
3757 * @IWL_BAR_FRAME_RELEASE_BAID_MASK: BAID mask
3758 */
3759 #define IWX_BAR_FRAME_RELEASE_NSSN_MASK 0x00000fff
3760 #define IWX_BAR_FRAME_RELEASE_SN_MASK 0x00fff000
3761 #define IWX_BAR_FRAME_RELEASE_SN_SHIFT 12
3762 #define IWX_BAR_FRAME_RELEASE_BAID_MASK 0x3f000000
3763 #define IWX_BAR_FRAME_RELEASE_BAID_SHIFT 24
3764
3765 /**
3766 * struct iwx_bar_frame_release - frame release from BAR info
3767 * @sta_tid: STA & TID information, see &enum iwx_bar_frame_release_sta_tid.
3768 * @ba_info: BA information, see &enum iwx_bar_frame_release_ba_info.
3769 */
3770 struct iwx_bar_frame_release {
3771 uint32_t sta_tid;
3772 uint32_t ba_info;
3773 } __packed; /* RX_BAR_TO_FRAME_RELEASE_API_S_VER_1 */
3774
3775 /**
3776 * struct iwx_radio_version_notif - information on the radio version
3777 * ( IWX_RADIO_VERSION_NOTIFICATION = 0x68 )
3778 * @radio_flavor:
3779 * @radio_step:
3780 * @radio_dash:
3781 */
3782 struct iwx_radio_version_notif {
3783 uint32_t radio_flavor;
3784 uint32_t radio_step;
3785 uint32_t radio_dash;
3786 } __packed; /* IWX_RADIO_VERSION_NOTOFICATION_S_VER_1 */
3787
3788 #define IWX_CARD_ENABLED 0x00
3789 #define IWX_HW_CARD_DISABLED 0x01
3790 #define IWX_SW_CARD_DISABLED 0x02
3791 #define IWX_CT_KILL_CARD_DISABLED 0x04
3792 #define IWX_HALT_CARD_DISABLED 0x08
3793 #define IWX_CARD_DISABLED_MSK 0x0f
3794 #define IWX_CARD_IS_RX_ON 0x10
3795
3796 /**
3797 * struct iwx_radio_version_notif - information on the radio version
3798 * (IWX_CARD_STATE_NOTIFICATION = 0xa1 )
3799 * @flags: %iwx_card_state_flags
3800 */
3801 struct iwx_card_state_notif {
3802 uint32_t flags;
3803 } __packed; /* CARD_STATE_NTFY_API_S_VER_1 */
3804
3805 /**
3806 * struct iwx_missed_beacons_notif - information on missed beacons
3807 * ( IWX_MISSED_BEACONS_NOTIFICATION = 0xa2 )
3808 * @mac_id: interface ID
3809 * @consec_missed_beacons_since_last_rx: number of consecutive missed
3810 * beacons since last RX.
3811 * @consec_missed_beacons: number of consecutive missed beacons
3812 * @num_expected_beacons:
3813 * @num_recvd_beacons:
3814 */
3815 struct iwx_missed_beacons_notif {
3816 uint32_t mac_id;
3817 uint32_t consec_missed_beacons_since_last_rx;
3818 uint32_t consec_missed_beacons;
3819 uint32_t num_expected_beacons;
3820 uint32_t num_recvd_beacons;
3821 } __packed; /* IWX_MISSED_BEACON_NTFY_API_S_VER_3 */
3822
3823 /**
3824 * struct iwx_mfuart_load_notif - mfuart image version & status
3825 * ( IWX_MFUART_LOAD_NOTIFICATION = 0xb1 )
3826 * @installed_ver: installed image version
3827 * @external_ver: external image version
3828 * @status: MFUART loading status
3829 * @duration: MFUART loading time
3830 */
3831 struct iwx_mfuart_load_notif {
3832 uint32_t installed_ver;
3833 uint32_t external_ver;
3834 uint32_t status;
3835 uint32_t duration;
3836 } __packed; /*MFU_LOADER_NTFY_API_S_VER_1*/
3837
3838 /**
3839 * struct iwx_set_calib_default_cmd - set default value for calibration.
3840 * ( IWX_SET_CALIB_DEFAULT_CMD = 0x8e )
3841 * @calib_index: the calibration to set value for
3842 * @length: of data
3843 * @data: the value to set for the calibration result
3844 */
3845 struct iwx_set_calib_default_cmd {
3846 uint16_t calib_index;
3847 uint16_t length;
3848 uint8_t data[0];
3849 } __packed; /* IWX_PHY_CALIB_OVERRIDE_VALUES_S */
3850
3851 #define IWX_MAX_PORT_ID_NUM 2
3852 #define IWX_MAX_MCAST_FILTERING_ADDRESSES 256
3853
3854 /**
3855 * struct iwx_mcast_filter_cmd - configure multicast filter.
3856 * @filter_own: Set 1 to filter out multicast packets sent by station itself
3857 * @port_id: Multicast MAC addresses array specifier. This is a strange way
3858 * to identify network interface adopted in host-device IF.
3859 * It is used by FW as index in array of addresses. This array has
3860 * IWX_MAX_PORT_ID_NUM members.
3861 * @count: Number of MAC addresses in the array
3862 * @pass_all: Set 1 to pass all multicast packets.
3863 * @bssid: current association BSSID.
3864 * @addr_list: Place holder for array of MAC addresses.
3865 * IMPORTANT: add padding if necessary to ensure DWORD alignment.
3866 */
3867 struct iwx_mcast_filter_cmd {
3868 uint8_t filter_own;
3869 uint8_t port_id;
3870 uint8_t count;
3871 uint8_t pass_all;
3872 uint8_t bssid[6];
3873 uint8_t reserved[2];
3874 uint8_t addr_list[0];
3875 } __packed; /* IWX_MCAST_FILTERING_CMD_API_S_VER_1 */
3876
3877 struct iwx_statistics_dbg {
3878 uint32_t burst_check;
3879 uint32_t burst_count;
3880 uint32_t wait_for_silence_timeout_cnt;
3881 uint32_t reserved[3];
3882 } __packed; /* IWX_STATISTICS_DEBUG_API_S_VER_2 */
3883
3884 struct iwx_statistics_div {
3885 uint32_t tx_on_a;
3886 uint32_t tx_on_b;
3887 uint32_t exec_time;
3888 uint32_t probe_time;
3889 uint32_t rssi_ant;
3890 uint32_t reserved2;
3891 } __packed; /* IWX_STATISTICS_SLOW_DIV_API_S_VER_2 */
3892
3893 struct iwx_statistics_bt_activity {
3894 uint32_t hi_priority_tx_req_cnt;
3895 uint32_t hi_priority_tx_denied_cnt;
3896 uint32_t lo_priority_tx_req_cnt;
3897 uint32_t lo_priority_tx_denied_cnt;
3898 uint32_t hi_priority_rx_req_cnt;
3899 uint32_t hi_priority_rx_denied_cnt;
3900 uint32_t lo_priority_rx_req_cnt;
3901 uint32_t lo_priority_rx_denied_cnt;
3902 } __packed; /* IWX_STATISTICS_BT_ACTIVITY_API_S_VER_1 */
3903
3904 struct iwx_statistics_general_common {
3905 uint32_t radio_temperature;
3906 struct iwx_statistics_dbg dbg;
3907 uint32_t sleep_time;
3908 uint32_t slots_out;
3909 uint32_t slots_idle;
3910 uint32_t ttl_timestamp;
3911 struct iwx_statistics_div slow_div;
3912 uint32_t rx_enable_counter;
3913 /*
3914 * num_of_sos_states:
3915 * count the number of times we have to re-tune
3916 * in order to get out of bad PHY status
3917 */
3918 uint32_t num_of_sos_states;
3919 uint32_t beacon_filtered;
3920 uint32_t missed_beacons;
3921 uint8_t beacon_filter_average_energy;
3922 uint8_t beacon_filter_reason;
3923 uint8_t beacon_filter_current_energy;
3924 uint8_t beacon_filter_reserved;
3925 uint32_t beacon_filter_delta_time;
3926 struct iwx_statistics_bt_activity bt_activity;
3927 uint64_t rx_time;
3928 uint64_t on_time_rf;
3929 uint64_t on_time_scan;
3930 uint64_t tx_time;
3931 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */
3932
3933 struct iwx_statistics_rx_non_phy {
3934 uint32_t bogus_cts; /* CTS received when not expecting CTS */
3935 uint32_t bogus_ack; /* ACK received when not expecting ACK */
3936 uint32_t non_bssid_frames; /* number of frames with BSSID that
3937 * doesn't belong to the STA BSSID */
3938 uint32_t filtered_frames; /* count frames that were dumped in the
3939 * filtering process */
3940 uint32_t non_channel_beacons; /* beacons with our bss id but not on
3941 * our serving channel */
3942 uint32_t channel_beacons; /* beacons with our bss id and in our
3943 * serving channel */
3944 uint32_t num_missed_bcon; /* number of missed beacons */
3945 uint32_t adc_rx_saturation_time; /* count in 0.8us units the time the
3946 * ADC was in saturation */
3947 uint32_t ina_detection_search_time;/* total time (in 0.8us) searched
3948 * for INA */
3949 uint32_t beacon_silence_rssi[3];/* RSSI silence after beacon frame */
3950 uint32_t interference_data_flag; /* flag for interference data
3951 * availability. 1 when data is
3952 * available. */
3953 uint32_t channel_load; /* counts RX Enable time in uSec */
3954 uint32_t dsp_false_alarms; /* DSP false alarm (both OFDM
3955 * and CCK) counter */
3956 uint32_t beacon_rssi_a;
3957 uint32_t beacon_rssi_b;
3958 uint32_t beacon_rssi_c;
3959 uint32_t beacon_energy_a;
3960 uint32_t beacon_energy_b;
3961 uint32_t beacon_energy_c;
3962 uint32_t num_bt_kills;
3963 uint32_t mac_id;
3964 uint32_t directed_data_mpdu;
3965 } __packed; /* IWX_STATISTICS_RX_NON_PHY_API_S_VER_3 */
3966
3967 struct iwx_statistics_rx_phy {
3968 uint32_t ina_cnt;
3969 uint32_t fina_cnt;
3970 uint32_t plcp_err;
3971 uint32_t crc32_err;
3972 uint32_t overrun_err;
3973 uint32_t early_overrun_err;
3974 uint32_t crc32_good;
3975 uint32_t false_alarm_cnt;
3976 uint32_t fina_sync_err_cnt;
3977 uint32_t sfd_timeout;
3978 uint32_t fina_timeout;
3979 uint32_t unresponded_rts;
3980 uint32_t rxe_frame_limit_overrun;
3981 uint32_t sent_ack_cnt;
3982 uint32_t sent_cts_cnt;
3983 uint32_t sent_ba_rsp_cnt;
3984 uint32_t dsp_self_kill;
3985 uint32_t mh_format_err;
3986 uint32_t re_acq_main_rssi_sum;
3987 uint32_t reserved;
3988 } __packed; /* IWX_STATISTICS_RX_PHY_API_S_VER_2 */
3989
3990 struct iwx_statistics_rx_ht_phy {
3991 uint32_t plcp_err;
3992 uint32_t overrun_err;
3993 uint32_t early_overrun_err;
3994 uint32_t crc32_good;
3995 uint32_t crc32_err;
3996 uint32_t mh_format_err;
3997 uint32_t agg_crc32_good;
3998 uint32_t agg_mpdu_cnt;
3999 uint32_t agg_cnt;
4000 uint32_t unsupport_mcs;
4001 } __packed; /* IWX_STATISTICS_HT_RX_PHY_API_S_VER_1 */
4002
4003 /*
4004 * The first MAC indices (starting from 0)
4005 * are available to the driver, AUX follows
4006 */
4007 #define IWX_MAC_INDEX_AUX 4
4008 #define IWX_MAC_INDEX_MIN_DRIVER 0
4009 #define IWX_NUM_MAC_INDEX_DRIVER IWX_MAC_INDEX_AUX
4010
4011 #define IWX_STATION_COUNT 16
4012
4013 #define IWX_MAX_CHAINS 3
4014
4015 struct iwx_statistics_tx_non_phy_agg {
4016 uint32_t ba_timeout;
4017 uint32_t ba_reschedule_frames;
4018 uint32_t scd_query_agg_frame_cnt;
4019 uint32_t scd_query_no_agg;
4020 uint32_t scd_query_agg;
4021 uint32_t scd_query_mismatch;
4022 uint32_t frame_not_ready;
4023 uint32_t underrun;
4024 uint32_t bt_prio_kill;
4025 uint32_t rx_ba_rsp_cnt;
4026 int8_t txpower[IWX_MAX_CHAINS];
4027 int8_t reserved;
4028 uint32_t reserved2;
4029 } __packed; /* IWX_STATISTICS_TX_NON_PHY_AGG_API_S_VER_1 */
4030
4031 struct iwx_statistics_tx_channel_width {
4032 uint32_t ext_cca_narrow_ch20[1];
4033 uint32_t ext_cca_narrow_ch40[2];
4034 uint32_t ext_cca_narrow_ch80[3];
4035 uint32_t ext_cca_narrow_ch160[4];
4036 uint32_t last_tx_ch_width_indx;
4037 uint32_t rx_detected_per_ch_width[4];
4038 uint32_t success_per_ch_width[4];
4039 uint32_t fail_per_ch_width[4];
4040 }; /* IWX_STATISTICS_TX_CHANNEL_WIDTH_API_S_VER_1 */
4041
4042 struct iwx_statistics_tx {
4043 uint32_t preamble_cnt;
4044 uint32_t rx_detected_cnt;
4045 uint32_t bt_prio_defer_cnt;
4046 uint32_t bt_prio_kill_cnt;
4047 uint32_t few_bytes_cnt;
4048 uint32_t cts_timeout;
4049 uint32_t ack_timeout;
4050 uint32_t expected_ack_cnt;
4051 uint32_t actual_ack_cnt;
4052 uint32_t dump_msdu_cnt;
4053 uint32_t burst_abort_next_frame_mismatch_cnt;
4054 uint32_t burst_abort_missing_next_frame_cnt;
4055 uint32_t cts_timeout_collision;
4056 uint32_t ack_or_ba_timeout_collision;
4057 struct iwx_statistics_tx_non_phy_agg agg;
4058 struct iwx_statistics_tx_channel_width channel_width;
4059 } __packed; /* IWX_STATISTICS_TX_API_S_VER_4 */
4060
4061 struct iwx_statistics_general {
4062 struct iwx_statistics_general_common common;
4063 uint32_t beacon_counter[IWX_MAC_INDEX_AUX];
4064 uint8_t beacon_average_energy[IWX_MAC_INDEX_AUX];
4065 uint8_t reserved[8 - IWX_MAC_INDEX_AUX];
4066 } __packed; /* STATISTICS_GENERAL_API_S_VER_10 */
4067
4068 struct iwx_statistics_rx {
4069 struct iwx_statistics_rx_phy ofdm;
4070 struct iwx_statistics_rx_phy cck;
4071 struct iwx_statistics_rx_non_phy general;
4072 struct iwx_statistics_rx_ht_phy ofdm_ht;
4073 } __packed; /* IWX_STATISTICS_RX_API_S_VER_3 */
4074
4075 /*
4076 * IWX_STATISTICS_NOTIFICATION = 0x9d (notification only, not a command)
4077 *
4078 * By default, uCode issues this notification after receiving a beacon
4079 * while associated. To disable this behavior, set DISABLE_NOTIF flag in the
4080 * IWX_REPLY_STATISTICS_CMD 0x9c, above.
4081 *
4082 * Statistics counters continue to increment beacon after beacon, but are
4083 * cleared when changing channels or when driver issues IWX_REPLY_STATISTICS_CMD
4084 * 0x9c with CLEAR_STATS bit set (see above).
4085 *
4086 * uCode also issues this notification during scans. uCode clears statistics
4087 * appropriately so that each notification contains statistics for only the
4088 * one channel that has just been scanned.
4089 */
4090
4091 /**
4092 * struct iwx_statistics_load - RX statistics for multi-queue devices
4093 * @air_time: accumulated air time, per mac
4094 * @byte_count: accumulated byte count, per mac
4095 * @pkt_count: accumulated packet count, per mac
4096 * @avg_energy: average RSSI, per station
4097 */
4098 struct iwx_statistics_load {
4099 uint32_t air_time[IWX_MAC_INDEX_AUX];
4100 uint32_t byte_count[IWX_MAC_INDEX_AUX];
4101 uint32_t pkt_count[IWX_MAC_INDEX_AUX];
4102 uint8_t avg_energy[IWX_STATION_COUNT];
4103 } __packed; /* STATISTICS_RX_MAC_STATION_S_VER_3 */
4104
4105 struct iwx_notif_statistics {
4106 uint32_t flag;
4107 struct iwx_statistics_rx rx;
4108 struct iwx_statistics_tx tx;
4109 struct iwx_statistics_general general;
4110 struct iwx_statistics_load load_stats;
4111 } __packed; /* STATISTICS_NTFY_API_S_VER_13 */
4112
4113
4114 /**
4115 * flags used in statistics notification
4116 * @IWX_STATISTICS_REPLY_FLG_CLEAR: statistics were cleared after this report
4117 */
4118 #define IWX_STATISTICS_REPLY_FLG_CLEAR 0x01
4119
4120 /**
4121 * flags used in statistics command
4122 * @IWX_STATISTICS_FLG_CLEAR: request to clear statistics after the report
4123 * that's sent after this command
4124 * @IWX_STATISTICS_FLG_DISABLE_NOTIF: disable unilateral statistics
4125 * notifications
4126 */
4127 #define IWX_STATISTICS_FLG_CLEAR 0x01
4128 #define IWX_STATISTICS_FLG_DISABLE_NOTIF 0x02
4129
4130 /**
4131 * struct iwx_statistics_cmd - statistics config command
4132 * @flags: IWX_STATISTICS_* flags
4133 */
4134 struct iwx_statistics_cmd {
4135 uint32_t flags;
4136 } __packed; /* STATISTICS_CMD_API_S_VER_1 */
4137
4138
4139 /***********************************
4140 * Smart Fifo API
4141 ***********************************/
4142 /* Smart Fifo state */
4143 #define IWX_SF_LONG_DELAY_ON 0 /* should never be called by driver */
4144 #define IWX_SF_FULL_ON 1
4145 #define IWX_SF_UNINIT 2
4146 #define IWX_SF_INIT_OFF 3
4147 #define IWX_SF_HW_NUM_STATES 4
4148
4149 /* Smart Fifo possible scenario */
4150 #define IWX_SF_SCENARIO_SINGLE_UNICAST 0
4151 #define IWX_SF_SCENARIO_AGG_UNICAST 1
4152 #define IWX_SF_SCENARIO_MULTICAST 2
4153 #define IWX_SF_SCENARIO_BA_RESP 3
4154 #define IWX_SF_SCENARIO_TX_RESP 4
4155 #define IWX_SF_NUM_SCENARIO 5
4156
4157 #define IWX_SF_TRANSIENT_STATES_NUMBER 2 /* IWX_SF_LONG_DELAY_ON and IWX_SF_FULL_ON */
4158 #define IWX_SF_NUM_TIMEOUT_TYPES 2 /* Aging timer and Idle timer */
4159
4160 /* smart FIFO default values */
4161 #define IWX_SF_W_MARK_SISO 4096
4162 #define IWX_SF_W_MARK_MIMO2 8192
4163 #define IWX_SF_W_MARK_MIMO3 6144
4164 #define IWX_SF_W_MARK_LEGACY 4096
4165 #define IWX_SF_W_MARK_SCAN 4096
4166
4167 /* SF Scenarios timers for default configuration (aligned to 32 uSec) */
4168 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
4169 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
4170 #define IWX_SF_AGG_UNICAST_IDLE_TIMER_DEF 160 /* 150 uSec */
4171 #define IWX_SF_AGG_UNICAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
4172 #define IWX_SF_MCAST_IDLE_TIMER_DEF 160 /* 150 mSec */
4173 #define IWX_SF_MCAST_AGING_TIMER_DEF 400 /* 0.4 mSec */
4174 #define IWX_SF_BA_IDLE_TIMER_DEF 160 /* 150 uSec */
4175 #define IWX_SF_BA_AGING_TIMER_DEF 400 /* 0.4 mSec */
4176 #define IWX_SF_TX_RE_IDLE_TIMER_DEF 160 /* 150 uSec */
4177 #define IWX_SF_TX_RE_AGING_TIMER_DEF 400 /* 0.4 mSec */
4178
4179 /* SF Scenarios timers for FULL_ON state (aligned to 32 uSec) */
4180 #define IWX_SF_SINGLE_UNICAST_IDLE_TIMER 320 /* 300 uSec */
4181 #define IWX_SF_SINGLE_UNICAST_AGING_TIMER 2016 /* 2 mSec */
4182 #define IWX_SF_AGG_UNICAST_IDLE_TIMER 320 /* 300 uSec */
4183 #define IWX_SF_AGG_UNICAST_AGING_TIMER 2016 /* 2 mSec */
4184 #define IWX_SF_MCAST_IDLE_TIMER 2016 /* 2 mSec */
4185 #define IWX_SF_MCAST_AGING_TIMER 10016 /* 10 mSec */
4186 #define IWX_SF_BA_IDLE_TIMER 320 /* 300 uSec */
4187 #define IWX_SF_BA_AGING_TIMER 2016 /* 2 mSec */
4188 #define IWX_SF_TX_RE_IDLE_TIMER 320 /* 300 uSec */
4189 #define IWX_SF_TX_RE_AGING_TIMER 2016 /* 2 mSec */
4190
4191 #define IWX_SF_LONG_DELAY_AGING_TIMER 1000000 /* 1 Sec */
4192
4193 #define IWX_SF_CFG_DUMMY_NOTIF_OFF (1 << 16)
4194
4195 /**
4196 * Smart Fifo configuration command.
4197 * @state: smart fifo state, types listed in enum %iwx_sf_state.
4198 * @watermark: Minimum allowed available free space in RXF for transient state.
4199 * @long_delay_timeouts: aging and idle timer values for each scenario
4200 * in long delay state.
4201 * @full_on_timeouts: timer values for each scenario in full on state.
4202 */
4203 struct iwx_sf_cfg_cmd {
4204 uint32_t state;
4205 uint32_t watermark[IWX_SF_TRANSIENT_STATES_NUMBER];
4206 uint32_t long_delay_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES];
4207 uint32_t full_on_timeouts[IWX_SF_NUM_SCENARIO][IWX_SF_NUM_TIMEOUT_TYPES];
4208 } __packed; /* IWX_SF_CFG_API_S_VER_2 */
4209
4210 #define IWX_AC_BK 0
4211 #define IWX_AC_BE 1
4212 #define IWX_AC_VI 2
4213 #define IWX_AC_VO 3
4214 #define IWX_AC_NUM 4
4215
4216 /**
4217 * MAC context flags
4218 * @IWX_MAC_PROT_FLG_TGG_PROTECT: 11g protection when transmitting OFDM frames,
4219 * this will require CCK RTS/CTS2self.
4220 * RTS/CTS will protect full burst time.
4221 * @IWX_MAC_PROT_FLG_HT_PROT: enable HT protection
4222 * @IWX_MAC_PROT_FLG_FAT_PROT: protect 40 MHz transmissions
4223 * @IWX_MAC_PROT_FLG_SELF_CTS_EN: allow CTS2self
4224 */
4225 #define IWX_MAC_PROT_FLG_TGG_PROTECT (1 << 3)
4226 #define IWX_MAC_PROT_FLG_HT_PROT (1 << 23)
4227 #define IWX_MAC_PROT_FLG_FAT_PROT (1 << 24)
4228 #define IWX_MAC_PROT_FLG_SELF_CTS_EN (1 << 30)
4229
4230 #define IWX_MAC_FLG_SHORT_SLOT (1 << 4)
4231 #define IWX_MAC_FLG_SHORT_PREAMBLE (1 << 5)
4232
4233 /**
4234 * Supported MAC types
4235 * @IWX_FW_MAC_TYPE_FIRST: lowest supported MAC type
4236 * @IWX_FW_MAC_TYPE_AUX: Auxiliary MAC (internal)
4237 * @IWX_FW_MAC_TYPE_LISTENER: monitor MAC type (?)
4238 * @IWX_FW_MAC_TYPE_PIBSS: Pseudo-IBSS
4239 * @IWX_FW_MAC_TYPE_IBSS: IBSS
4240 * @IWX_FW_MAC_TYPE_BSS_STA: BSS (managed) station
4241 * @IWX_FW_MAC_TYPE_P2P_DEVICE: P2P Device
4242 * @IWX_FW_MAC_TYPE_P2P_STA: P2P client
4243 * @IWX_FW_MAC_TYPE_GO: P2P GO
4244 * @IWX_FW_MAC_TYPE_TEST: ?
4245 * @IWX_FW_MAC_TYPE_MAX: highest support MAC type
4246 */
4247 #define IWX_FW_MAC_TYPE_FIRST 1
4248 #define IWX_FW_MAC_TYPE_AUX IWX_FW_MAC_TYPE_FIRST
4249 #define IWX_FW_MAC_TYPE_LISTENER 2
4250 #define IWX_FW_MAC_TYPE_PIBSS 3
4251 #define IWX_FW_MAC_TYPE_IBSS 4
4252 #define IWX_FW_MAC_TYPE_BSS_STA 5
4253 #define IWX_FW_MAC_TYPE_P2P_DEVICE 6
4254 #define IWX_FW_MAC_TYPE_P2P_STA 7
4255 #define IWX_FW_MAC_TYPE_GO 8
4256 #define IWX_FW_MAC_TYPE_TEST 9
4257 #define IWX_FW_MAC_TYPE_MAX IWX_FW_MAC_TYPE_TEST
4258 /* IWX_MAC_CONTEXT_TYPE_API_E_VER_1 */
4259
4260 /**
4261 * TSF hw timer ID
4262 * @IWX_TSF_ID_A: use TSF A
4263 * @IWX_TSF_ID_B: use TSF B
4264 * @IWX_TSF_ID_C: use TSF C
4265 * @IWX_TSF_ID_D: use TSF D
4266 * @IWX_NUM_TSF_IDS: number of TSF timers available
4267 */
4268 #define IWX_TSF_ID_A 0
4269 #define IWX_TSF_ID_B 1
4270 #define IWX_TSF_ID_C 2
4271 #define IWX_TSF_ID_D 3
4272 #define IWX_NUM_TSF_IDS 4
4273 /* IWX_TSF_ID_API_E_VER_1 */
4274
4275 /**
4276 * struct iwx_mac_data_ap - configuration data for AP MAC context
4277 * @beacon_time: beacon transmit time in system time
4278 * @beacon_tsf: beacon transmit time in TSF
4279 * @bi: beacon interval in TU
4280 * @bi_reciprocal: 2^32 / bi
4281 * @dtim_interval: dtim transmit time in TU
4282 * @dtim_reciprocal: 2^32 / dtim_interval
4283 * @mcast_qid: queue ID for multicast traffic
4284 * NOTE: obsolete from VER2 and on
4285 * @beacon_template: beacon template ID
4286 */
4287 struct iwx_mac_data_ap {
4288 uint32_t beacon_time;
4289 uint64_t beacon_tsf;
4290 uint32_t bi;
4291 uint32_t bi_reciprocal;
4292 uint32_t dtim_interval;
4293 uint32_t dtim_reciprocal;
4294 uint32_t mcast_qid;
4295 uint32_t beacon_template;
4296 } __packed; /* AP_MAC_DATA_API_S_VER_2 */
4297
4298 /**
4299 * struct iwx_mac_data_ibss - configuration data for IBSS MAC context
4300 * @beacon_time: beacon transmit time in system time
4301 * @beacon_tsf: beacon transmit time in TSF
4302 * @bi: beacon interval in TU
4303 * @bi_reciprocal: 2^32 / bi
4304 * @beacon_template: beacon template ID
4305 */
4306 struct iwx_mac_data_ibss {
4307 uint32_t beacon_time;
4308 uint64_t beacon_tsf;
4309 uint32_t bi;
4310 uint32_t bi_reciprocal;
4311 uint32_t beacon_template;
4312 } __packed; /* IBSS_MAC_DATA_API_S_VER_1 */
4313
4314 /**
4315 * enum iwx_mac_data_policy - policy of the data path for this MAC
4316 * @TWT_SUPPORTED: twt is supported
4317 * @MORE_DATA_ACK_SUPPORTED: AP supports More Data Ack according to
4318 * paragraph 9.4.1.17 in P802.11ax_D4 specification. Used for TWT
4319 * early termination detection.
4320 * @FLEXIBLE_TWT_SUPPORTED: AP supports flexible TWT schedule
4321 * @PROTECTED_TWT_SUPPORTED: AP supports protected TWT frames (with 11w)
4322 * @BROADCAST_TWT_SUPPORTED: AP and STA support broadcast TWT
4323 * @COEX_HIGH_PRIORITY_ENABLE: high priority mode for BT coex, to be used
4324 * during 802.1X negotiation (and allowed during 4-way-HS)
4325 */
4326 #define IWX_TWT_SUPPORTED BIT (1 << 0)
4327 #define IWX_MORE_DATA_ACK_SUPPORTED (1 << 1)
4328 #define IWX_FLEXIBLE_TWT_SUPPORTED (1 << 2)
4329 #define IWX_PROTECTED_TWT_SUPPORTED (1 << 3)
4330 #define IWX_BROADCAST_TWT_SUPPORTED (1 << 4)
4331 #define IWX_COEX_HIGH_PRIORITY_ENABLE (1 << 5)
4332
4333 /**
4334 * struct iwx_mac_data_sta - configuration data for station MAC context
4335 * @is_assoc: 1 for associated state, 0 otherwise
4336 * @dtim_time: DTIM arrival time in system time
4337 * @dtim_tsf: DTIM arrival time in TSF
4338 * @bi: beacon interval in TU, applicable only when associated
4339 * @data_policy: see &enum iwl_mac_data_policy
4340 * @dtim_interval: DTIM interval in TU, applicable only when associated
4341 * @listen_interval: in beacon intervals, applicable only when associated
4342 * @assoc_id: unique ID assigned by the AP during association
4343 */
4344 struct iwx_mac_data_sta {
4345 uint32_t is_assoc;
4346 uint32_t dtim_time;
4347 uint64_t dtim_tsf;
4348 uint32_t bi;
4349 uint32_t reserved1;
4350 uint32_t dtim_interval;
4351 uint32_t data_policy;
4352 uint32_t listen_interval;
4353 uint32_t assoc_id;
4354 uint32_t assoc_beacon_arrive_time;
4355 } __packed; /* IWX_STA_MAC_DATA_API_S_VER_2 */
4356
4357 /**
4358 * struct iwx_mac_data_go - configuration data for P2P GO MAC context
4359 * @ap: iwx_mac_data_ap struct with most config data
4360 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
4361 * 0 indicates that there is no CT window.
4362 * @opp_ps_enabled: indicate that opportunistic PS allowed
4363 */
4364 struct iwx_mac_data_go {
4365 struct iwx_mac_data_ap ap;
4366 uint32_t ctwin;
4367 uint32_t opp_ps_enabled;
4368 } __packed; /* GO_MAC_DATA_API_S_VER_1 */
4369
4370 /**
4371 * struct iwx_mac_data_p2p_sta - configuration data for P2P client MAC context
4372 * @sta: iwx_mac_data_sta struct with most config data
4373 * @ctwin: client traffic window in TU (period after TBTT when GO is present).
4374 * 0 indicates that there is no CT window.
4375 */
4376 struct iwx_mac_data_p2p_sta {
4377 struct iwx_mac_data_sta sta;
4378 uint32_t ctwin;
4379 } __packed; /* P2P_STA_MAC_DATA_API_S_VER_1 */
4380
4381 /**
4382 * struct iwx_mac_data_pibss - Pseudo IBSS config data
4383 * @stats_interval: interval in TU between statistics notifications to host.
4384 */
4385 struct iwx_mac_data_pibss {
4386 uint32_t stats_interval;
4387 } __packed; /* PIBSS_MAC_DATA_API_S_VER_1 */
4388
4389 /*
4390 * struct iwx_mac_data_p2p_dev - configuration data for the P2P Device MAC
4391 * context.
4392 * @is_disc_extended: if set to true, P2P Device discoverability is enabled on
4393 * other channels as well. This should be to true only in case that the
4394 * device is discoverable and there is an active GO. Note that setting this
4395 * field when not needed, will increase the number of interrupts and have
4396 * effect on the platform power, as this setting opens the Rx filters on
4397 * all macs.
4398 */
4399 struct iwx_mac_data_p2p_dev {
4400 uint32_t is_disc_extended;
4401 } __packed; /* _P2P_DEV_MAC_DATA_API_S_VER_1 */
4402
4403 /**
4404 * MAC context filter flags
4405 * @IWX_MAC_FILTER_IN_PROMISC: accept all data frames
4406 * @IWX_MAC_FILTER_IN_CONTROL_AND_MGMT: pass all management and
4407 * control frames to the host
4408 * @IWX_MAC_FILTER_ACCEPT_GRP: accept multicast frames
4409 * @IWX_MAC_FILTER_DIS_DECRYPT: don't decrypt unicast frames
4410 * @IWX_MAC_FILTER_DIS_GRP_DECRYPT: don't decrypt multicast frames
4411 * @IWX_MAC_FILTER_IN_BEACON: transfer foreign BSS's beacons to host
4412 * (in station mode when associated)
4413 * @IWX_MAC_FILTER_OUT_BCAST: filter out all broadcast frames
4414 * @IWX_MAC_FILTER_IN_CRC32: extract FCS and append it to frames
4415 * @IWX_MAC_FILTER_IN_PROBE_REQUEST: pass probe requests to host
4416 */
4417 #define IWX_MAC_FILTER_IN_PROMISC (1 << 0)
4418 #define IWX_MAC_FILTER_IN_CONTROL_AND_MGMT (1 << 1)
4419 #define IWX_MAC_FILTER_ACCEPT_GRP (1 << 2)
4420 #define IWX_MAC_FILTER_DIS_DECRYPT (1 << 3)
4421 #define IWX_MAC_FILTER_DIS_GRP_DECRYPT (1 << 4)
4422 #define IWX_MAC_FILTER_IN_BEACON (1 << 6)
4423 #define IWX_MAC_FILTER_OUT_BCAST (1 << 8)
4424 #define IWX_MAC_FILTER_IN_CRC32 (1 << 11)
4425 #define IWX_MAC_FILTER_IN_PROBE_REQUEST (1 << 12)
4426
4427 /**
4428 * QoS flags
4429 * @IWX_MAC_QOS_FLG_UPDATE_EDCA: ?
4430 * @IWX_MAC_QOS_FLG_TGN: HT is enabled
4431 * @IWX_MAC_QOS_FLG_TXOP_TYPE: ?
4432 *
4433 */
4434 #define IWX_MAC_QOS_FLG_UPDATE_EDCA (1 << 0)
4435 #define IWX_MAC_QOS_FLG_TGN (1 << 1)
4436 #define IWX_MAC_QOS_FLG_TXOP_TYPE (1 << 4)
4437
4438 /**
4439 * struct iwx_ac_qos - QOS timing params for IWX_MAC_CONTEXT_CMD
4440 * @cw_min: Contention window, start value in numbers of slots.
4441 * Should be a power-of-2, minus 1. Device's default is 0x0f.
4442 * @cw_max: Contention window, max value in numbers of slots.
4443 * Should be a power-of-2, minus 1. Device's default is 0x3f.
4444 * @aifsn: Number of slots in Arbitration Interframe Space (before
4445 * performing random backoff timing prior to Tx). Device default 1.
4446 * @fifos_mask: FIFOs used by this MAC for this AC
4447 * @edca_txop: Length of Tx opportunity, in uSecs. Device default is 0.
4448 *
4449 * One instance of this config struct for each of 4 EDCA access categories
4450 * in struct iwx_qosparam_cmd.
4451 *
4452 * Device will automatically increase contention window by (2*CW) + 1 for each
4453 * transmission retry. Device uses cw_max as a bit mask, ANDed with new CW
4454 * value, to cap the CW value.
4455 */
4456 struct iwx_ac_qos {
4457 uint16_t cw_min;
4458 uint16_t cw_max;
4459 uint8_t aifsn;
4460 uint8_t fifos_mask;
4461 uint16_t edca_txop;
4462 } __packed; /* IWX_AC_QOS_API_S_VER_2 */
4463
4464 /**
4465 * struct iwx_mac_ctx_cmd - command structure to configure MAC contexts
4466 * ( IWX_MAC_CONTEXT_CMD = 0x28 )
4467 * @id_and_color: ID and color of the MAC
4468 * @action: action to perform, one of IWX_FW_CTXT_ACTION_*
4469 * @mac_type: one of IWX_FW_MAC_TYPE_*
4470 * @tsf_id: TSF HW timer, one of IWX_TSF_ID_*
4471 * @node_addr: MAC address
4472 * @bssid_addr: BSSID
4473 * @cck_rates: basic rates available for CCK
4474 * @ofdm_rates: basic rates available for OFDM
4475 * @protection_flags: combination of IWX_MAC_PROT_FLG_FLAG_*
4476 * @cck_short_preamble: 0x20 for enabling short preamble, 0 otherwise
4477 * @short_slot: 0x10 for enabling short slots, 0 otherwise
4478 * @filter_flags: combination of IWX_MAC_FILTER_*
4479 * @qos_flags: from IWX_MAC_QOS_FLG_*
4480 * @ac: one iwx_mac_qos configuration for each AC
4481 * @mac_specific: one of struct iwx_mac_data_*, according to mac_type
4482 */
4483 struct iwx_mac_ctx_cmd {
4484 /* COMMON_INDEX_HDR_API_S_VER_1 */
4485 uint32_t id_and_color;
4486 uint32_t action;
4487 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S_VER_1 */
4488 uint32_t mac_type;
4489 uint32_t tsf_id;
4490 uint8_t node_addr[6];
4491 uint16_t reserved_for_node_addr;
4492 uint8_t bssid_addr[6];
4493 uint16_t reserved_for_bssid_addr;
4494 uint32_t cck_rates;
4495 uint32_t ofdm_rates;
4496 uint32_t protection_flags;
4497 uint32_t cck_short_preamble;
4498 uint32_t short_slot;
4499 uint32_t filter_flags;
4500 /* IWX_MAC_QOS_PARAM_API_S_VER_1 */
4501 uint32_t qos_flags;
4502 struct iwx_ac_qos ac[IWX_AC_NUM+1];
4503 /* IWX_MAC_CONTEXT_COMMON_DATA_API_S */
4504 union {
4505 struct iwx_mac_data_ap ap;
4506 struct iwx_mac_data_go go;
4507 struct iwx_mac_data_sta sta;
4508 struct iwx_mac_data_p2p_sta p2p_sta;
4509 struct iwx_mac_data_p2p_dev p2p_dev;
4510 struct iwx_mac_data_pibss pibss;
4511 struct iwx_mac_data_ibss ibss;
4512 };
4513 } __packed; /* IWX_MAC_CONTEXT_CMD_API_S_VER_1 */
4514
iwx_reciprocal(uint32_t v)4515 static inline uint32_t iwx_reciprocal(uint32_t v)
4516 {
4517 if (!v)
4518 return 0;
4519 return 0xFFFFFFFF / v;
4520 }
4521
4522 /* Power Management Commands, Responses, Notifications */
4523
4524 /**
4525 * masks for LTR config command flags
4526 * @IWX_LTR_CFG_FLAG_FEATURE_ENABLE: Feature operational status
4527 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS: allow LTR change on shadow
4528 * memory access
4529 * @IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH: allow LTR msg send on ANY LTR
4530 * reg change
4531 * @IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3: allow LTR msg send on transition from
4532 * D0 to D3
4533 * @IWX_LTR_CFG_FLAG_SW_SET_SHORT: fixed static short LTR register
4534 * @IWX_LTR_CFG_FLAG_SW_SET_LONG: fixed static short LONG register
4535 * @IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD: allow going into C10 on PD
4536 */
4537 #define IWX_LTR_CFG_FLAG_FEATURE_ENABLE 0x00000001
4538 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_SHADOW_REG_ACCESS 0x00000002
4539 #define IWX_LTR_CFG_FLAG_HW_EN_SHRT_WR_THROUGH 0x00000004
4540 #define IWX_LTR_CFG_FLAG_HW_DIS_ON_D0_2_D3 0x00000008
4541 #define IWX_LTR_CFG_FLAG_SW_SET_SHORT 0x00000010
4542 #define IWX_LTR_CFG_FLAG_SW_SET_LONG 0x00000020
4543 #define IWX_LTR_CFG_FLAG_DENIE_C10_ON_PD 0x00000040
4544
4545 #define IWX_LTR_VALID_STATES_NUM 4
4546
4547 /**
4548 * struct iwx_ltr_config_cmd - configures the LTR
4549 * @flags: See %enum iwx_ltr_config_flags
4550 * @static_long:
4551 * @static_short:
4552 * @ltr_cfg_values:
4553 * @ltr_short_idle_timeout:
4554 */
4555 struct iwx_ltr_config_cmd {
4556 uint32_t flags;
4557 uint32_t static_long;
4558 uint32_t static_short;
4559 uint32_t ltr_cfg_values[IWX_LTR_VALID_STATES_NUM];
4560 uint32_t ltr_short_idle_timeout;
4561 } __packed; /* LTR_CAPABLE_API_S_VER_2 */
4562
4563 /* Radio LP RX Energy Threshold measured in dBm */
4564 #define IWX_POWER_LPRX_RSSI_THRESHOLD 75
4565 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MAX 94
4566 #define IWX_POWER_LPRX_RSSI_THRESHOLD_MIN 30
4567
4568 /**
4569 * Masks for iwx_mac_power_cmd command flags
4570 * @IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK: '1' Allow to save power by turning off
4571 * receiver and transmitter. '0' - does not allow.
4572 * @IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK: '0' Driver disables power management,
4573 * '1' Driver enables PM (use rest of parameters)
4574 * @IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK: '0' PM have to walk up every DTIM,
4575 * '1' PM could sleep over DTIM till listen Interval.
4576 * @IWX_POWER_FLAGS_SNOOZE_ENA_MSK: Enable snoozing only if uAPSD is enabled and all
4577 * access categories are both delivery and trigger enabled.
4578 * @IWX_POWER_FLAGS_BT_SCO_ENA: Enable BT SCO coex only if uAPSD and
4579 * PBW Snoozing enabled
4580 * @IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK: Advanced PM (uAPSD) enable mask
4581 * @IWX_POWER_FLAGS_LPRX_ENA_MSK: Low Power RX enable.
4582 * @IWX_POWER_FLAGS_AP_UAPSD_MISBEHAVING_ENA_MSK: AP/GO's uAPSD misbehaving
4583 * detection enablement
4584 */
4585 #define IWX_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
4586 #define IWX_POWER_FLAGS_POWER_MANAGEMENT_ENA_MSK (1 << 1)
4587 #define IWX_POWER_FLAGS_SKIP_OVER_DTIM_MSK (1 << 2)
4588 #define IWX_POWER_FLAGS_SNOOZE_ENA_MSK (1 << 5)
4589 #define IWX_POWER_FLAGS_BT_SCO_ENA (1 << 8)
4590 #define IWX_POWER_FLAGS_ADVANCE_PM_ENA_MSK (1 << 9)
4591 #define IWX_POWER_FLAGS_LPRX_ENA_MSK (1 << 11)
4592 #define IWX_POWER_FLAGS_UAPSD_MISBEHAVING_ENA_MSK (1 << 12)
4593
4594 #define IWX_POWER_VEC_SIZE 5
4595
4596 /**
4597 * Masks for device power command flags
4598 * @IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK:
4599 * '1' Allow to save power by turning off receiver and transmitter.
4600 * '0' Do not allow. This flag should be always set to '1' unless
4601 * one needs to disable actual power down for debug purposes.
4602 * @IWX_DEVICE_POWER_FLAGS_CAM_MSK:
4603 * '1' CAM (Continuous Active Mode) is set, power management is disabled.
4604 * '0' Power management is enabled, one of the power schemes is applied.
4605 */
4606 #define IWX_DEVICE_POWER_FLAGS_POWER_SAVE_ENA_MSK (1 << 0)
4607 #define IWX_DEVICE_POWER_FLAGS_CAM_MSK (1 << 13)
4608
4609 /**
4610 * struct iwx_device_power_cmd - device wide power command.
4611 * IWX_POWER_TABLE_CMD = 0x77 (command, has simple generic response)
4612 *
4613 * @flags: Power table command flags from IWX_DEVICE_POWER_FLAGS_*
4614 */
4615 struct iwx_device_power_cmd {
4616 /* PM_POWER_TABLE_CMD_API_S_VER_6 */
4617 uint16_t flags;
4618 uint16_t reserved;
4619 } __packed;
4620
4621 /**
4622 * struct iwx_mac_power_cmd - New power command containing uAPSD support
4623 * IWX_MAC_PM_POWER_TABLE = 0xA9 (command, has simple generic response)
4624 * @id_and_color: MAC context identifier
4625 * @flags: Power table command flags from POWER_FLAGS_*
4626 * @keep_alive_seconds: Keep alive period in seconds. Default - 25 sec.
4627 * Minimum allowed:- 3 * DTIM. Keep alive period must be
4628 * set regardless of power scheme or current power state.
4629 * FW use this value also when PM is disabled.
4630 * @rx_data_timeout: Minimum time (usec) from last Rx packet for AM to
4631 * PSM transition - legacy PM
4632 * @tx_data_timeout: Minimum time (usec) from last Tx packet for AM to
4633 * PSM transition - legacy PM
4634 * @sleep_interval: not in use
4635 * @skip_dtim_periods: Number of DTIM periods to skip if Skip over DTIM flag
4636 * is set. For example, if it is required to skip over
4637 * one DTIM, this value need to be set to 2 (DTIM periods).
4638 * @rx_data_timeout_uapsd: Minimum time (usec) from last Rx packet for AM to
4639 * PSM transition - uAPSD
4640 * @tx_data_timeout_uapsd: Minimum time (usec) from last Tx packet for AM to
4641 * PSM transition - uAPSD
4642 * @lprx_rssi_threshold: Signal strength up to which LP RX can be enabled.
4643 * Default: 80dbm
4644 * @num_skip_dtim: Number of DTIMs to skip if Skip over DTIM flag is set
4645 * @snooze_interval: Maximum time between attempts to retrieve buffered data
4646 * from the AP [msec]
4647 * @snooze_window: A window of time in which PBW snoozing insures that all
4648 * packets received. It is also the minimum time from last
4649 * received unicast RX packet, before client stops snoozing
4650 * for data. [msec]
4651 * @snooze_step: TBD
4652 * @qndp_tid: TID client shall use for uAPSD QNDP triggers
4653 * @uapsd_ac_flags: Set trigger-enabled and delivery-enabled indication for
4654 * each corresponding AC.
4655 * Use IEEE80211_WMM_IE_STA_QOSINFO_AC* for correct values.
4656 * @uapsd_max_sp: Use IEEE80211_WMM_IE_STA_QOSINFO_SP_* for correct
4657 * values.
4658 * @heavy_tx_thld_packets: TX threshold measured in number of packets
4659 * @heavy_rx_thld_packets: RX threshold measured in number of packets
4660 * @heavy_tx_thld_percentage: TX threshold measured in load's percentage
4661 * @heavy_rx_thld_percentage: RX threshold measured in load's percentage
4662 * @limited_ps_threshold:
4663 */
4664 struct iwx_mac_power_cmd {
4665 /* CONTEXT_DESC_API_T_VER_1 */
4666 uint32_t id_and_color;
4667
4668 /* CLIENT_PM_POWER_TABLE_S_VER_1 */
4669 uint16_t flags;
4670 uint16_t keep_alive_seconds;
4671 uint32_t rx_data_timeout;
4672 uint32_t tx_data_timeout;
4673 uint32_t rx_data_timeout_uapsd;
4674 uint32_t tx_data_timeout_uapsd;
4675 uint8_t lprx_rssi_threshold;
4676 uint8_t skip_dtim_periods;
4677 uint16_t snooze_interval;
4678 uint16_t snooze_window;
4679 uint8_t snooze_step;
4680 uint8_t qndp_tid;
4681 uint8_t uapsd_ac_flags;
4682 uint8_t uapsd_max_sp;
4683 uint8_t heavy_tx_thld_packets;
4684 uint8_t heavy_rx_thld_packets;
4685 uint8_t heavy_tx_thld_percentage;
4686 uint8_t heavy_rx_thld_percentage;
4687 uint8_t limited_ps_threshold;
4688 uint8_t reserved;
4689 } __packed;
4690
4691 #define IWX_DEFAULT_PS_TX_DATA_TIMEOUT (100 * 1000)
4692 #define IWX_DEFAULT_PS_RX_DATA_TIMEOUT (100 * 1000)
4693
4694 /*
4695 * struct iwx_uapsd_misbehaving_ap_notif - FW sends this notification when
4696 * associated AP is identified as improperly implementing uAPSD protocol.
4697 * IWX_PSM_UAPSD_AP_MISBEHAVING_NOTIFICATION = 0x78
4698 * @sta_id: index of station in uCode's station table - associated AP ID in
4699 * this context.
4700 */
4701 struct iwx_uapsd_misbehaving_ap_notif {
4702 uint32_t sta_id;
4703 uint8_t mac_id;
4704 uint8_t reserved[3];
4705 } __packed;
4706
4707 /**
4708 * struct iwx_beacon_filter_cmd
4709 * IWX_REPLY_BEACON_FILTERING_CMD = 0xd2 (command)
4710 * @id_and_color: MAC context identifier
4711 * @bf_energy_delta: Used for RSSI filtering, if in 'normal' state. Send beacon
4712 * to driver if delta in Energy values calculated for this and last
4713 * passed beacon is greater than this threshold. Zero value means that
4714 * the Energy change is ignored for beacon filtering, and beacon will
4715 * not be forced to be sent to driver regardless of this delta. Typical
4716 * energy delta 5dB.
4717 * @bf_roaming_energy_delta: Used for RSSI filtering, if in 'roaming' state.
4718 * Send beacon to driver if delta in Energy values calculated for this
4719 * and last passed beacon is greater than this threshold. Zero value
4720 * means that the Energy change is ignored for beacon filtering while in
4721 * Roaming state, typical energy delta 1dB.
4722 * @bf_roaming_state: Used for RSSI filtering. If absolute Energy values
4723 * calculated for current beacon is less than the threshold, use
4724 * Roaming Energy Delta Threshold, otherwise use normal Energy Delta
4725 * Threshold. Typical energy threshold is -72dBm.
4726 * @bf_temp_threshold: This threshold determines the type of temperature
4727 * filtering (Slow or Fast) that is selected (Units are in Celsius):
4728 * If the current temperature is above this threshold - Fast filter
4729 * will be used, If the current temperature is below this threshold -
4730 * Slow filter will be used.
4731 * @bf_temp_fast_filter: Send Beacon to driver if delta in temperature values
4732 * calculated for this and the last passed beacon is greater than this
4733 * threshold. Zero value means that the temperature change is ignored for
4734 * beacon filtering; beacons will not be forced to be sent to driver
4735 * regardless of whether its temperature has been changed.
4736 * @bf_temp_slow_filter: Send Beacon to driver if delta in temperature values
4737 * calculated for this and the last passed beacon is greater than this
4738 * threshold. Zero value means that the temperature change is ignored for
4739 * beacon filtering; beacons will not be forced to be sent to driver
4740 * regardless of whether its temperature has been changed.
4741 * @bf_enable_beacon_filter: 1, beacon filtering is enabled; 0, disabled.
4742 * @bf_escape_timer: Send beacons to driver if no beacons were passed
4743 * for a specific period of time. Units: Beacons.
4744 * @ba_escape_timer: Fully receive and parse beacon if no beacons were passed
4745 * for a longer period of time then this escape-timeout. Units: Beacons.
4746 * @ba_enable_beacon_abort: 1, beacon abort is enabled; 0, disabled.
4747 * @bf_threshold_absolute_low: See below.
4748 * @bf_threshold_absolute_high: Send Beacon to driver if Energy value calculated
4749 * for this beacon crossed this absolute threshold. For the 'Increase'
4750 * direction the bf_energy_absolute_low[i] is used. For the 'Decrease'
4751 * direction the bf_energy_absolute_high[i] is used. Zero value means
4752 * that this specific threshold is ignored for beacon filtering, and
4753 * beacon will not be forced to be sent to driver due to this setting.
4754 */
4755 struct iwx_beacon_filter_cmd {
4756 uint32_t bf_energy_delta;
4757 uint32_t bf_roaming_energy_delta;
4758 uint32_t bf_roaming_state;
4759 uint32_t bf_temp_threshold;
4760 uint32_t bf_temp_fast_filter;
4761 uint32_t bf_temp_slow_filter;
4762 uint32_t bf_enable_beacon_filter;
4763 uint32_t bf_debug_flag;
4764 uint32_t bf_escape_timer;
4765 uint32_t ba_escape_timer;
4766 uint32_t ba_enable_beacon_abort;
4767 uint32_t bf_threshold_absolute_low[2];
4768 uint32_t bf_threshold_absolute_high[2];
4769 } __packed; /* BEACON_FILTER_CONFIG_API_S_VER_4 */
4770
4771 /* Beacon filtering and beacon abort */
4772 #define IWX_BF_ENERGY_DELTA_DEFAULT 5
4773 #define IWX_BF_ENERGY_DELTA_MAX 255
4774 #define IWX_BF_ENERGY_DELTA_MIN 0
4775
4776 #define IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT 1
4777 #define IWX_BF_ROAMING_ENERGY_DELTA_MAX 255
4778 #define IWX_BF_ROAMING_ENERGY_DELTA_MIN 0
4779
4780 #define IWX_BF_ROAMING_STATE_DEFAULT 72
4781 #define IWX_BF_ROAMING_STATE_MAX 255
4782 #define IWX_BF_ROAMING_STATE_MIN 0
4783
4784 #define IWX_BF_TEMP_THRESHOLD_DEFAULT 112
4785 #define IWX_BF_TEMP_THRESHOLD_MAX 255
4786 #define IWX_BF_TEMP_THRESHOLD_MIN 0
4787
4788 #define IWX_BF_TEMP_FAST_FILTER_DEFAULT 1
4789 #define IWX_BF_TEMP_FAST_FILTER_MAX 255
4790 #define IWX_BF_TEMP_FAST_FILTER_MIN 0
4791
4792 #define IWX_BF_TEMP_SLOW_FILTER_DEFAULT 5
4793 #define IWX_BF_TEMP_SLOW_FILTER_MAX 255
4794 #define IWX_BF_TEMP_SLOW_FILTER_MIN 0
4795
4796 #define IWX_BF_ENABLE_BEACON_FILTER_DEFAULT 1
4797
4798 #define IWX_BF_DEBUG_FLAG_DEFAULT 0
4799
4800 #define IWX_BF_ESCAPE_TIMER_DEFAULT 50
4801 #define IWX_BF_ESCAPE_TIMER_MAX 1024
4802 #define IWX_BF_ESCAPE_TIMER_MIN 0
4803
4804 #define IWX_BA_ESCAPE_TIMER_DEFAULT 6
4805 #define IWX_BA_ESCAPE_TIMER_D3 9
4806 #define IWX_BA_ESCAPE_TIMER_MAX 1024
4807 #define IWX_BA_ESCAPE_TIMER_MIN 0
4808
4809 #define IWX_BA_ENABLE_BEACON_ABORT_DEFAULT 1
4810
4811 #define IWX_BF_CMD_CONFIG_DEFAULTS \
4812 .bf_energy_delta = htole32(IWX_BF_ENERGY_DELTA_DEFAULT), \
4813 .bf_roaming_energy_delta = \
4814 htole32(IWX_BF_ROAMING_ENERGY_DELTA_DEFAULT), \
4815 .bf_roaming_state = htole32(IWX_BF_ROAMING_STATE_DEFAULT), \
4816 .bf_temp_threshold = htole32(IWX_BF_TEMP_THRESHOLD_DEFAULT), \
4817 .bf_temp_fast_filter = htole32(IWX_BF_TEMP_FAST_FILTER_DEFAULT), \
4818 .bf_temp_slow_filter = htole32(IWX_BF_TEMP_SLOW_FILTER_DEFAULT), \
4819 .bf_debug_flag = htole32(IWX_BF_DEBUG_FLAG_DEFAULT), \
4820 .bf_escape_timer = htole32(IWX_BF_ESCAPE_TIMER_DEFAULT), \
4821 .ba_escape_timer = htole32(IWX_BA_ESCAPE_TIMER_DEFAULT)
4822
4823 /* uCode API values for HT/VHT bit rates */
4824 #define IWX_RATE_HT_SISO_MCS_0_PLCP 0
4825 #define IWX_RATE_HT_SISO_MCS_1_PLCP 1
4826 #define IWX_RATE_HT_SISO_MCS_2_PLCP 2
4827 #define IWX_RATE_HT_SISO_MCS_3_PLCP 3
4828 #define IWX_RATE_HT_SISO_MCS_4_PLCP 4
4829 #define IWX_RATE_HT_SISO_MCS_5_PLCP 5
4830 #define IWX_RATE_HT_SISO_MCS_6_PLCP 6
4831 #define IWX_RATE_HT_SISO_MCS_7_PLCP 7
4832 #define IWX_RATE_HT_MIMO2_MCS_8_PLCP 0x8
4833 #define IWX_RATE_HT_MIMO2_MCS_9_PLCP 0x9
4834 #define IWX_RATE_HT_MIMO2_MCS_10_PLCP 0xA
4835 #define IWX_RATE_HT_MIMO2_MCS_11_PLCP 0xB
4836 #define IWX_RATE_HT_MIMO2_MCS_12_PLCP 0xC
4837 #define IWX_RATE_HT_MIMO2_MCS_13_PLCP 0xD
4838 #define IWX_RATE_HT_MIMO2_MCS_14_PLCP 0xE
4839 #define IWX_RATE_HT_MIMO2_MCS_15_PLCP 0xF
4840 #define IWX_RATE_VHT_SISO_MCS_0_PLCP 0
4841 #define IWX_RATE_VHT_SISO_MCS_1_PLCP 1
4842 #define IWX_RATE_VHT_SISO_MCS_2_PLCP 2
4843 #define IWX_RATE_VHT_SISO_MCS_3_PLCP 3
4844 #define IWX_RATE_VHT_SISO_MCS_4_PLCP 4
4845 #define IWX_RATE_VHT_SISO_MCS_5_PLCP 5
4846 #define IWX_RATE_VHT_SISO_MCS_6_PLCP 6
4847 #define IWX_RATE_VHT_SISO_MCS_7_PLCP 7
4848 #define IWX_RATE_VHT_SISO_MCS_8_PLCP 8
4849 #define IWX_RATE_VHT_SISO_MCS_9_PLCP 9
4850 #define IWX_RATE_VHT_MIMO2_MCS_0_PLCP 0x10
4851 #define IWX_RATE_VHT_MIMO2_MCS_1_PLCP 0x11
4852 #define IWX_RATE_VHT_MIMO2_MCS_2_PLCP 0x12
4853 #define IWX_RATE_VHT_MIMO2_MCS_3_PLCP 0x13
4854 #define IWX_RATE_VHT_MIMO2_MCS_4_PLCP 0x14
4855 #define IWX_RATE_VHT_MIMO2_MCS_5_PLCP 0x15
4856 #define IWX_RATE_VHT_MIMO2_MCS_6_PLCP 0x16
4857 #define IWX_RATE_VHT_MIMO2_MCS_7_PLCP 0x17
4858 #define IWX_RATE_VHT_MIMO2_MCS_8_PLCP 0x18
4859 #define IWX_RATE_VHT_MIMO2_MCS_9_PLCP 0x19
4860 #define IWX_RATE_HT_SISO_MCS_INV_PLCP 0x20
4861 #define IWX_RATE_HT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
4862 #define IWX_RATE_VHT_SISO_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
4863 #define IWX_RATE_VHT_MIMO2_MCS_INV_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
4864 #define IWX_RATE_HT_SISO_MCS_8_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
4865 #define IWX_RATE_HT_SISO_MCS_9_PLCP IWX_RATE_HT_SISO_MCS_INV_PLCP
4866
4867 /*
4868 * These serve as indexes into struct iwx_rate iwx_rates[IWX_RIDX_MAX].
4869 */
4870 enum {
4871 IWX_RATE_1M_INDEX = 0,
4872 IWX_FIRST_CCK_RATE = IWX_RATE_1M_INDEX,
4873 IWX_RATE_2M_INDEX,
4874 IWX_RATE_5M_INDEX,
4875 IWX_RATE_11M_INDEX,
4876 IWX_LAST_CCK_RATE = IWX_RATE_11M_INDEX,
4877 IWX_RATE_6M_INDEX,
4878 IWX_FIRST_OFDM_RATE = IWX_RATE_6M_INDEX,
4879 IWX_RATE_MCS_0_INDEX = IWX_RATE_6M_INDEX,
4880 IWX_FIRST_HT_RATE = IWX_RATE_MCS_0_INDEX,
4881 IWX_FIRST_VHT_RATE = IWX_RATE_MCS_0_INDEX,
4882 IWX_RATE_9M_INDEX,
4883 IWX_RATE_12M_INDEX,
4884 IWX_RATE_MCS_1_INDEX = IWX_RATE_12M_INDEX,
4885 IWX_RATE_MCS_8_INDEX,
4886 IWX_FIRST_HT_MIMO2_RATE = IWX_RATE_MCS_8_INDEX,
4887 IWX_RATE_18M_INDEX,
4888 IWX_RATE_MCS_2_INDEX = IWX_RATE_18M_INDEX,
4889 IWX_RATE_24M_INDEX,
4890 IWX_RATE_MCS_3_INDEX = IWX_RATE_24M_INDEX,
4891 IWX_RATE_MCS_9_INDEX,
4892 IWX_RATE_36M_INDEX,
4893 IWX_RATE_MCS_4_INDEX = IWX_RATE_36M_INDEX,
4894 IWX_RATE_MCS_10_INDEX,
4895 IWX_RATE_48M_INDEX,
4896 IWX_RATE_MCS_5_INDEX = IWX_RATE_48M_INDEX,
4897 IWX_RATE_MCS_11_INDEX,
4898 IWX_RATE_54M_INDEX,
4899 IWX_RATE_MCS_6_INDEX = IWX_RATE_54M_INDEX,
4900 IWX_LAST_NON_HT_RATE = IWX_RATE_54M_INDEX,
4901 IWX_RATE_MCS_7_INDEX,
4902 IWX_LAST_HT_SISO_RATE = IWX_RATE_MCS_7_INDEX,
4903 IWX_RATE_MCS_12_INDEX,
4904 IWX_RATE_MCS_13_INDEX,
4905 IWX_RATE_MCS_14_INDEX,
4906 IWX_RATE_MCS_15_INDEX,
4907 IWX_LAST_HT_RATE = IWX_RATE_MCS_15_INDEX,
4908 IWX_LAST_VHT_RATE = IWX_RATE_MCS_9_INDEX,
4909 IWX_RATE_COUNT_LEGACY = IWX_LAST_NON_HT_RATE + 1,
4910 IWX_RATE_COUNT = IWX_LAST_HT_RATE + 1,
4911 };
4912
4913 #define IWX_RATE_BIT_MSK(r) (1 << (IWX_RATE_##r##M_INDEX))
4914
4915 /* fw API values for legacy bit rates, both OFDM and CCK */
4916 #define IWX_RATE_6M_PLCP 13
4917 #define IWX_RATE_9M_PLCP 15
4918 #define IWX_RATE_12M_PLCP 5
4919 #define IWX_RATE_18M_PLCP 7
4920 #define IWX_RATE_24M_PLCP 9
4921 #define IWX_RATE_36M_PLCP 11
4922 #define IWX_RATE_48M_PLCP 1
4923 #define IWX_RATE_54M_PLCP 3
4924 #define IWX_RATE_1M_PLCP 10
4925 #define IWX_RATE_2M_PLCP 20
4926 #define IWX_RATE_5M_PLCP 55
4927 #define IWX_RATE_11M_PLCP 110
4928 #define IWX_RATE_INVM_PLCP 0xff
4929
4930 /*
4931 * rate_n_flags bit fields version 1
4932 *
4933 * The 32-bit value has different layouts in the low 8 bites depending on the
4934 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
4935 * for CCK and OFDM).
4936 *
4937 * High-throughput (HT) rate format
4938 * bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
4939 * Very High-throughput (VHT) rate format
4940 * bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
4941 * Legacy OFDM rate format for bits 7:0
4942 * bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
4943 * Legacy CCK rate format for bits 7:0:
4944 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
4945 */
4946
4947 /* Bit 8: (1) HT format, (0) legacy or VHT format */
4948 #define IWX_RATE_MCS_HT_POS 8
4949 #define IWX_RATE_MCS_HT_MSK_V1 (1 << IWX_RATE_MCS_HT_POS)
4950
4951 /* Bit 9: (1) CCK, (0) OFDM. HT (bit 8) must be "0" for this bit to be valid */
4952 #define IWX_RATE_MCS_CCK_POS_V1 9
4953 #define IWX_RATE_MCS_CCK_MSK_V1 (1 << IWX_RATE_MCS_CCK_POS_V1)
4954
4955 /* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
4956 #define IWX_RATE_MCS_VHT_POS_V1 26
4957 #define IWX_RATE_MCS_VHT_MSK_V1 (1 << IWX_RATE_MCS_VHT_POS_V1)
4958
4959
4960 /*
4961 * High-throughput (HT) rate format for bits 7:0
4962 *
4963 * 2-0: MCS rate base
4964 * 0) 6 Mbps
4965 * 1) 12 Mbps
4966 * 2) 18 Mbps
4967 * 3) 24 Mbps
4968 * 4) 36 Mbps
4969 * 5) 48 Mbps
4970 * 6) 54 Mbps
4971 * 7) 60 Mbps
4972 * 4-3: 0) Single stream (SISO)
4973 * 1) Dual stream (MIMO)
4974 * 2) Triple stream (MIMO)
4975 * 5: Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
4976 * (bits 7-6 are zero)
4977 *
4978 * Together the low 5 bits work out to the MCS index because we don't
4979 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
4980 * streams and 16-23 have three streams. We could also support MCS 32
4981 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
4982 */
4983 #define IWX_RATE_HT_MCS_RATE_CODE_MSK_V1 0x7
4984 #define IWX_RATE_HT_MCS_NSS_POS_V1 3
4985 #define IWX_RATE_HT_MCS_NSS_MSK_V1 (3 << IWX_RATE_HT_MCS_NSS_POS_V1)
4986 #define IWX_RATE_HT_MCS_MIMO2_MSK_V1 (1 << IWX_RATE_HT_MCS_NSS_POS_V1)
4987
4988 /* Bit 10: (1) Use Green Field preamble */
4989 #define IWX_RATE_HT_MCS_GF_POS 10
4990 #define IWX_RATE_HT_MCS_GF_MSK (1 << IWX_RATE_HT_MCS_GF_POS)
4991
4992 #define IWX_RATE_HT_MCS_INDEX_MSK_V1 0x3f
4993
4994 /*
4995 * Very High-throughput (VHT) rate format for bits 7:0
4996 *
4997 * 3-0: VHT MCS (0-9)
4998 * 5-4: number of streams - 1:
4999 * 0) Single stream (SISO)
5000 * 1) Dual stream (MIMO)
5001 * 2) Triple stream (MIMO)
5002 */
5003
5004 /* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
5005 #define IWX_RATE_VHT_MCS_RATE_CODE_MSK 0xf
5006 #define IWX_RATE_VHT_MCS_NSS_POS 4
5007 #define IWX_RATE_VHT_MCS_NSS_MSK (3 << IWX_RATE_VHT_MCS_NSS_POS)
5008 #define IWX_RATE_VHT_MCS_MIMO2_MSK (1 << IWX_RATE_VHT_MCS_NSS_POS)
5009
5010 /*
5011 * Legacy OFDM rate format for bits 7:0
5012 *
5013 * 3-0: 0xD) 6 Mbps
5014 * 0xF) 9 Mbps
5015 * 0x5) 12 Mbps
5016 * 0x7) 18 Mbps
5017 * 0x9) 24 Mbps
5018 * 0xB) 36 Mbps
5019 * 0x1) 48 Mbps
5020 * 0x3) 54 Mbps
5021 * (bits 7-4 are 0)
5022 *
5023 * Legacy CCK rate format for bits 7:0:
5024 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
5025 *
5026 * 6-0: 10) 1 Mbps
5027 * 20) 2 Mbps
5028 * 55) 5.5 Mbps
5029 * 110) 11 Mbps
5030 * (bit 7 is 0)
5031 */
5032 #define IWX_RATE_LEGACY_RATE_MSK_V1 0xff
5033
5034 /* Bit 10 - OFDM HE */
5035 #define IWX_RATE_MCS_HE_POS_V1 10
5036 #define IWX_RATE_MCS_HE_MSK_V1 (1 << RATE_MCS_HE_POS_V1)
5037
5038 /*
5039 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
5040 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
5041 */
5042 #define IWX_RATE_MCS_CHAN_WIDTH_POS 11
5043 #define IWX_RATE_MCS_CHAN_WIDTH_MSK_V1 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5044 #define IWX_RATE_MCS_CHAN_WIDTH_20_V1 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5045 #define IWX_RATE_MCS_CHAN_WIDTH_40_V1 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5046 #define IWX_RATE_MCS_CHAN_WIDTH_80_V1 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5047 #define IWX_RATE_MCS_CHAN_WIDTH_160_V1 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5048
5049 /* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
5050 #define IWX_RATE_MCS_SGI_POS_V1 13
5051 #define IWX_RATE_MCS_SGI_MSK_V1 (1 << IWX_RATE_MCS_SGI_POS_V1)
5052
5053 /* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C (unused) */
5054 #define IWX_RATE_MCS_ANT_POS 14
5055 #define IWX_RATE_MCS_ANT_A_MSK (1 << IWX_RATE_MCS_ANT_POS)
5056 #define IWX_RATE_MCS_ANT_B_MSK (2 << IWX_RATE_MCS_ANT_POS)
5057 #define IWX_RATE_MCS_ANT_AB_MSK (IWX_RATE_MCS_ANT_A_MSK | \
5058 IWX_RATE_MCS_ANT_B_MSK)
5059 #define IWX_RATE_MCS_ANT_MSK IWX_RATE_MCS_ANT_ABC_MSK
5060 #define IWX_RATE_MCS_ANT_NUM 2
5061
5062 /* Bit 17: (0) SS, (1) SS*2 */
5063 #define IWX_RATE_MCS_STBC_POS 17
5064 #define IWX_RATE_MCS_STBC_MSK (1 << IWX_RATE_MCS_STBC_POS)
5065
5066 /* Bit 18: OFDM-HE dual carrier mode */
5067 #define IWX_RATE_HE_DUAL_CARRIER_MODE 18
5068 #define IWX_RATE_HE_DUAL_CARRIER_MODE_MSK (1 << IWX_RATE_HE_DUAL_CARRIER_MODE)
5069
5070 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
5071 #define IWX_RATE_MCS_BF_POS 19
5072 #define IWX_RATE_MCS_BF_MSK (1 << IWX_RATE_MCS_BF_POS)
5073
5074 /*
5075 * Bit 20-21: HE LTF type and guard interval
5076 * HE (ext) SU:
5077 * 0 1xLTF+0.8us
5078 * 1 2xLTF+0.8us
5079 * 2 2xLTF+1.6us
5080 * 3 & SGI (bit 13) clear 4xLTF+3.2us
5081 * 3 & SGI (bit 13) set 4xLTF+0.8us
5082 * HE MU:
5083 * 0 4xLTF+0.8us
5084 * 1 2xLTF+0.8us
5085 * 2 2xLTF+1.6us
5086 * 3 4xLTF+3.2us
5087 * HE TRIG:
5088 * 0 1xLTF+1.6us
5089 * 1 2xLTF+1.6us
5090 * 2 4xLTF+3.2us
5091 * 3 (does not occur)
5092 */
5093 #define IWX_RATE_MCS_HE_GI_LTF_POS 20
5094 #define IWX_RATE_MCS_HE_GI_LTF_MSK_V1 (3 << IWX_RATE_MCS_HE_GI_LTF_POS)
5095
5096 /* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
5097 #define IWX_RATE_MCS_HE_TYPE_POS_V1 22
5098 #define IWX_RATE_MCS_HE_TYPE_SU_V1 (0 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5099 #define IWX_RATE_MCS_HE_TYPE_EXT_SU_V1 (1 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5100 #define IWX_RATE_MCS_HE_TYPE_MU_V1 (2 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5101 #define IWX_RATE_MCS_HE_TYPE_TRIG_V1 (3 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5102 #define IWX_RATE_MCS_HE_TYPE_MSK_V1 (3 << IWX_RATE_MCS_HE_TYPE_POS_V1)
5103
5104 /* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
5105 #define IWX_RATE_MCS_DUP_POS_V1 24
5106 #define IWX_RATE_MCS_DUP_MSK_V1 (3 << IWX_RATE_MCS_DUP_POS_V1)
5107
5108 /* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
5109 #define IWX_RATE_MCS_LDPC_POS_V1 27
5110 #define IWX_RATE_MCS_LDPC_MSK_V1 (1 << IWX_RATE_MCS_LDPC_POS_V1)
5111
5112 /* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
5113 #define IWX_RATE_MCS_HE_106T_POS_V1 28
5114 #define IWX_RATE_MCS_HE_106T_MSK_V1 (1 << IWX_RATE_MCS_HE_106T_POS_V1)
5115
5116 /* Bit 30-31: (1) RTS, (2) CTS */
5117 #define IWX_RATE_MCS_RTS_REQUIRED_POS (30)
5118 #define IWX_RATE_MCS_RTS_REQUIRED_MSK (1 << IWX_RATE_MCS_RTS_REQUIRED_POS)
5119 #define IWX_RATE_MCS_CTS_REQUIRED_POS (31)
5120 #define IWX_RATE_MCS_CTS_REQUIRED_MSK (1 << IWX_RATE_MCS_CTS_REQUIRED_POS)
5121
5122
5123 /* rate_n_flags bit field version 2
5124 *
5125 * The 32-bit value has different layouts in the low 8 bits depending on the
5126 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
5127 * for CCK and OFDM).
5128 *
5129 */
5130
5131 /* Bits 10-8: rate format
5132 * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT)
5133 * (3) Very High-throughput (VHT) (4) High-efficiency (HE)
5134 * (5) Extremely High-throughput (EHT)
5135 */
5136 #define IWX_RATE_MCS_MOD_TYPE_POS 8
5137 #define IWX_RATE_MCS_MOD_TYPE_MSK (0x7 << IWX_RATE_MCS_MOD_TYPE_POS)
5138 #define IWX_RATE_MCS_CCK_MSK (0 << IWX_RATE_MCS_MOD_TYPE_POS)
5139 #define IWX_RATE_MCS_LEGACY_OFDM_MSK (1 << IWX_RATE_MCS_MOD_TYPE_POS)
5140 #define IWX_RATE_MCS_HT_MSK (2 << IWX_RATE_MCS_MOD_TYPE_POS)
5141 #define IWX_RATE_MCS_VHT_MSK (3 << IWX_RATE_MCS_MOD_TYPE_POS)
5142 #define IWX_RATE_MCS_HE_MSK (4 << IWX_RATE_MCS_MOD_TYPE_POS)
5143 #define IWX_RATE_MCS_EHT_MSK (5 << IWX_RATE_MCS_MOD_TYPE_POS)
5144
5145 /*
5146 * Legacy CCK rate format for bits 0:3:
5147 *
5148 * (0) 0xa - 1 Mbps
5149 * (1) 0x14 - 2 Mbps
5150 * (2) 0x37 - 5.5 Mbps
5151 * (3) 0x6e - 11 nbps
5152 *
5153 * Legacy OFDM rate format for bits 0:3:
5154 *
5155 * (0) 6 Mbps
5156 * (1) 9 Mbps
5157 * (2) 12 Mbps
5158 * (3) 18 Mbps
5159 * (4) 24 Mbps
5160 * (5) 36 Mbps
5161 * (6) 48 Mbps
5162 * (7) 54 Mbps
5163 *
5164 */
5165 #define IWX_RATE_LEGACY_RATE_MSK 0x7
5166
5167 /*
5168 * HT, VHT, HE, EHT rate format for bits 3:0
5169 * 3-0: MCS
5170 *
5171 */
5172 #define IWX_RATE_HT_MCS_CODE_MSK 0x7
5173 #define IWX_RATE_MCS_NSS_POS 4
5174 #define IWX_RATE_MCS_NSS_MSK (1 << IWX_RATE_MCS_NSS_POS)
5175 #define IWX_RATE_MCS_CODE_MSK 0xf
5176 #define IWX_RATE_HT_MCS_INDEX(r) ((((r) & IWX_RATE_MCS_NSS_MSK) >> 1) | \
5177 ((r) & IWX_RATE_HT_MCS_CODE_MSK))
5178
5179 /* Bits 7-5: reserved */
5180
5181 /*
5182 * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz
5183 */
5184 #define IWX_RATE_MCS_CHAN_WIDTH_MSK (0x7 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5185 #define IWX_RATE_MCS_CHAN_WIDTH_20 (0 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5186 #define IWX_RATE_MCS_CHAN_WIDTH_40 (1 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5187 #define IWX_RATE_MCS_CHAN_WIDTH_80 (2 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5188 #define IWX_RATE_MCS_CHAN_WIDTH_160 (3 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5189 #define IWX_RATE_MCS_CHAN_WIDTH_320 (4 << IWX_RATE_MCS_CHAN_WIDTH_POS)
5190
5191 /* Bit 15-14: Antenna selection:
5192 * Bit 14: Ant A active
5193 * Bit 15: Ant B active
5194 *
5195 * All relevant definitions are same as in v1
5196 */
5197
5198 /* Bit 16 (1) LDPC enables, (0) LDPC disabled */
5199 #define IWX_RATE_MCS_LDPC_POS 16
5200 #define IWX_RATE_MCS_LDPC_MSK (1 << IWX_RATE_MCS_LDPC_POS)
5201
5202 /* Bit 17: (0) SS, (1) SS*2 (same as v1) */
5203
5204 /* Bit 18: OFDM-HE dual carrier mode (same as v1) */
5205
5206 /* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */
5207
5208 /*
5209 * Bit 22-20: HE LTF type and guard interval
5210 * CCK:
5211 * 0 long preamble
5212 * 1 short preamble
5213 * HT/VHT:
5214 * 0 0.8us
5215 * 1 0.4us
5216 * HE (ext) SU:
5217 * 0 1xLTF+0.8us
5218 * 1 2xLTF+0.8us
5219 * 2 2xLTF+1.6us
5220 * 3 4xLTF+3.2us
5221 * 4 4xLTF+0.8us
5222 * HE MU:
5223 * 0 4xLTF+0.8us
5224 * 1 2xLTF+0.8us
5225 * 2 2xLTF+1.6us
5226 * 3 4xLTF+3.2us
5227 * HE TRIG:
5228 * 0 1xLTF+1.6us
5229 * 1 2xLTF+1.6us
5230 * 2 4xLTF+3.2us
5231 * */
5232 #define IWX_RATE_MCS_HE_GI_LTF_MSK (0x7 << IWX_RATE_MCS_HE_GI_LTF_POS)
5233 #define IWX_RATE_MCS_SGI_POS IWX_RATE_MCS_HE_GI_LTF_POS
5234 #define IWX_RATE_MCS_SGI_MSK (1 << IWX_RATE_MCS_SGI_POS)
5235 #define IWX_RATE_MCS_HE_SU_4_LTF 3
5236 #define IWX_RATE_MCS_HE_SU_4_LTF_08_GI 4
5237
5238 /* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
5239 #define IWX_RATE_MCS_HE_TYPE_POS 23
5240 #define IWX_RATE_MCS_HE_TYPE_SU (0 << IWX_RATE_MCS_HE_TYPE_POS)
5241 #define IWX_RATE_MCS_HE_TYPE_EXT_SU (1 << IWX_RATE_MCS_HE_TYPE_POS)
5242 #define IWX_RATE_MCS_HE_TYPE_MU (2 << IWX_RATE_MCS_HE_TYPE_POS)
5243 #define IWX_RATE_MCS_HE_TYPE_TRIG (3 << IWX_RATE_MCS_HE_TYPE_POS)
5244 #define IWX_RATE_MCS_HE_TYPE_MSK (3 << IWX_RATE_MCS_HE_TYPE_POS)
5245
5246 /* Bit 25: duplicate channel enabled
5247 *
5248 * if this bit is set, duplicate is according to BW (bits 11-13):
5249 *
5250 * CCK: 2x 20MHz
5251 * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16)
5252 * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160)
5253 * */
5254 #define IWX_RATE_MCS_DUP_POS 25
5255 #define IWX_RATE_MCS_DUP_MSK (1 << IWX_RATE_MCS_DUP_POS)
5256
5257 /* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
5258 #define IWX_RATE_MCS_HE_106T_POS 26
5259 #define IWX_RATE_MCS_HE_106T_MSK (1 << IWX_RATE_MCS_HE_106T_POS)
5260
5261 /* Bit 27: EHT extra LTF:
5262 * instead of 1 LTF for SISO use 2 LTFs,
5263 * instead of 2 LTFs for NSTS=2 use 4 LTFs*/
5264 #define IWX_RATE_MCS_EHT_EXTRA_LTF_POS 27
5265 #define IWX_RATE_MCS_EHT_EXTRA_LTF_MSK (1 << IWX_RATE_MCS_EHT_EXTRA_LTF_POS)
5266
5267 /* Bit 31-28: reserved */
5268
5269
5270 /* Link Quality definitions */
5271
5272 /* # entries in rate scale table to support Tx retries */
5273 #define IWX_LQ_MAX_RETRY_NUM 16
5274
5275 /* Link quality command flags bit fields */
5276
5277 /* Bit 0: (0) Don't use RTS (1) Use RTS */
5278 #define IWX_LQ_FLAG_USE_RTS_POS 0
5279 #define IWX_LQ_FLAG_USE_RTS_MSK (1 << IWX_LQ_FLAG_USE_RTS_POS)
5280
5281 /* Bit 1-3: LQ command color. Used to match responses to LQ commands */
5282 #define IWX_LQ_FLAG_COLOR_POS 1
5283 #define IWX_LQ_FLAG_COLOR_MSK (7 << IWX_LQ_FLAG_COLOR_POS)
5284
5285 /* Bit 4-5: Tx RTS BW Signalling
5286 * (0) No RTS BW signalling
5287 * (1) Static BW signalling
5288 * (2) Dynamic BW signalling
5289 */
5290 #define IWX_LQ_FLAG_RTS_BW_SIG_POS 4
5291 #define IWX_LQ_FLAG_RTS_BW_SIG_NONE (0 << IWX_LQ_FLAG_RTS_BW_SIG_POS)
5292 #define IWX_LQ_FLAG_RTS_BW_SIG_STATIC (1 << IWX_LQ_FLAG_RTS_BW_SIG_POS)
5293 #define IWX_LQ_FLAG_RTS_BW_SIG_DYNAMIC (2 << IWX_LQ_FLAG_RTS_BW_SIG_POS)
5294
5295 /* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
5296 * Dynamic BW selection allows Tx with narrower BW then requested in rates
5297 */
5298 #define IWX_LQ_FLAG_DYNAMIC_BW_POS 6
5299 #define IWX_LQ_FLAG_DYNAMIC_BW_MSK (1 << IWX_LQ_FLAG_DYNAMIC_BW_POS)
5300
5301 #define IWX_RLC_CHAIN_INFO_DRIVER_FORCE (1 << 0)
5302 #define IWL_RLC_CHAIN_INFO_VALID 0x000e
5303 #define IWL_RLC_CHAIN_INFO_FORCE 0x0070
5304 #define IWL_RLC_CHAIN_INFO_FORCE_MIMO 0x0380
5305 #define IWL_RLC_CHAIN_INFO_COUNT 0x0c00
5306 #define IWL_RLC_CHAIN_INFO_MIMO_COUNT 0x3000
5307
5308 /**
5309 * struct iwx_rlc_properties - RLC properties
5310 * @rx_chain_info: RX chain info, IWX_RLC_CHAIN_INFO_*
5311 * @reserved: reserved
5312 */
5313 struct iwx_rlc_properties {
5314 uint32_t rx_chain_info;
5315 uint32_t reserved;
5316 } __packed; /* RLC_PROPERTIES_S_VER_1 */
5317
5318 #define IWX_SAD_MODE_ENABLED (1 << 0)
5319 #define IWX_SAD_MODE_DEFAULT_ANT_MSK 0x6
5320 #define IWX_SAD_MODE_DEFAULT_ANT_FW 0x0
5321 #define IWX_SAD_MODE_DEFAULT_ANT_A 0x2
5322 #define IWX_SAD_MODE_DEFAULT_ANT_B 0x4
5323
5324 /**
5325 * struct iwx_sad_properties - SAD properties
5326 * @chain_a_sad_mode: chain A SAD mode, IWX_SAD_MODE_*
5327 * @chain_b_sad_mode: chain B SAD mode, IWX_SAD_MODE_*
5328 * @mac_id: MAC index
5329 * @reserved: reserved
5330 */
5331 struct iwx_sad_properties {
5332 uint32_t chain_a_sad_mode;
5333 uint32_t chain_b_sad_mode;
5334 uint32_t mac_id;
5335 uint32_t reserved;
5336 } __packed;
5337
5338 /**
5339 * struct iwx_rlc_config_cmd - RLC configuration
5340 * @phy_id: PHY index
5341 * @rlc: RLC properties, &struct iwx_rlc_properties
5342 * @sad: SAD (single antenna diversity) options, &struct iwx_sad_properties
5343 * @flags: flags, IWX_RLC_FLAGS_*
5344 * @reserved: reserved
5345 */
5346 struct iwx_rlc_config_cmd {
5347 uint32_t phy_id;
5348 struct iwx_rlc_properties rlc;
5349 struct iwx_sad_properties sad;
5350 uint8_t flags;
5351 uint8_t reserved[3];
5352 } __packed; /* RLC_CONFIG_CMD_API_S_VER_2 */
5353
5354 #define IWX_MAX_BAID_OLD 16 /* MAX_IMMEDIATE_BA_API_D_VER_2 */
5355 #define IWX_MAX_BAID 32 /* MAX_IMMEDIATE_BA_API_D_VER_3 */
5356
5357 /**
5358 * BAID allocation/config action
5359 * @IWX_RX_BAID_ACTION_ADD: add a new BAID session
5360 * @IWX_RX_BAID_ACTION_MODIFY: modify the BAID session
5361 * @IWX_RX_BAID_ACTION_REMOVE: remove the BAID session
5362 */
5363 #define IWX_RX_BAID_ACTION_ADD 0
5364 #define IWX_RX_BAID_ACTION_MODIFY 1
5365 #define IWX_RX_BAID_ACTION_REMOVE 2
5366 /* RX_BAID_ALLOCATION_ACTION_E_VER_1 */
5367
5368 /**
5369 * struct iwx_rx_baid_cfg_cmd_alloc - BAID allocation data
5370 * @sta_id_mask: station ID mask
5371 * @tid: the TID for this session
5372 * @reserved: reserved
5373 * @ssn: the starting sequence number
5374 * @win_size: RX BA session window size
5375 */
5376 struct iwx_rx_baid_cfg_cmd_alloc {
5377 uint32_t sta_id_mask;
5378 uint8_t tid;
5379 uint8_t reserved[3];
5380 uint16_t ssn;
5381 uint16_t win_size;
5382 } __packed; /* RX_BAID_ALLOCATION_ADD_CMD_API_S_VER_1 */
5383
5384 /**
5385 * struct iwx_rx_baid_cfg_cmd_modify - BAID modification data
5386 * @old_sta_id_mask: old station ID mask
5387 * @new_sta_id_mask: new station ID mask
5388 * @tid: TID of the BAID
5389 */
5390 struct iwx_rx_baid_cfg_cmd_modify {
5391 uint32_t old_sta_id_mask;
5392 uint32_t new_sta_id_mask;
5393 uint32_t tid;
5394 } __packed; /* RX_BAID_ALLOCATION_MODIFY_CMD_API_S_VER_2 */
5395
5396 /**
5397 * struct iwx_rx_baid_cfg_cmd_remove_v1 - BAID removal data
5398 * @baid: the BAID to remove
5399 */
5400 struct iwx_rx_baid_cfg_cmd_remove_v1 {
5401 uint32_t baid;
5402 } __packed; /* RX_BAID_ALLOCATION_REMOVE_CMD_API_S_VER_1 */
5403
5404 /**
5405 * struct iwx_rx_baid_cfg_cmd_remove - BAID removal data
5406 * @sta_id_mask: the station mask of the BAID to remove
5407 * @tid: the TID of the BAID to remove
5408 */
5409 struct iwx_rx_baid_cfg_cmd_remove {
5410 uint32_t sta_id_mask;
5411 uint32_t tid;
5412 } __packed; /* RX_BAID_ALLOCATION_REMOVE_CMD_API_S_VER_2 */
5413
5414 /**
5415 * struct iwx_rx_baid_cfg_cmd - BAID allocation/config command
5416 * @action: the action, from &enum iwx_rx_baid_action
5417 */
5418 struct iwx_rx_baid_cfg_cmd {
5419 uint32_t action;
5420 union {
5421 struct iwx_rx_baid_cfg_cmd_alloc alloc;
5422 struct iwx_rx_baid_cfg_cmd_modify modify;
5423 struct iwx_rx_baid_cfg_cmd_remove_v1 remove_v1;
5424 struct iwx_rx_baid_cfg_cmd_remove remove;
5425 }; /* RX_BAID_ALLOCATION_OPERATION_API_U_VER_2 */
5426 } __packed; /* RX_BAID_ALLOCATION_CONFIG_CMD_API_S_VER_2 */
5427
5428 /**
5429 * struct iwx_rx_baid_cfg_resp - BAID allocation response
5430 * @baid: the allocated BAID
5431 */
5432 struct iwx_rx_baid_cfg_resp {
5433 uint32_t baid;
5434 }; /* RX_BAID_ALLOCATION_RESPONSE_API_S_VER_1 */
5435
5436 /**
5437 * scheduler queue operation
5438 * @IWX_SCD_QUEUE_ADD: allocate a new queue
5439 * @IWX_SCD_QUEUE_REMOVE: remove a queue
5440 * @IWX_SCD_QUEUE_MODIFY: modify a queue
5441 */
5442 #define IWX_SCD_QUEUE_ADD 0
5443 #define IWX_SCD_QUEUE_REMOVE 1
5444 #define IWX_SCD_QUEUE_MODIFY 2
5445
5446 /**
5447 * struct iwx_scd_queue_cfg_cmd - scheduler queue allocation command
5448 * @operation: the operation, see &enum iwl_scd_queue_cfg_operation
5449 * @u.add.sta_mask: station mask
5450 * @u.add.tid: TID
5451 * @u.add.reserved: reserved
5452 * @u.add.flags: flags from &enum iwl_tx_queue_cfg_actions, except
5453 * %TX_QUEUE_CFG_ENABLE_QUEUE is not valid
5454 * @u.add.cb_size: size code
5455 * @u.add.bc_dram_addr: byte-count table IOVA
5456 * @u.add.tfdq_dram_addr: TFD queue IOVA
5457 * @u.remove.sta_mask: station mask of queue to remove
5458 * @u.remove.tid: TID of queue to remove
5459 * @u.modify.old_sta_mask: old station mask for modify
5460 * @u.modify.tid: TID of queue to modify
5461 * @u.modify.new_sta_mask: new station mask for modify
5462 */
5463 struct iwx_scd_queue_cfg_cmd {
5464 uint32_t operation;
5465 union {
5466 struct {
5467 uint32_t sta_mask;
5468 uint8_t tid;
5469 uint8_t reserved[3];
5470 uint32_t flags;
5471 uint32_t cb_size;
5472 uint64_t bc_dram_addr;
5473 uint64_t tfdq_dram_addr;
5474 } __packed add; /* TX_QUEUE_CFG_CMD_ADD_API_S_VER_1 */
5475 struct {
5476 uint32_t sta_mask;
5477 uint32_t tid;
5478 } __packed remove; /* TX_QUEUE_CFG_CMD_REMOVE_API_S_VER_1 */
5479 struct {
5480 uint32_t old_sta_mask;
5481 uint32_t tid;
5482 uint32_t new_sta_mask;
5483 } __packed modify; /* TX_QUEUE_CFG_CMD_MODIFY_API_S_VER_1 */
5484 } __packed u; /* TX_QUEUE_CFG_CMD_OPERATION_API_U_VER_1 */
5485 } __packed; /* TX_QUEUE_CFG_CMD_API_S_VER_3 */
5486
5487 /**
5488 * Options for TLC config flags
5489 * @IWX_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for
5490 * bandwidths <= 80MHz
5491 * @IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC
5492 * @IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
5493 * bandwidth
5494 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation
5495 * for BPSK (MCS 0) with 1 spatial
5496 * stream
5497 * @IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation
5498 * for BPSK (MCS 0) with 2 spatial
5499 * streams
5500 */
5501 #define IWX_TLC_MNG_CFG_FLAGS_STBC_MSK (1 << 0)
5502 #define IWX_TLC_MNG_CFG_FLAGS_LDPC_MSK (1 << 1)
5503 #define IWX_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK (1 << 2)
5504 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK (1 << 3)
5505 #define IWX_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK (1 << 4)
5506
5507 /**
5508 * enum iwx_tlc_mng_cfg_cw - channel width options
5509 * @IWX_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
5510 * @IWX_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
5511 * @IWX_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
5512 * @IWX_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
5513 * @IWX_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
5514 */
5515 enum iwx_tlc_mng_cfg_cw {
5516 IWX_TLC_MNG_CH_WIDTH_20MHZ,
5517 IWX_TLC_MNG_CH_WIDTH_40MHZ,
5518 IWX_TLC_MNG_CH_WIDTH_80MHZ,
5519 IWX_TLC_MNG_CH_WIDTH_160MHZ,
5520 IWX_TLC_MNG_CH_WIDTH_320MHZ,
5521 };
5522
5523 /**
5524 * @IWX_TLC_MNG_CHAIN_A_MSK: chain A
5525 * @IWX_TLC_MNG_CHAIN_B_MSK: chain B
5526 */
5527 #define IWX_TLC_MNG_CHAIN_A_MSK (1 << 0)
5528 #define IWX_TLC_MNG_CHAIN_B_MSK (1 << 1)
5529
5530 /**
5531 * enum iwx_tlc_mng_cfg_mode - supported modes
5532 * @IWX_TLC_MNG_MODE_CCK: enable CCK
5533 * @IWX_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT)
5534 * @IWX_TLC_MNG_MODE_NON_HT: enable non HT
5535 * @IWX_TLC_MNG_MODE_HT: enable HT
5536 * @IWX_TLC_MNG_MODE_VHT: enable VHT
5537 * @IWX_TLC_MNG_MODE_HE: enable HE
5538 * @IWX_TLC_MNG_MODE_EHT: enable EHT
5539 */
5540 enum iwx_tlc_mng_cfg_mode {
5541 IWX_TLC_MNG_MODE_CCK = 0,
5542 IWX_TLC_MNG_MODE_OFDM_NON_HT = IWX_TLC_MNG_MODE_CCK,
5543 IWX_TLC_MNG_MODE_NON_HT = IWX_TLC_MNG_MODE_CCK,
5544 IWX_TLC_MNG_MODE_HT,
5545 IWX_TLC_MNG_MODE_VHT,
5546 IWX_TLC_MNG_MODE_HE,
5547 IWX_TLC_MNG_MODE_EHT,
5548 };
5549
5550 /**
5551 * @IWX_TLC_MNG_HT_RATE_MCS0: index of MCS0
5552 * @IWX_TLC_MNG_HT_RATE_MCS1: index of MCS1
5553 * @IWX_TLC_MNG_HT_RATE_MCS2: index of MCS2
5554 * @IWX_TLC_MNG_HT_RATE_MCS3: index of MCS3
5555 * @IWX_TLC_MNG_HT_RATE_MCS4: index of MCS4
5556 * @IWX_TLC_MNG_HT_RATE_MCS5: index of MCS5
5557 * @IWX_TLC_MNG_HT_RATE_MCS6: index of MCS6
5558 * @IWX_TLC_MNG_HT_RATE_MCS7: index of MCS7
5559 * @IWX_TLC_MNG_HT_RATE_MCS8: index of MCS8
5560 * @IWX_TLC_MNG_HT_RATE_MCS9: index of MCS9
5561 * @IWX_TLC_MNG_HT_RATE_MCS10: index of MCS10
5562 * @IWX_TLC_MNG_HT_RATE_MCS11: index of MCS11
5563 * @IWX_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT
5564 */
5565 enum iwx_tlc_mng_ht_rates {
5566 IWX_TLC_MNG_HT_RATE_MCS0 = 0,
5567 IWX_TLC_MNG_HT_RATE_MCS1,
5568 IWX_TLC_MNG_HT_RATE_MCS2,
5569 IWX_TLC_MNG_HT_RATE_MCS3,
5570 IWX_TLC_MNG_HT_RATE_MCS4,
5571 IWX_TLC_MNG_HT_RATE_MCS5,
5572 IWX_TLC_MNG_HT_RATE_MCS6,
5573 IWX_TLC_MNG_HT_RATE_MCS7,
5574 IWX_TLC_MNG_HT_RATE_MCS8,
5575 IWX_TLC_MNG_HT_RATE_MCS9,
5576 IWX_TLC_MNG_HT_RATE_MCS10,
5577 IWX_TLC_MNG_HT_RATE_MCS11,
5578 IWX_TLC_MNG_HT_RATE_MAX = IWX_TLC_MNG_HT_RATE_MCS11,
5579 };
5580
5581 #define IWX_TLC_NSS_1 0
5582 #define IWX_TLC_NSS_2 1
5583 #define IWX_TLC_NSS_MAX 2
5584
5585
5586 /**
5587 * IWX_TLC_MCS_PER_BW - mcs index per BW
5588 * @IWX_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz
5589 * @IWX_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
5590 * @IWX_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
5591 * @IWX_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3
5592 * @IWX_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4
5593 */
5594 #define IWX_TLC_MCS_PER_BW_80 0
5595 #define IWX_TLC_MCS_PER_BW_160 1
5596 #define IWX_TLC_MCS_PER_BW_320 2
5597 #define IWX_TLC_MCS_PER_BW_NUM_V3 (IWX_TLC_MCS_PER_BW_160 + 1)
5598 #define IWX_TLC_MCS_PER_BW_NUM_V4 (IWX_TLC_MCS_PER_BW_320 + 1)
5599
5600 /**
5601 * struct iwx_tlc_config_cmd_v3 - TLC configuration version 3
5602 * @sta_id: station id
5603 * @reserved1: reserved
5604 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw
5605 * @mode: &enum iwx_tlc_mng_cfg_mode
5606 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK
5607 * @amsdu: 1 = TX amsdu is supported, 0 = not supported
5608 * @flags: bitmask of IWX_TLC_MNG_CFG_*
5609 * @non_ht_rates: bitmap of supported legacy rates
5610 * @ht_rates: MCS index 0 - 11, per <nss, channel-width>
5611 * pair (0 - 80mhz width and below, 1 - 160mhz).
5612 * @max_mpdu_len: max MPDU length, in bytes
5613 * @sgi_ch_width_supp: bitmap of SGI support per channel width
5614 * use (1 << IWX_TLC_MNG_CFG_CW_*)
5615 * @reserved2: reserved
5616 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
5617 * set zero for no limit.
5618 */
5619 struct iwx_tlc_config_cmd_v3 {
5620 uint8_t sta_id;
5621 uint8_t reserved1[3];
5622 uint8_t max_ch_width;
5623 uint8_t mode;
5624 uint8_t chains;
5625 uint8_t amsdu;
5626 uint16_t flags;
5627 uint16_t non_ht_rates;
5628 uint16_t ht_rates[IWX_TLC_NSS_MAX][IWX_TLC_MCS_PER_BW_NUM_V3];
5629 uint16_t max_mpdu_len;
5630 uint8_t sgi_ch_width_supp;
5631 uint8_t reserved2;
5632 uint32_t max_tx_op;
5633 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */
5634
5635 /**
5636 * struct iwx_tlc_config_cmd_v4 - TLC configuration
5637 * @sta_id: station id
5638 * @reserved1: reserved
5639 * @max_ch_width: max supported channel width from @enum iwx_tlc_mng_cfg_cw
5640 * @mode: &enum iwx_tlc_mng_cfg_mode
5641 * @chains: bitmask of IWX_TLC_MNG_CHAIN_*_MSK
5642 * @sgi_ch_width_supp: bitmap of SGI support per channel width
5643 * use (1 << IWX_TLC_MNG_CFG_CW_*)
5644 * @flags: bitmask of IWX_TLC_MNG_CFG_*
5645 * @non_ht_rates: bitmap of supported legacy rates
5646 * @ht_rates: MCS index 0 - 11, per <nss, channel-width>
5647 * pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz).
5648 * @max_mpdu_len: max MPDU length, in bytes
5649 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
5650 * set zero for no limit.
5651 */
5652 struct iwx_tlc_config_cmd_v4 {
5653 uint8_t sta_id;
5654 uint8_t reserved1[3];
5655 uint8_t max_ch_width;
5656 uint8_t mode;
5657 uint8_t chains;
5658 uint8_t sgi_ch_width_supp;
5659 uint16_t flags;
5660 uint16_t non_ht_rates;
5661 uint16_t ht_rates[IWX_TLC_NSS_MAX][IWX_TLC_MCS_PER_BW_NUM_V4];
5662 uint16_t max_mpdu_len;
5663 uint16_t max_tx_op;
5664 } __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */
5665
5666 /**
5667 * @IWX_TLC_NOTIF_FLAG_RATE: last initial rate update
5668 * @IWX_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update
5669 */
5670 #define IWX_TLC_NOTIF_FLAG_RATE (1 << 0)
5671 #define IWX_TLC_NOTIF_FLAG_AMSDU (1 << 1)
5672
5673 /**
5674 * struct iwx_tlc_update_notif - TLC notification from FW
5675 * @sta_id: station id
5676 * @reserved: reserved
5677 * @flags: bitmap of notifications reported
5678 * @rate: current initial rate; using rate_n_flags version 1 if notification
5679 * version is < 3 at run-time, else rate_n_flags version 2
5680 * @amsdu_size: Max AMSDU size, in bytes
5681 * @amsdu_enabled: bitmap for per-TID AMSDU enablement
5682 */
5683 struct iwx_tlc_update_notif {
5684 uint8_t sta_id;
5685 uint8_t reserved[3];
5686 uint32_t flags;
5687 uint32_t rate;
5688 uint32_t amsdu_size;
5689 uint32_t amsdu_enabled;
5690 } __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2 */
5691
5692 /* Antenna flags. */
5693 #define IWX_ANT_A (1 << 0)
5694 #define IWX_ANT_B (1 << 1)
5695 #define IWX_ANT_C (1 << 2)
5696 /* Shortcuts. */
5697 #define IWX_ANT_AB (IWX_ANT_A | IWX_ANT_B)
5698 #define IWX_ANT_BC (IWX_ANT_B | IWX_ANT_C)
5699 #define IWX_ANT_ABC (IWX_ANT_A | IWX_ANT_B | IWX_ANT_C)
5700
5701 /*
5702 * TX command security control
5703 */
5704 #define IWX_TX_CMD_SEC_WEP 0x01
5705 #define IWX_TX_CMD_SEC_CCM 0x02
5706 #define IWX_TX_CMD_SEC_TKIP 0x03
5707 #define IWX_TX_CMD_SEC_EXT 0x04
5708 #define IWX_TX_CMD_SEC_MSK 0x07
5709 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_POS 6
5710 #define IWX_TX_CMD_SEC_WEP_KEY_IDX_MSK 0xc0
5711 #define IWX_TX_CMD_SEC_KEY128 0x08
5712
5713 /* TODO: how does these values are OK with only 16 bit variable??? */
5714 /*
5715 * TX command next frame info
5716 *
5717 * bits 0:2 - security control (IWX_TX_CMD_SEC_*)
5718 * bit 3 - immediate ACK required
5719 * bit 4 - rate is taken from STA table
5720 * bit 5 - frame belongs to BA stream
5721 * bit 6 - immediate BA response expected
5722 * bit 7 - unused
5723 * bits 8:15 - Station ID
5724 * bits 16:31 - rate
5725 */
5726 #define IWX_TX_CMD_NEXT_FRAME_ACK_MSK (0x8)
5727 #define IWX_TX_CMD_NEXT_FRAME_STA_RATE_MSK (0x10)
5728 #define IWX_TX_CMD_NEXT_FRAME_BA_MSK (0x20)
5729 #define IWX_TX_CMD_NEXT_FRAME_IMM_BA_RSP_MSK (0x40)
5730 #define IWX_TX_CMD_NEXT_FRAME_FLAGS_MSK (0xf8)
5731 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_MSK (0xff00)
5732 #define IWX_TX_CMD_NEXT_FRAME_STA_ID_POS (8)
5733 #define IWX_TX_CMD_NEXT_FRAME_RATE_MSK (0xffff0000)
5734 #define IWX_TX_CMD_NEXT_FRAME_RATE_POS (16)
5735
5736 /*
5737 * TX command Frame life time in us - to be written in pm_frame_timeout
5738 */
5739 #define IWX_TX_CMD_LIFE_TIME_INFINITE 0xFFFFFFFF
5740 #define IWX_TX_CMD_LIFE_TIME_DEFAULT 2000000 /* 2000 ms*/
5741 #define IWX_TX_CMD_LIFE_TIME_PROBE_RESP 40000 /* 40 ms */
5742 #define IWX_TX_CMD_LIFE_TIME_EXPIRED_FRAME 0
5743
5744 /*
5745 * TID for non QoS frames - to be written in tid_tspec
5746 */
5747 #define IWX_TID_NON_QOS 0
5748
5749 /*
5750 * Limits on the retransmissions - to be written in {data,rts}_retry_limit
5751 */
5752 #define IWX_DEFAULT_TX_RETRY 15
5753 #define IWX_MGMT_DFAULT_RETRY_LIMIT 3
5754 #define IWX_RTS_DFAULT_RETRY_LIMIT 3
5755 #define IWX_BAR_DFAULT_RETRY_LIMIT 60
5756 #define IWX_LOW_RETRY_LIMIT 7
5757
5758 /*
5759 * The FH will write back to the first TB only, so we need to copy some data
5760 * into the buffer regardless of whether it should be mapped or not.
5761 * This indicates how big the first TB must be to include the scratch buffer
5762 * and the assigned PN.
5763 * Since PN location is 8 bytes at offset 12, it's 20 now.
5764 * If we make it bigger then allocations will be bigger and copy slower, so
5765 * that's probably not useful.
5766 */
5767 #define IWX_FIRST_TB_SIZE 20
5768 #define IWX_FIRST_TB_SIZE_ALIGN ((IWX_FIRST_TB_SIZE + (64 - 1)) & ~(64 - 1))
5769
5770 /**
5771 * %iwx_tx_cmd offload_assist values
5772 * @TX_CMD_OFFLD_IP_HDR: offset to start of IP header (in words)
5773 * from mac header end. For normal case it is 4 words for SNAP.
5774 * note: tx_cmd, mac header and pad are not counted in the offset.
5775 * This is used to help the offload in case there is tunneling such as
5776 * IPv6 in IPv4, in such case the ip header offset should point to the
5777 * inner ip header and IPv4 checksum of the external header should be
5778 * calculated by driver.
5779 * @TX_CMD_OFFLD_L4_EN: enable TCP/UDP checksum
5780 * @TX_CMD_OFFLD_L3_EN: enable IP header checksum
5781 * @TX_CMD_OFFLD_MH_SIZE: size of the mac header in words. Includes the IV
5782 * field. Doesn't include the pad.
5783 * @TX_CMD_OFFLD_PAD: mark 2-byte pad was inserted after the mac header for
5784 * alignment
5785 * @TX_CMD_OFFLD_AMSDU: mark TX command is A-MSDU
5786 */
5787 #define IWX_TX_CMD_OFFLD_IP_HDR(x) ((x) << 0)
5788 #define IWX_TX_CMD_OFFLD_L4_EN (1 << 6)
5789 #define IWX_TX_CMD_OFFLD_L3_EN (1 << 7)
5790 #define IWX_TX_CMD_OFFLD_MH_SIZE(x) ((x) << 8)
5791 #define IWX_TX_CMD_OFFLD_PAD (1 << 13)
5792 #define IWX_TX_CMD_OFFLD_AMSDU (1 << 14)
5793 #define IWX_TX_CMD_OFFLD_MH_MASK 0x1f
5794 #define IWX_TX_CMD_OFFLD_IP_HDR_MASK 0x3f
5795
5796 struct iwx_dram_sec_info {
5797 uint32_t pn_low;
5798 uint16_t pn_high;
5799 uint16_t aux_info;
5800 } __packed; /* DRAM_SEC_INFO_API_S_VER_1 */
5801
5802 /**
5803 * bitmasks for tx_flags in TX command for 22000
5804 * @IWX_TX_FLAGS_CMD_RATE: use rate from the TX command
5805 * @IWX_TX_FLAGS_ENCRYPT_DIS: frame should not be encrypted, even if it belongs
5806 * to a secured STA
5807 * @IWX_TX_FLAGS_HIGH_PRI: high priority frame (like EAPOL) - can affect rate
5808 * selection, retry limits and BT kill
5809 */
5810 /* Valid for TX_FLAGS_BITS_API_S_VER_3: */
5811 #define IWX_TX_FLAGS_CMD_RATE (1 << 0)
5812 #define IWX_TX_FLAGS_ENCRYPT_DIS (1 << 1)
5813 #define IWX_TX_FLAGS_HIGH_PRI (1 << 2)
5814 /* Valid for TX_FLAGS_BITS_API_S_VER_4 and above: */
5815 #define IWX_TX_FLAGS_RTS (1 << 3)
5816 #define IWX_TX_FLAGS_CTS (1 << 4)
5817 /* TX_FLAGS_BITS_API_S_VER_4 */
5818
5819 /**
5820 * struct iwx_tx_cmd_gen2 - TX command struct to FW for 22000 devices
5821 * ( TX_CMD = 0x1c )
5822 * @len: in bytes of the payload, see below for details
5823 * @offload_assist: TX offload configuration
5824 * @flags: combination of TX_FLAGS_*
5825 * @dram_info: FW internal DRAM storage
5826 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
5827 * cleared. Combination of RATE_MCS_*
5828 * @hdr: 802.11 header
5829 */
5830 struct iwx_tx_cmd_gen2 {
5831 uint16_t len;
5832 uint16_t offload_assist;
5833 uint32_t flags;
5834 struct iwx_dram_sec_info dram_info;
5835 uint32_t rate_n_flags;
5836 struct ieee80211_frame hdr[0];
5837 } __packed; /* TX_CMD_API_S_VER_7,
5838 TX_CMD_API_S_VER_9 */
5839
5840 /**
5841 * struct iwx_tx_cmd_gen3 - TX command struct to FW for AX210+ devices
5842 * ( TX_CMD = 0x1c )
5843 * @len: in bytes of the payload, see below for details
5844 * @flags: combination of TX_FLAGS_*
5845 * @offload_assist: TX offload configuration
5846 * @dram_info: FW internal DRAM storage
5847 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
5848 * cleared. Combination of RATE_MCS_*
5849 * @reserved: reserved
5850 * @hdr: 802.11 header
5851 */
5852 struct iwx_tx_cmd_gen3 {
5853 uint16_t len;
5854 uint16_t flags;
5855 uint32_t offload_assist;
5856 struct iwx_dram_sec_info dram_info;
5857 uint32_t rate_n_flags;
5858 uint8_t reserved[8];
5859 struct ieee80211_frame hdr[];
5860 } __packed; /* TX_CMD_API_S_VER_8,
5861 TX_CMD_API_S_VER_10 */
5862
5863 /*
5864 * TX response related data
5865 */
5866
5867 /*
5868 * status that is returned by the fw after attempts to Tx
5869 * @IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH: mismatch between color of Tx cmd and
5870 * STA table
5871 * Valid only if frame_count =1
5872 */
5873 #define IWX_TX_STATUS_MSK 0x000000ff
5874 #define IWX_TX_STATUS_SUCCESS 0x01
5875 #define IWX_TX_STATUS_DIRECT_DONE 0x02
5876 /* postpone TX */
5877 #define IWX_TX_STATUS_POSTPONE_DELAY 0x40
5878 #define IWX_TX_STATUS_POSTPONE_FEW_BYTES 0x41
5879 #define IWX_TX_STATUS_POSTPONE_BT_PRIO 0x42
5880 #define IWX_TX_STATUS_POSTPONE_QUIET_PERIOD 0x43
5881 #define IWX_TX_STATUS_POSTPONE_CALC_TTAK 0x44
5882 /* abort TX */
5883 #define IWX_TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY 0x81
5884 #define IWX_TX_STATUS_FAIL_SHORT_LIMIT 0x82
5885 #define IWX_TX_STATUS_FAIL_LONG_LIMIT 0x83
5886 #define IWX_TX_STATUS_FAIL_UNDERRUN 0x84
5887 #define IWX_TX_STATUS_FAIL_DRAIN_FLOW 0x85
5888 #define IWX_TX_STATUS_FAIL_RFKILL_FLUSH 0x86
5889 #define IWX_TX_STATUS_FAIL_LIFE_EXPIRE 0x87
5890 #define IWX_TX_STATUS_FAIL_DEST_PS 0x88
5891 #define IWX_TX_STATUS_FAIL_HOST_ABORTED 0x89
5892 #define IWX_TX_STATUS_FAIL_BT_RETRY 0x8a
5893 #define IWX_TX_STATUS_FAIL_STA_INVALID 0x8b
5894 #define IWX_TX_STATUS_FAIL_FRAG_DROPPED 0x8c
5895 #define IWX_TX_STATUS_FAIL_TID_DISABLE 0x8d
5896 #define IWX_TX_STATUS_FAIL_FIFO_FLUSHED 0x8e
5897 #define IWX_TX_STATUS_FAIL_SMALL_CF_POLL 0x8f
5898 #define IWX_TX_STATUS_FAIL_FW_DROP 0x90
5899 #define IWX_TX_STATUS_FAIL_STA_COLOR_MISMATCH 0x91
5900 #define IWX_TX_STATUS_INTERNAL_ABORT 0x92
5901 #define IWX_TX_MODE_MSK 0x00000f00
5902 #define IWX_TX_MODE_NO_BURST 0x00000000
5903 #define IWX_TX_MODE_IN_BURST_SEQ 0x00000100
5904 #define IWX_TX_MODE_FIRST_IN_BURST 0x00000200
5905 #define IWX_TX_QUEUE_NUM_MSK 0x0001f000
5906 #define IWX_TX_NARROW_BW_MSK 0x00060000
5907 #define IWX_TX_NARROW_BW_1DIV2 0x00020000
5908 #define IWX_TX_NARROW_BW_1DIV4 0x00040000
5909 #define IWX_TX_NARROW_BW_1DIV8 0x00060000
5910
5911 /*
5912 * TX aggregation status
5913 * @IWX_AGG_TX_STATE_TRY_CNT_MSK: Retry count for 1st frame in aggregation (retries
5914 * occur if tx failed for this frame when it was a member of a previous
5915 * aggregation block). If rate scaling is used, retry count indicates the
5916 * rate table entry used for all frames in the new agg.
5917 * @IWX_AGG_TX_STATE_SEQ_NUM_MSK: Command ID and sequence number of Tx command for
5918 * this frame
5919 */
5920 #define IWX_AGG_TX_STATE_STATUS_MSK 0x0fff
5921 #define IWX_AGG_TX_STATE_TRANSMITTED 0x0000
5922 #define IWX_AGG_TX_STATE_UNDERRUN 0x0001
5923 #define IWX_AGG_TX_STATE_BT_PRIO 0x0002
5924 #define IWX_AGG_TX_STATE_FEW_BYTES 0x0004
5925 #define IWX_AGG_TX_STATE_ABORT 0x0008
5926 #define IWX_AGG_TX_STATE_LAST_SENT_TTL 0x0010
5927 #define IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT 0x0020
5928 #define IWX_AGG_TX_STATE_LAST_SENT_BT_KILL 0x0040
5929 #define IWX_AGG_TX_STATE_SCD_QUERY 0x0080
5930 #define IWX_AGG_TX_STATE_TEST_BAD_CRC32 0x0100
5931 #define IWX_AGG_TX_STATE_RESPONSE 0x01ff
5932 #define IWX_AGG_TX_STATE_DUMP_TX 0x0200
5933 #define IWX_AGG_TX_STATE_DELAY_TX 0x0400
5934 #define IWX_AGG_TX_STATE_TRY_CNT_POS 12
5935 #define IWX_AGG_TX_STATE_TRY_CNT_MSK (0xf << IWX_AGG_TX_STATE_TRY_CNT_POS)
5936
5937 #define IWX_AGG_TX_STATE_LAST_SENT_MSK (IWX_AGG_TX_STATE_LAST_SENT_TTL| \
5938 IWX_AGG_TX_STATE_LAST_SENT_TRY_CNT| \
5939 IWX_AGG_TX_STATE_LAST_SENT_BT_KILL)
5940
5941 /*
5942 * The mask below describes a status where we are absolutely sure that the MPDU
5943 * wasn't sent. For BA/Underrun we cannot be that sure. All we know that we've
5944 * written the bytes to the TXE, but we know nothing about what the DSP did.
5945 */
5946 #define IWX_AGG_TX_STAT_FRAME_NOT_SENT (IWX_AGG_TX_STATE_FEW_BYTES | \
5947 IWX_AGG_TX_STATE_ABORT | \
5948 IWX_AGG_TX_STATE_SCD_QUERY)
5949
5950 /*
5951 * IWX_REPLY_TX = 0x1c (response)
5952 *
5953 * This response may be in one of two slightly different formats, indicated
5954 * by the frame_count field:
5955 *
5956 * 1) No aggregation (frame_count == 1). This reports Tx results for a single
5957 * frame. Multiple attempts, at various bit rates, may have been made for
5958 * this frame.
5959 *
5960 * 2) Aggregation (frame_count > 1). This reports Tx results for two or more
5961 * frames that used block-acknowledge. All frames were transmitted at
5962 * same rate. Rate scaling may have been used if first frame in this new
5963 * agg block failed in previous agg block(s).
5964 *
5965 * Note that, for aggregation, ACK (block-ack) status is not delivered
5966 * here; block-ack has not been received by the time the device records
5967 * this status.
5968 * This status relates to reasons the tx might have been blocked or aborted
5969 * within the device, rather than whether it was received successfully by
5970 * the destination station.
5971 */
5972
5973 /**
5974 * struct iwx_agg_tx_status - per packet TX aggregation status
5975 * @status: enum iwx_tx_agg_status
5976 * @sequence: Sequence # for this frame's Tx cmd (not SSN!)
5977 */
5978 struct iwx_agg_tx_status {
5979 uint16_t status;
5980 uint16_t sequence;
5981 } __packed;
5982
5983 /*
5984 * definitions for initial rate index field
5985 * bits [3:0] initial rate index
5986 * bits [6:4] rate table color, used for the initial rate
5987 * bit-7 invalid rate indication
5988 */
5989 #define IWX_TX_RES_INIT_RATE_INDEX_MSK 0x0f
5990 #define IWX_TX_RES_RATE_TABLE_COLOR_MSK 0x70
5991 #define IWX_TX_RES_INV_RATE_INDEX_MSK 0x80
5992
5993 #define IWX_TX_RES_GET_TID(_ra_tid) ((_ra_tid) & 0x0f)
5994 #define IWX_TX_RES_GET_RA(_ra_tid) ((_ra_tid) >> 4)
5995
5996 /**
5997 * struct iwx_tx_resp_v3 - notifies that fw is TXing a packet
5998 * ( IWX_REPLY_TX = 0x1c )
5999 * @frame_count: 1 no aggregation, >1 aggregation
6000 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
6001 * @failure_rts: num of failures due to unsuccessful RTS
6002 * @failure_frame: num failures due to no ACK (unused for agg)
6003 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
6004 * Tx of all the batch. IWX_RATE_MCS_*
6005 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
6006 * for agg: RTS + CTS + aggregation tx time + block-ack time.
6007 * in usec.
6008 * @pa_status: tx power info
6009 * @pa_integ_res_a: tx power info
6010 * @pa_integ_res_b: tx power info
6011 * @pa_integ_res_c: tx power info
6012 * @measurement_req_id: tx power info
6013 * @tfd_info: TFD information set by the FH
6014 * @seq_ctl: sequence control from the Tx cmd
6015 * @byte_cnt: byte count from the Tx cmd
6016 * @tlc_info: TLC rate info
6017 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
6018 * @frame_ctrl: frame control
6019 * @status: for non-agg: frame status IWX_TX_STATUS_*
6020 * for agg: status of 1st frame, IWX_AGG_TX_STATE_*; other frame status fields
6021 * follow this one, up to frame_count.
6022 *
6023 * After the array of statuses comes the SSN of the SCD. Look at
6024 * %iwx_get_scd_ssn for more details.
6025 */
6026 struct iwx_tx_resp_v3 {
6027 uint8_t frame_count;
6028 uint8_t bt_kill_count;
6029 uint8_t failure_rts;
6030 uint8_t failure_frame;
6031 uint32_t initial_rate;
6032 uint16_t wireless_media_time;
6033
6034 uint8_t pa_status;
6035 uint8_t pa_integ_res_a[3];
6036 uint8_t pa_integ_res_b[3];
6037 uint8_t pa_integ_res_c[3];
6038 uint16_t measurement_req_id;
6039 uint16_t reserved;
6040
6041 uint32_t tfd_info;
6042 uint16_t seq_ctl;
6043 uint16_t byte_cnt;
6044 uint8_t tlc_info;
6045 uint8_t ra_tid;
6046 uint16_t frame_ctrl;
6047
6048 struct iwx_agg_tx_status status;
6049 } __packed; /* IWX_TX_RSP_API_S_VER_3 */
6050
6051 /**
6052 * struct iwx_tx_resp - notifies that fw is TXing a packet
6053 * ( REPLY_TX = 0x1c )
6054 * @frame_count: 1 no aggregation, >1 aggregation
6055 * @bt_kill_count: num of times blocked by bluetooth (unused for agg)
6056 * @failure_rts: num of failures due to unsuccessful RTS
6057 * @failure_frame: num failures due to no ACK (unused for agg)
6058 * @initial_rate: for non-agg: rate of the successful Tx. For agg: rate of the
6059 * Tx of all the batch. RATE_MCS_*
6060 * @wireless_media_time: for non-agg: RTS + CTS + frame tx attempts time + ACK.
6061 * for agg: RTS + CTS + aggregation tx time + block-ack time.
6062 * in usec.
6063 * @pa_status: tx power info
6064 * @pa_integ_res_a: tx power info
6065 * @pa_integ_res_b: tx power info
6066 * @pa_integ_res_c: tx power info
6067 * @measurement_req_id: tx power info
6068 * @reduced_tpc: transmit power reduction used
6069 * @reserved: reserved
6070 * @tfd_info: TFD information set by the FH
6071 * @seq_ctl: sequence control from the Tx cmd
6072 * @byte_cnt: byte count from the Tx cmd
6073 * @tlc_info: TLC rate info
6074 * @ra_tid: bits [3:0] = ra, bits [7:4] = tid
6075 * @frame_ctrl: frame control
6076 * @tx_queue: TX queue for this response
6077 * @reserved2: reserved for padding/alignment
6078 * @status: for non-agg: frame status TX_STATUS_*
6079 * For version 6 TX response isn't received for aggregation at all.
6080 *
6081 * After the array of statuses comes the SSN of the SCD. Look at
6082 * %iwl_mvm_get_scd_ssn for more details.
6083 */
6084 struct iwx_tx_resp {
6085 uint8_t frame_count;
6086 uint8_t bt_kill_count;
6087 uint8_t failure_rts;
6088 uint8_t failure_frame;
6089 uint32_t initial_rate;
6090 uint16_t wireless_media_time;
6091
6092 uint8_t pa_status;
6093 uint8_t pa_integ_res_a[3];
6094 uint8_t pa_integ_res_b[3];
6095 uint8_t pa_integ_res_c[3];
6096 uint16_t measurement_req_id;
6097 uint8_t reduced_tpc;
6098 uint8_t reserved;
6099
6100 uint32_t tfd_info;
6101 uint16_t seq_ctl;
6102 uint16_t byte_cnt;
6103 uint8_t tlc_info;
6104 uint8_t ra_tid;
6105 uint16_t frame_ctrl;
6106 uint16_t tx_queue;
6107 uint16_t reserved2;
6108 struct iwx_agg_tx_status status;
6109 } __packed; /* TX_RSP_API_S_VER_6 */
6110
6111 /**
6112 * struct iwx_compressed_ba_tfd - progress of a TFD queue
6113 * @q_num: TFD queue number
6114 * @tfd_index: Index of first un-acked frame in the TFD queue
6115 * @scd_queue: For debug only - the physical queue the TFD queue is bound to
6116 * @tid: TID of the queue (0-7)
6117 * @reserved: reserved for alignment
6118 */
6119 struct iwx_compressed_ba_tfd {
6120 uint16_t q_num;
6121 uint16_t tfd_index;
6122 uint8_t scd_queue;
6123 uint8_t tid;
6124 uint8_t reserved[2];
6125 } __packed; /* COMPRESSED_BA_TFD_API_S_VER_1 */
6126
6127 /**
6128 * struct iwx_compressed_ba_ratid - progress of a RA TID queue
6129 * @q_num: RA TID queue number
6130 * @tid: TID of the queue
6131 * @ssn: BA window current SSN
6132 */
6133 struct iwx_compressed_ba_ratid {
6134 uint8_t q_num;
6135 uint8_t tid;
6136 uint16_t ssn;
6137 } __packed; /* COMPRESSED_BA_RATID_API_S_VER_1 */
6138
6139 /*
6140 * enum iwx_ba_resp_flags - TX aggregation status
6141 * @IWX_MVM_BA_RESP_TX_AGG: generated due to BA
6142 * @IWX_MVM_BA_RESP_TX_BAR: generated due to BA after BAR
6143 * @IWX_MVM_BA_RESP_TX_AGG_FAIL: aggregation didn't receive BA
6144 * @IWX_MVM_BA_RESP_TX_UNDERRUN: aggregation got underrun
6145 * @IWX_MVM_BA_RESP_TX_BT_KILL: aggregation got BT-kill
6146 * @IWX_MVM_BA_RESP_TX_DSP_TIMEOUT: aggregation didn't finish within the
6147 * expected time
6148 */
6149 enum iwx_ba_resp_flags {
6150 IWX_MVM_BA_RESP_TX_AGG,
6151 IWX_MVM_BA_RESP_TX_BAR,
6152 IWX_MVM_BA_RESP_TX_AGG_FAIL,
6153 IWX_MVM_BA_RESP_TX_UNDERRUN,
6154 IWX_MVM_BA_RESP_TX_BT_KILL,
6155 IWX_MVM_BA_RESP_TX_DSP_TIMEOUT
6156 };
6157
6158 /**
6159 * struct iwx_compressed_ba_notif - notifies about reception of BA
6160 * ( BA_NOTIF = 0xc5 )
6161 * @flags: status flag, see the &iwx_ba_resp_flags
6162 * @sta_id: Index of recipient (BA-sending) station in fw's station table
6163 * @reduced_txp: power reduced according to TPC. This is the actual value and
6164 * not a copy from the LQ command. Thus, if not the first rate was used
6165 * for Tx-ing then this value will be set to 0 by FW.
6166 * @tlc_rate_info: TLC rate info, initial rate index, TLC table color
6167 * @retry_cnt: retry count
6168 * @query_byte_cnt: SCD query byte count
6169 * @query_frame_cnt: SCD query frame count
6170 * @txed: number of frames sent in the aggregation (all-TIDs)
6171 * @done: number of frames that were Acked by the BA (all-TIDs)
6172 * @reserved: reserved (for alignment)
6173 * @wireless_time: Wireless-media time
6174 * @tx_rate: the rate the aggregation was sent at
6175 * @tfd_cnt: number of TFD-Q elements
6176 * @ra_tid_cnt: number of RATID-Q elements
6177 * @tfd: array of TFD queue status updates. See &iwx_compressed_ba_tfd
6178 * for details. Length in @tfd_cnt.
6179 * @ra_tid: array of RA-TID queue status updates. For debug purposes only. See
6180 * &iwx_compressed_ba_ratid for more details. Length in @ra_tid_cnt.
6181 */
6182 struct iwx_compressed_ba_notif {
6183 uint32_t flags;
6184 uint8_t sta_id;
6185 uint8_t reduced_txp;
6186 uint8_t tlc_rate_info;
6187 uint8_t retry_cnt;
6188 uint32_t query_byte_cnt;
6189 uint16_t query_frame_cnt;
6190 uint16_t txed;
6191 uint16_t done;
6192 uint16_t reserved;
6193 uint32_t wireless_time;
6194 uint32_t tx_rate;
6195 uint16_t tfd_cnt;
6196 uint16_t ra_tid_cnt;
6197 struct iwx_compressed_ba_ratid ra_tid[0];
6198 struct iwx_compressed_ba_tfd tfd[];
6199 } __packed; /* COMPRESSED_BA_RES_API_S_VER_4 */
6200
6201
6202 struct iwx_beacon_notif {
6203 struct iwx_tx_resp_v3 beacon_notify_hdr;
6204 uint64_t tsf;
6205 uint32_t ibss_mgr_status;
6206 } __packed;
6207
6208 /**
6209 * dump (flush) control flags
6210 * @IWX_DUMP_TX_FIFO_FLUSH: Dump MSDUs until the FIFO is empty
6211 * and the TFD queues are empty.
6212 */
6213 #define IWX_DUMP_TX_FIFO_FLUSH (1 << 1)
6214
6215 /**
6216 * struct iwx_tx_path_flush_cmd -- queue/FIFO flush command
6217 * @queues_ctl: bitmap of queues to flush
6218 * @flush_ctl: control flags
6219 * @reserved: reserved
6220 */
6221 struct iwx_tx_path_flush_cmd_v1 {
6222 uint32_t queues_ctl;
6223 uint16_t flush_ctl;
6224 uint16_t reserved;
6225 } __packed; /* IWX_TX_PATH_FLUSH_CMD_API_S_VER_1 */
6226
6227 /**
6228 * struct iwl_tx_path_flush_cmd -- queue/FIFO flush command
6229 * @sta_id: station ID to flush
6230 * @tid_mask: TID mask to flush
6231 * @reserved: reserved
6232 */
6233 struct iwx_tx_path_flush_cmd {
6234 uint32_t sta_id;
6235 uint16_t tid_mask;
6236 uint16_t reserved;
6237 } __packed; /* TX_PATH_FLUSH_CMD_API_S_VER_2 */
6238
6239 #define IWX_TX_FLUSH_QUEUE_RSP 16
6240
6241 /**
6242 * struct iwx_flush_queue_info - virtual flush queue info
6243 * @queue_num: virtual queue id
6244 * @read_before_flush: read pointer before flush
6245 * @read_after_flush: read pointer after flush
6246 */
6247 struct iwx_flush_queue_info {
6248 uint16_t tid;
6249 uint16_t queue_num;
6250 uint16_t read_before_flush;
6251 uint16_t read_after_flush;
6252 } __packed; /* TFDQ_FLUSH_INFO_API_S_VER_1 */
6253
6254 /**
6255 * struct iwx_tx_path_flush_cmd_rsp -- queue/FIFO flush command response
6256 * @num_flushed_queues: number of queues in queues array
6257 * @queues: all flushed queues
6258 */
6259 struct iwx_tx_path_flush_cmd_rsp {
6260 uint16_t sta_id;
6261 uint16_t num_flushed_queues;
6262 struct iwx_flush_queue_info queues[IWX_TX_FLUSH_QUEUE_RSP];
6263 } __packed; /* TX_PATH_FLUSH_CMD_RSP_API_S_VER_1 */
6264
6265
6266 /**
6267 * iwx_get_scd_ssn - returns the SSN of the SCD
6268 * @tx_resp: the Tx response from the fw (agg or non-agg)
6269 *
6270 * When the fw sends an AMPDU, it fetches the MPDUs one after the other. Since
6271 * it can't know that everything will go well until the end of the AMPDU, it
6272 * can't know in advance the number of MPDUs that will be sent in the current
6273 * batch. This is why it writes the agg Tx response while it fetches the MPDUs.
6274 * Hence, it can't know in advance what the SSN of the SCD will be at the end
6275 * of the batch. This is why the SSN of the SCD is written at the end of the
6276 * whole struct at a variable offset. This function knows how to cope with the
6277 * variable offset and returns the SSN of the SCD.
6278 */
iwx_get_scd_ssn(struct iwx_tx_resp * tx_resp)6279 static inline uint32_t iwx_get_scd_ssn(struct iwx_tx_resp *tx_resp)
6280 {
6281 return le32_to_cpup((uint32_t *)&tx_resp->status +
6282 tx_resp->frame_count) & 0xfff;
6283 }
6284
6285 /**
6286 * struct iwx_scd_txq_cfg_cmd - New txq hw scheduler config command
6287 * @token:
6288 * @sta_id: station id
6289 * @tid:
6290 * @scd_queue: scheduler queue to config
6291 * @enable: 1 queue enable, 0 queue disable
6292 * @aggregate: 1 aggregated queue, 0 otherwise
6293 * @tx_fifo: %enum iwx_tx_fifo
6294 * @window: BA window size
6295 * @ssn: SSN for the BA agreement
6296 */
6297 struct iwx_scd_txq_cfg_cmd {
6298 uint8_t token;
6299 uint8_t sta_id;
6300 uint8_t tid;
6301 uint8_t scd_queue;
6302 uint8_t enable;
6303 uint8_t aggregate;
6304 uint8_t tx_fifo;
6305 uint8_t window;
6306 uint16_t ssn;
6307 uint16_t reserved;
6308 } __packed; /* SCD_QUEUE_CFG_CMD_API_S_VER_1 */
6309
6310 /**
6311 * struct iwx_scd_txq_cfg_rsp
6312 * @token: taken from the command
6313 * @sta_id: station id from the command
6314 * @tid: tid from the command
6315 * @scd_queue: scd_queue from the command
6316 */
6317 struct iwx_scd_txq_cfg_rsp {
6318 uint8_t token;
6319 uint8_t sta_id;
6320 uint8_t tid;
6321 uint8_t scd_queue;
6322 } __packed; /* SCD_QUEUE_CFG_RSP_API_S_VER_1 */
6323
6324
6325 /* Scan Commands, Responses, Notifications */
6326
6327 /* Max number of IEs for direct SSID scans in a command */
6328 #define IWX_PROBE_OPTION_MAX 20
6329
6330 /**
6331 * struct iwx_ssid_ie - directed scan network information element
6332 *
6333 * Up to 20 of these may appear in IWX_REPLY_SCAN_CMD,
6334 * selected by "type" bit field in struct iwx_scan_channel;
6335 * each channel may select different ssids from among the 20 entries.
6336 * SSID IEs get transmitted in reverse order of entry.
6337 */
6338 struct iwx_ssid_ie {
6339 uint8_t id;
6340 uint8_t len;
6341 uint8_t ssid[IEEE80211_NWID_LEN];
6342 } __packed; /* IWX_SCAN_DIRECT_SSID_IE_API_S_VER_1 */
6343
6344 /* scan offload */
6345 #define IWX_SCAN_MAX_BLACKLIST_LEN 64
6346 #define IWX_SCAN_SHORT_BLACKLIST_LEN 16
6347 #define IWX_SCAN_MAX_PROFILES 11
6348 #define IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE 512
6349
6350 /* Default watchdog (in MS) for scheduled scan iteration */
6351 #define IWX_SCHED_SCAN_WATCHDOG cpu_to_le16(15000)
6352
6353 #define IWX_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
6354 #define IWX_CAN_ABORT_STATUS 1
6355
6356 #define IWX_FULL_SCAN_MULTIPLIER 5
6357 #define IWX_FAST_SCHED_SCAN_ITERATIONS 3
6358 #define IWX_MAX_SCHED_SCAN_PLANS 2
6359
6360 /**
6361 * iwx_scan_schedule_lmac - schedule of scan offload
6362 * @delay: delay between iterations, in seconds.
6363 * @iterations: num of scan iterations
6364 * @full_scan_mul: number of partial scans before each full scan
6365 */
6366 struct iwx_scan_schedule_lmac {
6367 uint16_t delay;
6368 uint8_t iterations;
6369 uint8_t full_scan_mul;
6370 } __packed; /* SCAN_SCHEDULE_API_S */
6371
6372 /**
6373 * iwx_scan_req_tx_cmd - SCAN_REQ_TX_CMD_API_S
6374 * @tx_flags: combination of TX_CMD_FLG_*
6375 * @rate_n_flags: rate for *all* Tx attempts, if TX_CMD_FLG_STA_RATE_MSK is
6376 * cleared. Combination of RATE_MCS_*
6377 * @sta_id: index of destination station in FW station table
6378 * @reserved: for alignment and future use
6379 */
6380 struct iwx_scan_req_tx_cmd {
6381 uint32_t tx_flags;
6382 uint32_t rate_n_flags;
6383 uint8_t sta_id;
6384 uint8_t reserved[3];
6385 } __packed;
6386
6387 #define IWX_UNIFIED_SCAN_CHANNEL_FULL (1 << 27)
6388 #define IWX_UNIFIED_SCAN_CHANNEL_PARTIAL (1 << 28)
6389
6390 /**
6391 * iwx_scan_channel_cfg_lmac - SCAN_CHANNEL_CFG_S_VER2
6392 * @flags: bits 1-20: directed scan to i'th ssid
6393 * other bits &enum iwx_scan_channel_flags_lmac
6394 * @channel_number: channel number 1-13 etc
6395 * @iter_count: scan iteration on this channel
6396 * @iter_interval: interval in seconds between iterations on one channel
6397 */
6398 struct iwx_scan_channel_cfg_lmac {
6399 uint32_t flags;
6400 uint16_t channel_num;
6401 uint16_t iter_count;
6402 uint32_t iter_interval;
6403 } __packed;
6404
6405 /*
6406 * iwx_scan_probe_segment - PROBE_SEGMENT_API_S_VER_1
6407 * @offset: offset in the data block
6408 * @len: length of the segment
6409 */
6410 struct iwx_scan_probe_segment {
6411 uint16_t offset;
6412 uint16_t len;
6413 } __packed;
6414
6415 /* iwx_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_2
6416 * @mac_header: first (and common) part of the probe
6417 * @band_data: band specific data
6418 * @common_data: last (and common) part of the probe
6419 * @buf: raw data block
6420 */
6421 struct iwx_scan_probe_req_v1 {
6422 struct iwx_scan_probe_segment mac_header;
6423 struct iwx_scan_probe_segment band_data[2];
6424 struct iwx_scan_probe_segment common_data;
6425 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE];
6426 } __packed;
6427
6428 /* iwl_scan_probe_req - PROBE_REQUEST_FRAME_API_S_VER_v2
6429 * @mac_header: first (and common) part of the probe
6430 * @band_data: band specific data
6431 * @common_data: last (and common) part of the probe
6432 * @buf: raw data block
6433 */
6434 struct iwx_scan_probe_req {
6435 struct iwx_scan_probe_segment mac_header;
6436 struct iwx_scan_probe_segment band_data[3];
6437 struct iwx_scan_probe_segment common_data;
6438 uint8_t buf[IWX_SCAN_OFFLOAD_PROBE_REQ_SIZE];
6439 } __packed;
6440
6441
6442 #define IWX_SCAN_CHANNEL_FLAG_EBS (1 << 0)
6443 #define IWX_SCAN_CHANNEL_FLAG_EBS_ACCURATE (1 << 1)
6444 #define IWX_SCAN_CHANNEL_FLAG_CACHE_ADD (1 << 2)
6445 #define IWX_SCAN_CHANNEL_FLAG_EBS_FRAG (1 << 3)
6446 #define IWX_SCAN_CHANNEL_FLAG_FORCE_EBS (1 << 4)
6447 #define IWX_SCAN_CHANNEL_FLAG_ENABLE_CHAN_ORDER (1 << 5)
6448 #define IWX_SCAN_CHANNEL_FLAG_6G_PSC_NO_FILTER (1 << 6)
6449
6450 /* iwx_scan_channel_opt - CHANNEL_OPTIMIZATION_API_S
6451 * @flags: enum iwx_scan_channel_flags
6452 * @non_ebs_ratio: defines the ratio of number of scan iterations where EBS is
6453 * involved.
6454 * 1 - EBS is disabled.
6455 * 2 - every second scan will be full scan(and so on).
6456 */
6457 struct iwx_scan_channel_opt {
6458 uint16_t flags;
6459 uint16_t non_ebs_ratio;
6460 } __packed;
6461
6462 #define IWX_SCAN_PRIORITY_LOW 0
6463 #define IWX_SCAN_PRIORITY_MEDIUM 1
6464 #define IWX_SCAN_PRIORITY_HIGH 2
6465
6466 enum iwx_scan_priority_ext {
6467 IWX_SCAN_PRIORITY_EXT_0_LOWEST,
6468 IWX_SCAN_PRIORITY_EXT_1,
6469 IWX_SCAN_PRIORITY_EXT_2,
6470 IWX_SCAN_PRIORITY_EXT_3,
6471 IWX_SCAN_PRIORITY_EXT_4,
6472 IWX_SCAN_PRIORITY_EXT_5,
6473 IWX_SCAN_PRIORITY_EXT_6,
6474 IWX_SCAN_PRIORITY_EXT_7_HIGHEST,
6475 };
6476
6477 /**
6478 * iwx_scan_offload_complete - PERIODIC_SCAN_COMPLETE_NTF_API_S_VER_2
6479 * @last_schedule_line: last schedule line executed (fast or regular)
6480 * @last_schedule_iteration: last scan iteration executed before scan abort
6481 * @status: enum iwx_scan_offload_complete_status
6482 * @ebs_status: EBS success status &enum iwx_scan_ebs_status
6483 * @time_after_last_iter; time in seconds elapsed after last iteration
6484 */
6485 struct iwx_periodic_scan_complete {
6486 uint8_t last_schedule_line;
6487 uint8_t last_schedule_iteration;
6488 uint8_t status;
6489 uint8_t ebs_status;
6490 uint32_t time_after_last_iter;
6491 uint32_t reserved;
6492 } __packed;
6493
6494 /**
6495 * struct iwx_scan_results_notif - scan results for one channel -
6496 * SCAN_RESULT_NTF_API_S_VER_3
6497 * @channel: which channel the results are from
6498 * @band: 0 for 5.2 GHz, 1 for 2.4 GHz
6499 * @probe_status: IWX_SCAN_PROBE_STATUS_*, indicates success of probe request
6500 * @num_probe_not_sent: # of request that weren't sent due to not enough time
6501 * @duration: duration spent in channel, in usecs
6502 */
6503 struct iwx_scan_results_notif {
6504 uint8_t channel;
6505 uint8_t band;
6506 uint8_t probe_status;
6507 uint8_t num_probe_not_sent;
6508 uint32_t duration;
6509 } __packed;
6510
6511 #define IWX_SCAN_CLIENT_SCHED_SCAN (1 << 0)
6512 #define IWX_SCAN_CLIENT_NETDETECT (1 << 1)
6513 #define IWX_SCAN_CLIENT_ASSET_TRACKING (1 << 2)
6514
6515 /**
6516 * iwx_scan_offload_blacklist - IWX_SCAN_OFFLOAD_BLACKLIST_S
6517 * @ssid: MAC address to filter out
6518 * @reported_rssi: AP rssi reported to the host
6519 * @client_bitmap: clients ignore this entry - enum scan_framework_client
6520 */
6521 struct iwx_scan_offload_blacklist {
6522 uint8_t ssid[ETHER_ADDR_LEN];
6523 uint8_t reported_rssi;
6524 uint8_t client_bitmap;
6525 } __packed;
6526
6527 #define IWX_NETWORK_TYPE_BSS 1
6528 #define IWX_NETWORK_TYPE_IBSS 2
6529 #define IWX_NETWORK_TYPE_ANY 3
6530
6531 #define IWX_SCAN_OFFLOAD_SELECT_2_4 0x4
6532 #define IWX_SCAN_OFFLOAD_SELECT_5_2 0x8
6533 #define IWX_SCAN_OFFLOAD_SELECT_ANY 0xc
6534
6535 /**
6536 * iwx_scan_offload_profile - IWX_SCAN_OFFLOAD_PROFILE_S
6537 * @ssid_index: index to ssid list in fixed part
6538 * @unicast_cipher: encryption algorithm to match - bitmap
6539 * @aut_alg: authentication algorithm to match - bitmap
6540 * @network_type: enum iwx_scan_offload_network_type
6541 * @band_selection: enum iwx_scan_offload_band_selection
6542 * @client_bitmap: clients waiting for match - enum scan_framework_client
6543 */
6544 struct iwx_scan_offload_profile {
6545 uint8_t ssid_index;
6546 uint8_t unicast_cipher;
6547 uint8_t auth_alg;
6548 uint8_t network_type;
6549 uint8_t band_selection;
6550 uint8_t client_bitmap;
6551 uint8_t reserved[2];
6552 } __packed;
6553
6554 /**
6555 * iwx_scan_offload_profile_cfg - IWX_SCAN_OFFLOAD_PROFILES_CFG_API_S_VER_1
6556 * @blacklist: AP list to filter off from scan results
6557 * @profiles: profiles to search for match
6558 * @blacklist_len: length of blacklist
6559 * @num_profiles: num of profiles in the list
6560 * @match_notify: clients waiting for match found notification
6561 * @pass_match: clients waiting for the results
6562 * @active_clients: active clients bitmap - enum scan_framework_client
6563 * @any_beacon_notify: clients waiting for match notification without match
6564 */
6565 struct iwx_scan_offload_profile_cfg {
6566 struct iwx_scan_offload_profile profiles[IWX_SCAN_MAX_PROFILES];
6567 uint8_t blacklist_len;
6568 uint8_t num_profiles;
6569 uint8_t match_notify;
6570 uint8_t pass_match;
6571 uint8_t active_clients;
6572 uint8_t any_beacon_notify;
6573 uint8_t reserved[2];
6574 } __packed;
6575
6576 #define IWX_SCAN_OFFLOAD_COMPLETED 1
6577 #define IWX_SCAN_OFFLOAD_ABORTED 2
6578
6579 /* UMAC Scan API */
6580
6581 #define IWX_SCAN_CONFIG_FLAG_ACTIVATE (1 << 0)
6582 #define IWX_SCAN_CONFIG_FLAG_DEACTIVATE (1 << 1)
6583 #define IWX_SCAN_CONFIG_FLAG_FORBID_CHUB_REQS (1 << 2)
6584 #define IWX_SCAN_CONFIG_FLAG_ALLOW_CHUB_REQS (1 << 3)
6585 #define IWX_SCAN_CONFIG_FLAG_SET_TX_CHAINS (1 << 8)
6586 #define IWX_SCAN_CONFIG_FLAG_SET_RX_CHAINS (1 << 9)
6587 #define IWX_SCAN_CONFIG_FLAG_SET_AUX_STA_ID (1 << 10)
6588 #define IWX_SCAN_CONFIG_FLAG_SET_ALL_TIMES (1 << 11)
6589 #define IWX_SCAN_CONFIG_FLAG_SET_EFFECTIVE_TIMES (1 << 12)
6590 #define IWX_SCAN_CONFIG_FLAG_SET_CHANNEL_FLAGS (1 << 13)
6591 #define IWX_SCAN_CONFIG_FLAG_SET_LEGACY_RATES (1 << 14)
6592 #define IWX_SCAN_CONFIG_FLAG_SET_MAC_ADDR (1 << 15)
6593 #define IWX_SCAN_CONFIG_FLAG_SET_FRAGMENTED (1 << 16)
6594 #define IWX_SCAN_CONFIG_FLAG_CLEAR_FRAGMENTED (1 << 17)
6595 #define IWX_SCAN_CONFIG_FLAG_SET_CAM_MODE (1 << 18)
6596 #define IWX_SCAN_CONFIG_FLAG_CLEAR_CAM_MODE (1 << 19)
6597 #define IWX_SCAN_CONFIG_FLAG_SET_PROMISC_MODE (1 << 20)
6598 #define IWX_SCAN_CONFIG_FLAG_CLEAR_PROMISC_MODE (1 << 21)
6599
6600 /* Bits 26-31 are for num of channels in channel_array */
6601 #define IWX_SCAN_CONFIG_N_CHANNELS(n) ((n) << 26)
6602
6603 /* OFDM basic rates */
6604 #define IWX_SCAN_CONFIG_RATE_6M (1 << 0)
6605 #define IWX_SCAN_CONFIG_RATE_9M (1 << 1)
6606 #define IWX_SCAN_CONFIG_RATE_12M (1 << 2)
6607 #define IWX_SCAN_CONFIG_RATE_18M (1 << 3)
6608 #define IWX_SCAN_CONFIG_RATE_24M (1 << 4)
6609 #define IWX_SCAN_CONFIG_RATE_36M (1 << 5)
6610 #define IWX_SCAN_CONFIG_RATE_48M (1 << 6)
6611 #define IWX_SCAN_CONFIG_RATE_54M (1 << 7)
6612 /* CCK basic rates */
6613 #define IWX_SCAN_CONFIG_RATE_1M (1 << 8)
6614 #define IWX_SCAN_CONFIG_RATE_2M (1 << 9)
6615 #define IWX_SCAN_CONFIG_RATE_5M (1 << 10)
6616 #define IWX_SCAN_CONFIG_RATE_11M (1 << 11)
6617
6618 /* Bits 16-27 are for supported rates */
6619 #define IWX_SCAN_CONFIG_SUPPORTED_RATE(rate) ((rate) << 16)
6620
6621 #define IWX_CHANNEL_FLAG_EBS (1 << 0)
6622 #define IWX_CHANNEL_FLAG_ACCURATE_EBS (1 << 1)
6623 #define IWX_CHANNEL_FLAG_EBS_ADD (1 << 2)
6624 #define IWX_CHANNEL_FLAG_PRE_SCAN_PASSIVE2ACTIVE (1 << 3)
6625
6626 /**
6627 * struct iwx_scan_dwell
6628 * @active: default dwell time for active scan
6629 * @passive: default dwell time for passive scan
6630 * @fragmented: default dwell time for fragmented scan
6631 * @extended: default dwell time for channels 1, 6 and 11
6632 */
6633 struct iwx_scan_dwell {
6634 uint8_t active;
6635 uint8_t passive;
6636 uint8_t fragmented;
6637 uint8_t extended;
6638 } __packed;
6639
6640
6641 #define IWX_SCAN_TWO_LMACS 2
6642 #define IWX_SCAN_LB_LMAC_IDX 0 /* low-band */
6643 #define IWX_SCAN_HB_LMAC_IDX 1 /* high-band */
6644
6645 /**
6646 * struct iwl_scan_config
6647 * @enable_cam_mode: whether to enable CAM mode.
6648 * @enable_promiscuous_mode: whether to enable promiscuous mode
6649 * @bcast_sta_id: the index of the station in the fw. Deprecated starting with
6650 * API version 5.
6651 * @reserved: reserved
6652 * @tx_chains: valid_tx antenna - ANT_* definitions
6653 * @rx_chains: valid_rx antenna - ANT_* definitions
6654 */
6655 struct iwx_scan_config {
6656 uint8_t enable_cam_mode;
6657 uint8_t enable_promiscuous_mode;
6658 uint8_t bcast_sta_id;
6659 uint8_t reserved;
6660 uint32_t tx_chains;
6661 uint32_t rx_chains;
6662 } __packed; /* SCAN_CONFIG_DB_CMD_API_S_5 */
6663
6664 /**
6665 * struct iwx_scan_config_v2
6666 * @flags: enum scan_config_flags
6667 * @tx_chains: valid_tx antenna - ANT_* definitions
6668 * @rx_chains: valid_rx antenna - ANT_* definitions
6669 * @legacy_rates: default legacy rates - enum scan_config_rates
6670 * @out_of_channel_time: default max out of serving channel time
6671 * @suspend_time: default max suspend time
6672 * @dwell_active: default dwell time for active scan
6673 * @dwell_passive: default dwell time for passive scan
6674 * @dwell_fragmented: default dwell time for fragmented scan
6675 * @dwell_extended: default dwell time for channels 1, 6 and 11
6676 * @mac_addr: default mac address to be used in probes
6677 * @bcast_sta_id: the index of the station in the fw
6678 * @channel_flags: default channel flags - enum iwx_channel_flags
6679 * scan_config_channel_flag
6680 * @channel_array: default supported channels
6681 */
6682 struct iwx_scan_config_v2 {
6683 uint32_t flags;
6684 uint32_t tx_chains;
6685 uint32_t rx_chains;
6686 uint32_t legacy_rates;
6687 uint32_t out_of_channel_time[IWX_SCAN_TWO_LMACS];
6688 uint32_t suspend_time[IWX_SCAN_TWO_LMACS];
6689 struct iwx_scan_dwell dwell;
6690 uint8_t mac_addr[ETHER_ADDR_LEN];
6691 uint8_t bcast_sta_id;
6692 uint8_t channel_flags;
6693 uint8_t channel_array[];
6694 } __packed; /* SCAN_CONFIG_DB_CMD_API_S_2 */
6695
6696 /**
6697 * iwx_umac_scan_flags
6698 *@IWX_UMAC_SCAN_FLAG_PREEMPTIVE: scan process triggered by this scan request
6699 * can be preempted by other scan requests with higher priority.
6700 * The low priority scan will be resumed when the higher priority scan is
6701 * completed.
6702 *@IWX_UMAC_SCAN_FLAG_START_NOTIF: notification will be sent to the driver
6703 * when scan starts.
6704 */
6705 #define IWX_UMAC_SCAN_FLAG_PREEMPTIVE (1 << 0)
6706 #define IWX_UMAC_SCAN_FLAG_START_NOTIF (1 << 1)
6707
6708 #define IWX_UMAC_SCAN_UID_TYPE_OFFSET 0
6709 #define IWX_UMAC_SCAN_UID_SEQ_OFFSET 8
6710
6711 #define IWX_UMAC_SCAN_GEN_FLAGS_PERIODIC (1 << 0)
6712 #define IWX_UMAC_SCAN_GEN_FLAGS_OVER_BT (1 << 1)
6713 #define IWX_UMAC_SCAN_GEN_FLAGS_PASS_ALL (1 << 2)
6714 #define IWX_UMAC_SCAN_GEN_FLAGS_PASSIVE (1 << 3)
6715 #define IWX_UMAC_SCAN_GEN_FLAGS_PRE_CONNECT (1 << 4)
6716 #define IWX_UMAC_SCAN_GEN_FLAGS_ITER_COMPLETE (1 << 5)
6717 #define IWX_UMAC_SCAN_GEN_FLAGS_MULTIPLE_SSID (1 << 6)
6718 #define IWX_UMAC_SCAN_GEN_FLAGS_FRAGMENTED (1 << 7)
6719 #define IWX_UMAC_SCAN_GEN_FLAGS_RRM_ENABLED (1 << 8)
6720 #define IWX_UMAC_SCAN_GEN_FLAGS_MATCH (1 << 9)
6721 #define IWX_UMAC_SCAN_GEN_FLAGS_EXTENDED_DWELL (1 << 10)
6722 /* Extended dwell is obsolete when adaptive dwell is used, making this
6723 * bit reusable. Hence, probe request defer is used only when adaptive
6724 * dwell is supported. */
6725 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_DEFER_SUPP (1 << 10)
6726 #define IWX_UMAC_SCAN_GEN_FLAGS_LMAC2_FRAGMENTED (1 << 11)
6727 #define IWX_UMAC_SCAN_GEN_FLAGS_ADAPTIVE_DWELL (1 << 13)
6728 #define IWX_UMAC_SCAN_GEN_FLAGS_MAX_CHNL_TIME (1 << 14)
6729 #define IWX_UMAC_SCAN_GEN_FLAGS_PROB_REQ_HIGH_TX_RATE (1 << 15)
6730
6731 /**
6732 * UMAC scan general flags #2
6733 * @IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL: Whether to send a complete
6734 * notification per channel or not.
6735 * @IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER: Whether to allow channel
6736 * reorder optimization or not.
6737 */
6738 #define IWX_UMAC_SCAN_GEN_FLAGS2_NOTIF_PER_CHNL (1 << 0)
6739 #define IWX_UMAC_SCAN_GEN_FLAGS2_ALLOW_CHNL_REORDER (1 << 1)
6740
6741 /**
6742 * UMAC scan general flags version 2
6743 *
6744 * The FW flags were reordered and hence the driver introduce version 2
6745 *
6746 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC: periodic or scheduled
6747 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL: pass all probe responses and beacons
6748 * during scan iterations
6749 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE: send complete notification
6750 * on every iteration instead of only once after the last iteration
6751 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1: fragmented scan LMAC1
6752 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2: fragmented scan LMAC2
6753 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH: does this scan check for profile matching
6754 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS: use all valid chains for RX
6755 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL: works with adaptive dwell
6756 * for active channel
6757 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE: can be preempted by other requests
6758 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START: send notification of scan start
6759 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID: matching on multiple SSIDs
6760 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE: all the channels scanned
6761 * as passive
6762 * @IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN: at the end of 2.4GHz and
6763 * 5.2Ghz bands scan, trigger scan on 6GHz band to discover
6764 * the reported collocated APs
6765 */
6766 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PERIODIC (1 << 0)
6767 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PASS_ALL (1 << 1)
6768 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTFY_ITER_COMPLETE (1 << 2)
6769 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC1 (1 << 3)
6770 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FRAGMENTED_LMAC2 (1 << 4)
6771 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MATCH (1 << 5)
6772 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_USE_ALL_RX_CHAINS (1 << 6)
6773 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_ADAPTIVE_DWELL (1 << 7)
6774 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_PREEMPTIVE (1 << 8)
6775 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_NTF_START (1 << 9)
6776 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_MULTI_SSID (1 << 10)
6777 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_FORCE_PASSIVE (1 << 11)
6778 #define IWX_UMAC_SCAN_GEN_FLAGS_V2_TRIGGER_UHB_SCAN (1 << 12)
6779
6780 /**
6781 * struct iwx_scan_channel_cfg_umac
6782 * @flags: bitmap - 0-19: directed scan to i'th ssid.
6783 * @channel_num: channel number 1-13 etc.
6784 * @iter_count: repetition count for the channel.
6785 * @iter_interval: interval between two scan iterations on one channel.
6786 */
6787 struct iwx_scan_channel_cfg_umac {
6788 uint32_t flags;
6789 union {
6790 struct {
6791 uint8_t channel_num;
6792 uint8_t iter_count;
6793 uint16_t iter_interval;
6794 } v1; /* SCAN_CHANNEL_CFG_S_VER1 */
6795 struct {
6796 uint8_t channel_num;
6797 uint8_t band;
6798 uint8_t iter_count;
6799 uint8_t iter_interval;
6800 } v2; /* SCAN_CHANNEL_CFG_S_VER{2,3,4} */
6801 };
6802 } __packed;
6803
6804 /**
6805 * struct iwx_scan_umac_schedule
6806 * @interval: interval in seconds between scan iterations
6807 * @iter_count: num of scan iterations for schedule plan, 0xff for infinite loop
6808 * @reserved: for alignment and future use
6809 */
6810 struct iwx_scan_umac_schedule {
6811 uint16_t interval;
6812 uint8_t iter_count;
6813 uint8_t reserved;
6814 } __packed; /* SCAN_SCHED_PARAM_API_S_VER_1 */
6815
6816 /**
6817 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command
6818 * parameters following channels configuration array.
6819 * @schedule: two scheduling plans.
6820 * @delay: delay in TUs before starting the first scan iteration
6821 * @reserved: for future use and alignment
6822 * @preq: probe request with IEs blocks
6823 * @direct_scan: list of SSIDs for directed active scan
6824 */
6825 struct iwx_scan_req_umac_tail_v1 {
6826 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
6827 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS];
6828 uint16_t delay;
6829 uint16_t reserved;
6830 /* SCAN_PROBE_PARAMS_API_S_VER_1 */
6831 struct iwx_scan_probe_req_v1 preq;
6832 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX];
6833 } __packed;
6834
6835 /**
6836 * struct iwx_scan_req_umac_tail - the rest of the UMAC scan request command
6837 * parameters following channels configuration array.
6838 * @schedule: two scheduling plans.
6839 * @delay: delay in TUs before starting the first scan iteration
6840 * @reserved: for future use and alignment
6841 * @preq: probe request with IEs blocks
6842 * @direct_scan: list of SSIDs for directed active scan
6843 */
6844 struct iwx_scan_req_umac_tail_v2 {
6845 /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
6846 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS];
6847 uint16_t delay;
6848 uint16_t reserved;
6849 /* SCAN_PROBE_PARAMS_API_S_VER_2 */
6850 struct iwx_scan_probe_req preq;
6851 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX];
6852 } __packed;
6853
6854 /**
6855 * struct iwx_scan_umac_chan_param
6856 * @flags: channel flags &enum iwl_scan_channel_flags
6857 * @count: num of channels in scan request
6858 * @reserved: for future use and alignment
6859 */
6860 struct iwx_scan_umac_chan_param {
6861 uint8_t flags;
6862 uint8_t count;
6863 uint16_t reserved;
6864 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_1 */
6865
6866 #define IWX_SCAN_LB_LMAC_IDX 0
6867 #define IWX_SCAN_HB_LMAC_IDX 1
6868
6869 /**
6870 * struct iwx_scan_req_umac
6871 * @flags: &enum iwl_umac_scan_flags
6872 * @uid: scan id, &enum iwl_umac_scan_uid_offsets
6873 * @ooc_priority: out of channel priority - &enum iwl_scan_priority
6874 * @general_flags: &enum iwl_umac_scan_general_flags
6875 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF
6876 * @extended_dwell: dwell time for channels 1, 6 and 11
6877 * @active_dwell: dwell time for active scan per LMAC
6878 * @passive_dwell: dwell time for passive scan per LMAC
6879 * @fragmented_dwell: dwell time for fragmented passive scan
6880 * @adwell_default_n_aps: for adaptive dwell the default number of APs
6881 * per channel
6882 * @adwell_default_n_aps_social: for adaptive dwell the default
6883 * number of APs per social (1,6,11) channel
6884 * @general_flags2: &enum iwl_umac_scan_general_flags2
6885 * @adwell_max_budget: for adaptive dwell the maximal budget of TU to be added
6886 * to total scan time
6887 * @max_out_time: max out of serving channel time, per LMAC - for CDB there
6888 * are 2 LMACs (high band and low band)
6889 * @suspend_time: max suspend time, per LMAC - for CDB there are 2 LMACs
6890 * @scan_priority: scan internal prioritization &enum iwl_scan_priority
6891 * @num_of_fragments: Number of fragments needed for full coverage per band.
6892 * Relevant only for fragmented scan.
6893 * @channel: &struct iwx_scan_umac_chan_param
6894 * @reserved: for future use and alignment
6895 * @reserved3: for future use and alignment
6896 * @data: &struct iwx_scan_channel_cfg_umac and
6897 * &struct iwx_scan_req_umac_tail
6898 */
6899 struct iwx_scan_req_umac {
6900 uint32_t flags;
6901 uint32_t uid;
6902 uint32_t ooc_priority;
6903 /* SCAN_GENERAL_PARAMS_API_S_VER_1 */
6904 uint16_t general_flags;
6905 uint8_t reserved;
6906 uint8_t scan_start_mac_id;
6907 union {
6908 struct {
6909 uint8_t extended_dwell;
6910 uint8_t active_dwell;
6911 uint8_t passive_dwell;
6912 uint8_t fragmented_dwell;
6913 uint32_t max_out_time;
6914 uint32_t suspend_time;
6915 uint32_t scan_priority;
6916 struct iwx_scan_umac_chan_param channel;
6917 uint8_t data[];
6918 } v1; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_1 */
6919 struct {
6920 uint8_t extended_dwell;
6921 uint8_t active_dwell;
6922 uint8_t passive_dwell;
6923 uint8_t fragmented_dwell;
6924 uint32_t max_out_time[2];
6925 uint32_t suspend_time[2];
6926 uint32_t scan_priority;
6927 struct iwx_scan_umac_chan_param channel;
6928 uint8_t data[];
6929 } v6; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_6 */
6930 struct {
6931 uint8_t active_dwell;
6932 uint8_t passive_dwell;
6933 uint8_t fragmented_dwell;
6934 uint8_t adwell_default_n_aps;
6935 uint8_t adwell_default_n_aps_social;
6936 uint8_t reserved3;
6937 uint16_t adwell_max_budget;
6938 uint32_t max_out_time[2];
6939 uint32_t suspend_time[2];
6940 uint32_t scan_priority;
6941 struct iwx_scan_umac_chan_param channel;
6942 uint8_t data[];
6943 } v7; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_7 */
6944 struct {
6945 uint8_t active_dwell[2];
6946 uint8_t reserved2;
6947 uint8_t adwell_default_n_aps;
6948 uint8_t adwell_default_n_aps_social;
6949 uint8_t general_flags2;
6950 uint16_t adwell_max_budget;
6951 uint32_t max_out_time[2];
6952 uint32_t suspend_time[2];
6953 uint32_t scan_priority;
6954 uint8_t passive_dwell[2];
6955 uint8_t num_of_fragments[2];
6956 struct iwx_scan_umac_chan_param channel;
6957 uint8_t data[];
6958 } v8; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_8 */
6959 struct {
6960 uint8_t active_dwell[2];
6961 uint8_t adwell_default_hb_n_aps;
6962 uint8_t adwell_default_lb_n_aps;
6963 uint8_t adwell_default_n_aps_social;
6964 uint8_t general_flags2;
6965 uint16_t adwell_max_budget;
6966 uint32_t max_out_time[2];
6967 uint32_t suspend_time[2];
6968 uint32_t scan_priority;
6969 uint8_t passive_dwell[2];
6970 uint8_t num_of_fragments[2];
6971 struct iwx_scan_umac_chan_param channel;
6972 uint8_t data[];
6973 } v9; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_9 */
6974 };
6975 } __packed;
6976
6977 #define IWX_SCAN_REQ_UMAC_SIZE_V8 sizeof(struct iwx_scan_req_umac)
6978 #define IWX_SCAN_REQ_UMAC_SIZE_V7 48
6979 #define IWX_SCAN_REQ_UMAC_SIZE_V6 44
6980 #define IWX_SCAN_REQ_UMAC_SIZE_V1 36
6981
6982 /**
6983 * struct iwx_scan_general_params_v10
6984 * @flags: &enum iwx_umac_scan_flags
6985 * @reserved: reserved for future
6986 * @scan_start_mac_id: report the scan start TSF time according to this mac TSF
6987 * @active_dwell: dwell time for active scan per LMAC
6988 * @adwell_default_2g: adaptive dwell default number of APs
6989 * for 2.4GHz channel
6990 * @adwell_default_5g: adaptive dwell default number of APs
6991 * for 5GHz channels
6992 * @adwell_default_social_chn: adaptive dwell default number of
6993 * APs per social channel
6994 * @reserved1: reserved for future
6995 * @adwell_max_budget: the maximal number of TUs that adaptive dwell
6996 * can add to the total scan time
6997 * @max_out_of_time: max out of serving channel time, per LMAC
6998 * @suspend_time: max suspend time, per LMAC
6999 * @scan_priority: priority of the request
7000 * @passive_dwell: continues dwell time for passive channel
7001 * (without adaptive dwell)
7002 * @num_of_fragments: number of fragments needed for full fragmented
7003 * scan coverage.
7004 */
7005 struct iwx_scan_general_params_v10 {
7006 uint16_t flags;
7007 uint8_t reserved;
7008 uint8_t scan_start_mac_id;
7009 uint8_t active_dwell[IWX_SCAN_TWO_LMACS];
7010 uint8_t adwell_default_2g;
7011 uint8_t adwell_default_5g;
7012 uint8_t adwell_default_social_chn;
7013 uint8_t reserved1;
7014 uint16_t adwell_max_budget;
7015 uint32_t max_out_of_time[IWX_SCAN_TWO_LMACS];
7016 uint32_t suspend_time[IWX_SCAN_TWO_LMACS];
7017 uint32_t scan_priority;
7018 uint8_t passive_dwell[IWX_SCAN_TWO_LMACS];
7019 uint8_t num_of_fragments[IWX_SCAN_TWO_LMACS];
7020 } __packed; /* SCAN_GENERAL_PARAMS_API_S_VER_10 */
7021
7022 /**
7023 * struct iwx_scan_channel_params_v6
7024 * @flags: channel flags &enum iwl_scan_channel_flags
7025 * @count: num of channels in scan request
7026 * @n_aps_override: override the number of APs the FW uses to calculate dwell
7027 * time when adaptive dwell is used.
7028 * Channel k will use n_aps_override[i] when BIT(20 + i) is set in
7029 * channel_config[k].flags
7030 * @channel_config: array of explicit channel configurations
7031 * for 2.4Ghz and 5.2Ghz bands
7032 */
7033 struct iwx_scan_channel_params_v6 {
7034 uint8_t flags;
7035 uint8_t count;
7036 uint8_t n_aps_override[2];
7037 struct iwx_scan_channel_cfg_umac channel_config[67];
7038 } __packed; /* SCAN_CHANNEL_PARAMS_API_S_VER_6 */
7039
7040 /**
7041 * struct iwx_scan_periodic_parms_v1
7042 * @schedule: can scheduling parameter
7043 * @delay: initial delay of the periodic scan in seconds
7044 * @reserved: reserved for future
7045 */
7046 struct iwx_scan_periodic_parms_v1 {
7047 struct iwx_scan_umac_schedule schedule[IWX_MAX_SCHED_SCAN_PLANS];
7048 uint16_t delay;
7049 uint16_t reserved;
7050 } __packed; /* SCAN_PERIODIC_PARAMS_API_S_VER_1 */
7051
7052 #define IWX_SCAN_SHORT_SSID_MAX_SIZE 8
7053 #define IWX_SCAN_BSSID_MAX_SIZE 16
7054
7055 /**
7056 * struct iwx_scan_probe_params_v4
7057 * @preq: scan probe request params
7058 * @short_ssid_num: number of valid short SSIDs in short ssid array
7059 * @bssid_num: number of valid bssid in bssids array
7060 * @reserved: reserved
7061 * @direct_scan: list of ssids
7062 * @short_ssid: array of short ssids
7063 * @bssid_array: array of bssids
7064 */
7065 struct iwx_scan_probe_params_v4 {
7066 struct iwx_scan_probe_req preq;
7067 uint8_t short_ssid_num;
7068 uint8_t bssid_num;
7069 uint16_t reserved;
7070 struct iwx_ssid_ie direct_scan[IWX_PROBE_OPTION_MAX];
7071 uint32_t short_ssid[IWX_SCAN_SHORT_SSID_MAX_SIZE];
7072 uint8_t bssid_array[IWX_SCAN_BSSID_MAX_SIZE][ETHER_ADDR_LEN];
7073 } __packed; /* SCAN_PROBE_PARAMS_API_S_VER_4 */
7074
7075 /**
7076 * struct iwx_scan_req_params_v14
7077 * @general_params: &struct iwx_scan_general_params_v10
7078 * @channel_params: &struct iwx_scan_channel_params_v6
7079 * @periodic_params: &struct iwx_scan_periodic_parms_v1
7080 * @probe_params: &struct iwx_scan_probe_params_v4
7081 */
7082 struct iwx_scan_req_params_v14 {
7083 struct iwx_scan_general_params_v10 general_params;
7084 struct iwx_scan_channel_params_v6 channel_params;
7085 struct iwx_scan_periodic_parms_v1 periodic_params;
7086 struct iwx_scan_probe_params_v4 probe_params;
7087 } __packed; /* SCAN_REQUEST_PARAMS_API_S_VER_14 */
7088
7089 /**
7090 * struct iwx_scan_req_umac_v14
7091 * @uid: scan id, &enum iwl_umac_scan_uid_offsets
7092 * @ooc_priority: out of channel priority - &enum iwx_scan_priority
7093 * @scan_params: scan parameters
7094 */
7095 struct iwx_scan_req_umac_v14 {
7096 uint32_t uid;
7097 uint32_t ooc_priority;
7098 struct iwx_scan_req_params_v14 scan_params;
7099 } __packed; /* SCAN_REQUEST_CMD_UMAC_API_S_VER_14 */
7100
7101 /**
7102 * struct iwx_umac_scan_abort
7103 * @uid: scan id, &enum iwx_umac_scan_uid_offsets
7104 * @flags: reserved
7105 */
7106 struct iwx_umac_scan_abort {
7107 uint32_t uid;
7108 uint32_t flags;
7109 } __packed; /* SCAN_ABORT_CMD_UMAC_API_S_VER_1 */
7110
7111 /**
7112 * struct iwx_umac_scan_complete
7113 * @uid: scan id, &enum iwx_umac_scan_uid_offsets
7114 * @last_schedule: last scheduling line
7115 * @last_iter: last scan iteration number
7116 * @scan status: &enum iwx_scan_offload_complete_status
7117 * @ebs_status: &enum iwx_scan_ebs_status
7118 * @time_from_last_iter: time elapsed from last iteration
7119 * @reserved: for future use
7120 */
7121 struct iwx_umac_scan_complete {
7122 uint32_t uid;
7123 uint8_t last_schedule;
7124 uint8_t last_iter;
7125 uint8_t status;
7126 uint8_t ebs_status;
7127 uint32_t time_from_last_iter;
7128 uint32_t reserved;
7129 } __packed; /* SCAN_COMPLETE_NTF_UMAC_API_S_VER_1 */
7130
7131 #define IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN 5
7132 /**
7133 * struct iwx_scan_offload_profile_match - match information
7134 * @bssid: matched bssid
7135 * @channel: channel where the match occurred
7136 * @energy:
7137 * @matching_feature:
7138 * @matching_channels: bitmap of channels that matched, referencing
7139 * the channels passed in tue scan offload request
7140 */
7141 struct iwx_scan_offload_profile_match {
7142 uint8_t bssid[ETHER_ADDR_LEN];
7143 uint16_t reserved;
7144 uint8_t channel;
7145 uint8_t energy;
7146 uint8_t matching_feature;
7147 uint8_t matching_channels[IWX_SCAN_OFFLOAD_MATCHING_CHANNELS_LEN];
7148 } __packed; /* SCAN_OFFLOAD_PROFILE_MATCH_RESULTS_S_VER_1 */
7149
7150 /**
7151 * struct iwx_scan_offload_profiles_query - match results query response
7152 * @matched_profiles: bitmap of matched profiles, referencing the
7153 * matches passed in the scan offload request
7154 * @last_scan_age: age of the last offloaded scan
7155 * @n_scans_done: number of offloaded scans done
7156 * @gp2_d0u: GP2 when D0U occurred
7157 * @gp2_invoked: GP2 when scan offload was invoked
7158 * @resume_while_scanning: not used
7159 * @self_recovery: obsolete
7160 * @reserved: reserved
7161 * @matches: array of match information, one for each match
7162 */
7163 struct iwx_scan_offload_profiles_query {
7164 uint32_t matched_profiles;
7165 uint32_t last_scan_age;
7166 uint32_t n_scans_done;
7167 uint32_t gp2_d0u;
7168 uint32_t gp2_invoked;
7169 uint8_t resume_while_scanning;
7170 uint8_t self_recovery;
7171 uint16_t reserved;
7172 struct iwx_scan_offload_profile_match matches[IWX_SCAN_MAX_PROFILES];
7173 } __packed; /* SCAN_OFFLOAD_PROFILES_QUERY_RSP_S_VER_2 */
7174
7175 /**
7176 * struct iwx_umac_scan_iter_complete_notif - notifies end of scanning iteration
7177 * @uid: scan id, &enum iwx_umac_scan_uid_offsets
7178 * @scanned_channels: number of channels scanned and number of valid elements in
7179 * results array
7180 * @status: one of SCAN_COMP_STATUS_*
7181 * @bt_status: BT on/off status
7182 * @last_channel: last channel that was scanned
7183 * @tsf_low: TSF timer (lower half) in usecs
7184 * @tsf_high: TSF timer (higher half) in usecs
7185 * @results: array of scan results, only "scanned_channels" of them are valid
7186 */
7187 struct iwx_umac_scan_iter_complete_notif {
7188 uint32_t uid;
7189 uint8_t scanned_channels;
7190 uint8_t status;
7191 uint8_t bt_status;
7192 uint8_t last_channel;
7193 uint32_t tsf_low;
7194 uint32_t tsf_high;
7195 struct iwx_scan_results_notif results[];
7196 } __packed; /* SCAN_ITER_COMPLETE_NTF_UMAC_API_S_VER_1 */
7197
7198 #define IWX_GSCAN_START_CMD 0x0
7199 #define IWX_GSCAN_STOP_CMD 0x1
7200 #define IWX_GSCAN_SET_HOTLIST_CMD 0x2
7201 #define IWX_GSCAN_RESET_HOTLIST_CMD 0x3
7202 #define IWX_GSCAN_SET_SIGNIFICANT_CHANGE_CMD 0x4
7203 #define IWX_GSCAN_RESET_SIGNIFICANT_CHANGE_CMD 0x5
7204 #define IWX_GSCAN_SIGNIFICANT_CHANGE_EVENT 0xFD
7205 #define IWX_GSCAN_HOTLIST_CHANGE_EVENT 0xFE
7206 #define IWX_GSCAN_RESULTS_AVAILABLE_EVENT 0xFF
7207
7208 /* STA API */
7209
7210 /**
7211 * flags for the ADD_STA host command
7212 * @IWX_STA_FLG_REDUCED_TX_PWR_CTRL:
7213 * @IWX_STA_FLG_REDUCED_TX_PWR_DATA:
7214 * @IWX_STA_FLG_DISABLE_TX: set if TX should be disabled
7215 * @IWX_STA_FLG_PS: set if STA is in Power Save
7216 * @IWX_STA_FLG_INVALID: set if STA is invalid
7217 * @IWX_STA_FLG_DLP_EN: Direct Link Protocol is enabled
7218 * @IWX_STA_FLG_SET_ALL_KEYS: the current key applies to all key IDs
7219 * @IWX_STA_FLG_DRAIN_FLOW: drain flow
7220 * @IWX_STA_FLG_PAN: STA is for PAN interface
7221 * @IWX_STA_FLG_CLASS_AUTH:
7222 * @IWX_STA_FLG_CLASS_ASSOC:
7223 * @IWX_STA_FLG_CLASS_MIMO_PROT:
7224 * @IWX_STA_FLG_MAX_AGG_SIZE_MSK: maximal size for A-MPDU
7225 * @IWX_STA_FLG_AGG_MPDU_DENS_MSK: maximal MPDU density for Tx aggregation
7226 * @IWX_STA_FLG_FAT_EN_MSK: support for channel width (for Tx). This flag is
7227 * initialised by driver and can be updated by fw upon reception of
7228 * action frames that can change the channel width. When cleared the fw
7229 * will send all the frames in 20MHz even when FAT channel is requested.
7230 * @IWX_STA_FLG_MIMO_EN_MSK: support for MIMO. This flag is initialised by the
7231 * driver and can be updated by fw upon reception of action frames.
7232 * @IWX_STA_FLG_MFP_EN: Management Frame Protection
7233 */
7234 #define IWX_STA_FLG_REDUCED_TX_PWR_CTRL (1 << 3)
7235 #define IWX_STA_FLG_REDUCED_TX_PWR_DATA (1 << 6)
7236
7237 #define IWX_STA_FLG_DISABLE_TX (1 << 4)
7238
7239 #define IWX_STA_FLG_PS (1 << 8)
7240 #define IWX_STA_FLG_DRAIN_FLOW (1 << 12)
7241 #define IWX_STA_FLG_PAN (1 << 13)
7242 #define IWX_STA_FLG_CLASS_AUTH (1 << 14)
7243 #define IWX_STA_FLG_CLASS_ASSOC (1 << 15)
7244 #define IWX_STA_FLG_RTS_MIMO_PROT (1 << 17)
7245
7246 #define IWX_STA_FLG_MAX_AGG_SIZE_SHIFT 19
7247 #define IWX_STA_FLG_MAX_AGG_SIZE_8K (0 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7248 #define IWX_STA_FLG_MAX_AGG_SIZE_16K (1 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7249 #define IWX_STA_FLG_MAX_AGG_SIZE_32K (2 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7250 #define IWX_STA_FLG_MAX_AGG_SIZE_64K (3 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7251 #define IWX_STA_FLG_MAX_AGG_SIZE_128K (4 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7252 #define IWX_STA_FLG_MAX_AGG_SIZE_256K (5 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7253 #define IWX_STA_FLG_MAX_AGG_SIZE_512K (6 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7254 #define IWX_STA_FLG_MAX_AGG_SIZE_1024K (7 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7255 #define IWX_STA_FLG_MAX_AGG_SIZE_2M (8 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7256 #define IWX_STA_FLG_MAX_AGG_SIZE_4M (9 << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7257 #define IWX_STA_FLG_MAX_AGG_SIZE_MSK (0xf << IWX_STA_FLG_MAX_AGG_SIZE_SHIFT)
7258
7259 #define IWX_STA_FLG_AGG_MPDU_DENS_SHIFT 23
7260 #define IWX_STA_FLG_AGG_MPDU_DENS_2US (4 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7261 #define IWX_STA_FLG_AGG_MPDU_DENS_4US (5 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7262 #define IWX_STA_FLG_AGG_MPDU_DENS_8US (6 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7263 #define IWX_STA_FLG_AGG_MPDU_DENS_16US (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7264 #define IWX_STA_FLG_AGG_MPDU_DENS_MSK (7 << IWX_STA_FLG_AGG_MPDU_DENS_SHIFT)
7265
7266 #define IWX_STA_FLG_FAT_EN_20MHZ (0 << 26)
7267 #define IWX_STA_FLG_FAT_EN_40MHZ (1 << 26)
7268 #define IWX_STA_FLG_FAT_EN_80MHZ (2 << 26)
7269 #define IWX_STA_FLG_FAT_EN_160MHZ (3 << 26)
7270 #define IWX_STA_FLG_FAT_EN_MSK (3 << 26)
7271
7272 #define IWX_STA_FLG_MIMO_EN_SISO (0 << 28)
7273 #define IWX_STA_FLG_MIMO_EN_MIMO2 (1 << 28)
7274 #define IWX_STA_FLG_MIMO_EN_MIMO3 (2 << 28)
7275 #define IWX_STA_FLG_MIMO_EN_MSK (3 << 28)
7276
7277 /**
7278 * key flags for the ADD_STA host command
7279 * @IWX_STA_KEY_FLG_NO_ENC: no encryption
7280 * @IWX_STA_KEY_FLG_WEP: WEP encryption algorithm
7281 * @IWX_STA_KEY_FLG_CCM: CCMP encryption algorithm
7282 * @IWX_STA_KEY_FLG_TKIP: TKIP encryption algorithm
7283 * @IWX_STA_KEY_FLG_EXT: extended cipher algorithm (depends on the FW support)
7284 * @IWX_STA_KEY_FLG_CMAC: CMAC encryption algorithm
7285 * @IWX_STA_KEY_FLG_ENC_UNKNOWN: unknown encryption algorithm
7286 * @IWX_STA_KEY_FLG_EN_MSK: mask for encryption algorithm value
7287 * @IWX_STA_KEY_FLG_WEP_KEY_MAP: wep is either a group key (0 - legacy WEP) or from
7288 * station info array (1 - n 1X mode)
7289 * @IWX_STA_KEY_FLG_KEYID_MSK: the index of the key
7290 * @IWX_STA_KEY_NOT_VALID: key is invalid
7291 * @IWX_STA_KEY_FLG_WEP_13BYTES: set for 13 bytes WEP key
7292 * @IWX_STA_KEY_MULTICAST: set for multicast key
7293 * @IWX_STA_KEY_MFP: key is used for Management Frame Protection
7294 */
7295 #define IWX_STA_KEY_FLG_NO_ENC (0 << 0)
7296 #define IWX_STA_KEY_FLG_WEP (1 << 0)
7297 #define IWX_STA_KEY_FLG_CCM (2 << 0)
7298 #define IWX_STA_KEY_FLG_TKIP (3 << 0)
7299 #define IWX_STA_KEY_FLG_EXT (4 << 0)
7300 #define IWX_STA_KEY_FLG_CMAC (6 << 0)
7301 #define IWX_STA_KEY_FLG_ENC_UNKNOWN (7 << 0)
7302 #define IWX_STA_KEY_FLG_EN_MSK (7 << 0)
7303 #define IWX_STA_KEY_FLG_WEP_KEY_MAP (1 << 3)
7304 #define IWX_STA_KEY_FLG_KEYID_POS 8
7305 #define IWX_STA_KEY_FLG_KEYID_MSK (3 << IWX_STA_KEY_FLG_KEYID_POS)
7306 #define IWX_STA_KEY_NOT_VALID (1 << 11)
7307 #define IWX_STA_KEY_FLG_WEP_13BYTES (1 << 12)
7308 #define IWX_STA_KEY_MULTICAST (1 << 14)
7309 #define IWX_STA_KEY_MFP (1 << 15)
7310
7311 /**
7312 * indicate to the fw what flag are being changed
7313 * @IWX_STA_MODIFY_QUEUE_REMOVAL: this command removes a queue
7314 * @IWX_STA_MODIFY_TID_DISABLE_TX: this command modifies %tid_disable_tx
7315 * @IWX_STA_MODIFY_TX_RATE: unused
7316 * @IWX_STA_MODIFY_ADD_BA_TID: this command modifies %add_immediate_ba_tid
7317 * @IWX_STA_MODIFY_REMOVE_BA_TID: this command modifies %remove_immediate_ba_tid
7318 * @IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT: this command modifies %sleep_tx_count
7319 * @IWX_STA_MODIFY_PROT_TH:
7320 * @IWX_STA_MODIFY_QUEUES: modify the queues used by this station
7321 */
7322 #define IWX_STA_MODIFY_QUEUE_REMOVAL (1 << 0)
7323 #define IWX_STA_MODIFY_TID_DISABLE_TX (1 << 1)
7324 #define IWX_STA_MODIFY_TX_RATE (1 << 2)
7325 #define IWX_STA_MODIFY_ADD_BA_TID (1 << 3)
7326 #define IWX_STA_MODIFY_REMOVE_BA_TID (1 << 4)
7327 #define IWX_STA_MODIFY_SLEEPING_STA_TX_COUNT (1 << 5)
7328 #define IWX_STA_MODIFY_PROT_TH (1 << 6)
7329 #define IWX_STA_MODIFY_QUEUES (1 << 7)
7330
7331 #define IWX_STA_MODE_MODIFY 1
7332
7333 /**
7334 * type of sleep of the station
7335 * @IWX_STA_SLEEP_STATE_AWAKE:
7336 * @IWX_STA_SLEEP_STATE_PS_POLL:
7337 * @IWX_STA_SLEEP_STATE_UAPSD:
7338 * @IWX_STA_SLEEP_STATE_MOREDATA: set more-data bit on
7339 * (last) released frame
7340 */
7341 #define IWX_STA_SLEEP_STATE_AWAKE 0
7342 #define IWX_STA_SLEEP_STATE_PS_POLL (1 << 0)
7343 #define IWX_STA_SLEEP_STATE_UAPSD (1 << 1)
7344 #define IWX_STA_SLEEP_STATE_MOREDATA (1 << 2)
7345
7346 /* STA ID and color bits definitions */
7347 #define IWX_STA_ID_SEED (0x0f)
7348 #define IWX_STA_ID_POS (0)
7349 #define IWX_STA_ID_MSK (IWX_STA_ID_SEED << IWX_STA_ID_POS)
7350
7351 #define IWX_STA_COLOR_SEED (0x7)
7352 #define IWX_STA_COLOR_POS (4)
7353 #define IWX_STA_COLOR_MSK (IWX_STA_COLOR_SEED << IWX_STA_COLOR_POS)
7354
7355 #define IWX_STA_ID_N_COLOR_GET_COLOR(id_n_color) \
7356 (((id_n_color) & IWX_STA_COLOR_MSK) >> IWX_STA_COLOR_POS)
7357 #define IWX_STA_ID_N_COLOR_GET_ID(id_n_color) \
7358 (((id_n_color) & IWX_STA_ID_MSK) >> IWX_STA_ID_POS)
7359
7360 #define IWX_STA_KEY_MAX_NUM (16)
7361 #define IWX_STA_KEY_IDX_INVALID (0xff)
7362 #define IWX_STA_KEY_MAX_DATA_KEY_NUM (4)
7363 #define IWX_MAX_GLOBAL_KEYS (4)
7364 #define IWX_STA_KEY_LEN_WEP40 (5)
7365 #define IWX_STA_KEY_LEN_WEP104 (13)
7366
7367 /**
7368 * struct iwx_keyinfo - key information
7369 * @key_flags: type %iwx_sta_key_flag
7370 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
7371 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
7372 * @key_offset: key offset in the fw's key table
7373 * @key: 16-byte unicast decryption key
7374 * @tx_secur_seq_cnt: initial RSC / PN needed for replay check
7375 * @hw_tkip_mic_rx_key: byte: MIC Rx Key - used for TKIP only
7376 * @hw_tkip_mic_tx_key: byte: MIC Tx Key - used for TKIP only
7377 */
7378 struct iwx_keyinfo {
7379 uint16_t key_flags;
7380 uint8_t tkip_rx_tsc_byte2;
7381 uint8_t reserved1;
7382 uint16_t tkip_rx_ttak[5];
7383 uint8_t key_offset;
7384 uint8_t reserved2;
7385 uint8_t key[16];
7386 uint64_t tx_secur_seq_cnt;
7387 uint64_t hw_tkip_mic_rx_key;
7388 uint64_t hw_tkip_mic_tx_key;
7389 } __packed;
7390
7391 #define IWX_ADD_STA_STATUS_MASK 0xFF
7392 #define IWX_ADD_STA_BAID_VALID_MASK 0x8000
7393 #define IWX_ADD_STA_BAID_MASK 0x7F00
7394 #define IWX_ADD_STA_BAID_SHIFT 8
7395
7396 /**
7397 * struct iwx_add_sta_cmd - Add/modify a station in the fw's sta table.
7398 * ( REPLY_ADD_STA = 0x18 )
7399 * @add_modify: see &enum iwl_sta_mode
7400 * @awake_acs: ACs to transmit data on while station is sleeping (for U-APSD)
7401 * @tid_disable_tx: is tid BIT(tid) enabled for Tx. Clear BIT(x) to enable
7402 * AMPDU for tid x. Set %STA_MODIFY_TID_DISABLE_TX to change this field.
7403 * @mac_id_n_color: the Mac context this station belongs to,
7404 * see &enum iwl_ctxt_id_and_color
7405 * @addr: station's MAC address
7406 * @reserved2: reserved
7407 * @sta_id: index of station in uCode's station table
7408 * @modify_mask: STA_MODIFY_*, selects which parameters to modify vs. leave
7409 * alone. 1 - modify, 0 - don't change.
7410 * @reserved3: reserved
7411 * @station_flags: look at &enum iwl_sta_flags
7412 * @station_flags_msk: what of %station_flags have changed,
7413 * also &enum iwl_sta_flags
7414 * @add_immediate_ba_tid: tid for which to add block-ack support (Rx)
7415 * Set %STA_MODIFY_ADD_BA_TID to use this field, and also set
7416 * add_immediate_ba_ssn.
7417 * @remove_immediate_ba_tid: tid for which to remove block-ack support (Rx)
7418 * Set %STA_MODIFY_REMOVE_BA_TID to use this field
7419 * @add_immediate_ba_ssn: ssn for the Rx block-ack session. Used together with
7420 * add_immediate_ba_tid.
7421 * @sleep_tx_count: number of packets to transmit to station even though it is
7422 * asleep. Used to synchronise PS-poll and u-APSD responses while ucode
7423 * keeps track of STA sleep state.
7424 * @station_type: type of this station. See &enum iwl_sta_type.
7425 * @sleep_state_flags: Look at &enum iwl_sta_sleep_flag.
7426 * @assoc_id: assoc_id to be sent in VHT PLCP (9-bit), for grp use 0, for AP
7427 * mac-addr.
7428 * @beamform_flags: beam forming controls
7429 * @tfd_queue_msk: tfd queues used by this station.
7430 * Obsolete for new TX API (9 and above).
7431 * @rx_ba_window: aggregation window size
7432 * @sp_length: the size of the SP in actual number of frames
7433 * @uapsd_acs: 4 LS bits are trigger enabled ACs, 4 MS bits are the deliver
7434 * enabled ACs.
7435 *
7436 * The device contains an internal table of per-station information, with info
7437 * on security keys, aggregation parameters, and Tx rates for initial Tx
7438 * attempt and any retries (set by REPLY_TX_LINK_QUALITY_CMD).
7439 *
7440 * ADD_STA sets up the table entry for one station, either creating a new
7441 * entry, or modifying a pre-existing one.
7442 */
7443 struct iwx_add_sta_cmd {
7444 uint8_t add_modify;
7445 uint8_t awake_acs;
7446 uint16_t tid_disable_tx;
7447 uint32_t mac_id_n_color;
7448 uint8_t addr[ETHER_ADDR_LEN]; /* _STA_ID_MODIFY_INFO_API_S_VER_1 */
7449 uint16_t reserved2;
7450 uint8_t sta_id;
7451 uint8_t modify_mask;
7452 uint16_t reserved3;
7453 uint32_t station_flags;
7454 uint32_t station_flags_msk;
7455 uint8_t add_immediate_ba_tid;
7456 uint8_t remove_immediate_ba_tid;
7457 uint16_t add_immediate_ba_ssn;
7458 uint16_t sleep_tx_count;
7459 uint8_t sleep_state_flags;
7460 uint8_t station_type;
7461 uint16_t assoc_id;
7462 uint16_t beamform_flags;
7463 uint32_t tfd_queue_msk;
7464 uint16_t rx_ba_window;
7465 uint8_t sp_length;
7466 uint8_t uapsd_acs;
7467 } __packed; /* ADD_STA_CMD_API_S_VER_10 */
7468
7469 /**
7470 * FW station types
7471 * ( REPLY_ADD_STA = 0x18 )
7472 * @IWX_STA_LINK: Link station - normal RX and TX traffic.
7473 * @IWX_STA_GENERAL_PURPOSE: General purpose. In AP mode used for beacons
7474 * and probe responses.
7475 * @IWX_STA_MULTICAST: multicast traffic,
7476 * @IWX_STA_TDLS_LINK: TDLS link station
7477 * @IWX_STA_AUX_ACTIVITY: auxiliary station (scan, ROC and so on).
7478 */
7479 #define IWX_STA_LINK 0
7480 #define IWX_STA_GENERAL_PURPOSE 1
7481 #define IWX_STA_MULTICAST 2
7482 #define IWX_STA_TDLS_LINK 3
7483 #define IWX_STA_AUX_ACTIVITY 4
7484
7485 /**
7486 * struct iwx_add_sta_key_common - add/modify sta key common part
7487 * ( REPLY_ADD_STA_KEY = 0x17 )
7488 * @sta_id: index of station in uCode's station table
7489 * @key_offset: key offset in key storage
7490 * @key_flags: IWX_STA_KEY_FLG_*
7491 * @key: key material data
7492 * @rx_secur_seq_cnt: RX security sequence counter for the key
7493 */
7494 struct iwx_add_sta_key_common {
7495 uint8_t sta_id;
7496 uint8_t key_offset;
7497 uint16_t key_flags;
7498 uint8_t key[32];
7499 uint8_t rx_secur_seq_cnt[16];
7500 } __packed;
7501
7502 /**
7503 * struct iwx_add_sta_key_cmd_v1 - add/modify sta key
7504 * @common: see &struct iwx_add_sta_key_common
7505 * @tkip_rx_tsc_byte2: TSC[2] for key mix ph1 detection
7506 * @reserved: reserved
7507 * @tkip_rx_ttak: 10-byte unicast TKIP TTAK for Rx
7508 */
7509 struct iwx_add_sta_key_cmd_v1 {
7510 struct iwx_add_sta_key_common common;
7511 uint8_t tkip_rx_tsc_byte2;
7512 uint8_t reserved;
7513 uint16_t tkip_rx_ttak[5];
7514 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_1 */
7515
7516 /**
7517 * struct iwx_add_sta_key_cmd - add/modify sta key
7518 * @common: see &struct iwx_add_sta_key_common
7519 * @rx_mic_key: TKIP RX unicast or multicast key
7520 * @tx_mic_key: TKIP TX key
7521 * @transmit_seq_cnt: TSC, transmit packet number
7522 */
7523 struct iwx_add_sta_key_cmd {
7524 struct iwx_add_sta_key_common common;
7525 uint64_t rx_mic_key;
7526 uint64_t tx_mic_key;
7527 uint64_t transmit_seq_cnt;
7528 } __packed; /* ADD_MODIFY_STA_KEY_API_S_VER_2 */
7529
7530 /**
7531 * status in the response to ADD_STA command
7532 * @IWX_ADD_STA_SUCCESS: operation was executed successfully
7533 * @IWX_ADD_STA_STATIONS_OVERLOAD: no room left in the fw's station table
7534 * @IWX_ADD_STA_IMMEDIATE_BA_FAILURE: can't add Rx block ack session
7535 * @IWX_ADD_STA_MODIFY_NON_EXISTING_STA: driver requested to modify a station
7536 * that doesn't exist.
7537 */
7538 #define IWX_ADD_STA_SUCCESS 0x1
7539 #define IWX_ADD_STA_STATIONS_OVERLOAD 0x2
7540 #define IWX_ADD_STA_IMMEDIATE_BA_FAILURE 0x4
7541 #define IWX_ADD_STA_MODIFY_NON_EXISTING_STA 0x8
7542
7543 /**
7544 * struct iwx_rm_sta_cmd - Add / modify a station in the fw's station table
7545 * ( IWX_REMOVE_STA = 0x19 )
7546 * @sta_id: the station id of the station to be removed
7547 */
7548 struct iwx_rm_sta_cmd {
7549 uint8_t sta_id;
7550 uint8_t reserved[3];
7551 } __packed; /* IWX_REMOVE_STA_CMD_API_S_VER_2 */
7552
7553 /**
7554 * struct iwx_mgmt_mcast_key_cmd
7555 * ( IWX_MGMT_MCAST_KEY = 0x1f )
7556 * @ctrl_flags: %iwx_sta_key_flag
7557 * @IGTK:
7558 * @K1: IGTK master key
7559 * @K2: IGTK sub key
7560 * @sta_id: station ID that support IGTK
7561 * @key_id:
7562 * @receive_seq_cnt: initial RSC/PN needed for replay check
7563 */
7564 struct iwx_mgmt_mcast_key_cmd {
7565 uint32_t ctrl_flags;
7566 uint8_t IGTK[16];
7567 uint8_t K1[16];
7568 uint8_t K2[16];
7569 uint32_t key_id;
7570 uint32_t sta_id;
7571 uint64_t receive_seq_cnt;
7572 } __packed; /* SEC_MGMT_MULTICAST_KEY_CMD_API_S_VER_1 */
7573
7574 struct iwx_wep_key {
7575 uint8_t key_index;
7576 uint8_t key_offset;
7577 uint16_t reserved1;
7578 uint8_t key_size;
7579 uint8_t reserved2[3];
7580 uint8_t key[16];
7581 } __packed;
7582
7583 struct iwx_wep_key_cmd {
7584 uint32_t mac_id_n_color;
7585 uint8_t num_keys;
7586 uint8_t decryption_type;
7587 uint8_t flags;
7588 uint8_t reserved;
7589 struct iwx_wep_key wep_key[0];
7590 } __packed; /* SEC_CURR_WEP_KEY_CMD_API_S_VER_2 */
7591
7592 /*
7593 * BT coex
7594 */
7595
7596 #define IWX_BT_COEX_DISABLE 0x0
7597 #define IWX_BT_COEX_NW 0x1
7598 #define IWX_BT_COEX_BT 0x2
7599 #define IWX_BT_COEX_WIFI 0x3
7600 /* BT_COEX_MODES_E */
7601
7602 #define IWX_BT_COEX_MPLUT_ENABLED (1 << 0)
7603 #define IWX_BT_COEX_MPLUT_BOOST_ENABLED (1 << 1)
7604 #define IWX_BT_COEX_SYNC2SCO_ENABLED (1 << 2)
7605 #define IWX_BT_COEX_CORUN_ENABLED (1 << 3)
7606 #define IWX_BT_COEX_HIGH_BAND_RET (1 << 4)
7607 /* BT_COEX_MODULES_ENABLE_E_VER_1 */
7608
7609 enum iwx_bt_coex_enabled_modules {
7610 BT_COEX_DISABLE = 1 << 0,
7611 BT_COEX_MPLUT_BOOST_ENABLED = 1 << 1,
7612 BT_COEX_SYNC2SCO_ENABLED = 1 << 2,
7613 BT_COEX_CORUN_ENABLED = 1 << 3,
7614 BT_COEX_HIGH_BAND_RET = 1 << 4,
7615 };
7616
7617 /**
7618 * struct iwx_bt_coex_cmd - bt coex configuration command
7619 * @mode: enum %iwx_bt_coex_mode
7620 * @enabled_modules: enum %iwx_bt_coex_enabled_modules
7621 *
7622 * The structure is used for the BT_COEX command.
7623 */
7624 struct iwx_bt_coex_cmd {
7625 uint32_t mode;
7626 uint32_t enabled_modules;
7627 } __packed; /* BT_COEX_CMD_API_S_VER_6 */
7628
7629
7630 /*
7631 * Location Aware Regulatory (LAR) API - MCC updates
7632 */
7633
7634 /**
7635 * struct iwx_mcc_update_cmd - Request the device to update geographic
7636 * regulatory profile according to the given MCC (Mobile Country Code).
7637 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
7638 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
7639 * MCC in the cmd response will be the relevant MCC in the NVM.
7640 * @mcc: given mobile country code
7641 * @source_id: the source from where we got the MCC, see IWX_MCC_SOURCE_*
7642 * @reserved: reserved for alignment
7643 * @key: integrity key for MCC API OEM testing
7644 * @reserved2: reserved
7645 */
7646 struct iwx_mcc_update_cmd {
7647 uint16_t mcc;
7648 uint8_t source_id;
7649 uint8_t reserved;
7650 uint32_t key;
7651 uint32_t reserved2[5];
7652 } __packed; /* LAR_UPDATE_MCC_CMD_API_S_VER_2 */
7653
7654 /**
7655 * iwx_mcc_update_resp_v3 - response to MCC_UPDATE_CMD.
7656 * Contains the new channel control profile map, if changed, and the new MCC
7657 * (mobile country code).
7658 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
7659 * @status: see &enum iwx_mcc_update_status
7660 * @mcc: the new applied MCC
7661 * @cap: capabilities for all channels which matches the MCC
7662 * @source_id: the MCC source, see IWX_MCC_SOURCE_*
7663 * @time: time elapsed from the MCC test start (in 30 seconds TU)
7664 * @reserved: reserved.
7665 * @n_channels: number of channels in @channels_data (may be 14, 39, 50 or 51
7666 * channels, depending on platform)
7667 * @channels: channel control data map, DWORD for each channel. Only the first
7668 * 16bits are used.
7669 */
7670 struct iwx_mcc_update_resp_v3 {
7671 uint32_t status;
7672 uint16_t mcc;
7673 uint8_t cap;
7674 uint8_t source_id;
7675 uint16_t time;
7676 uint16_t geo_info;
7677 uint32_t n_channels;
7678 uint32_t channels[0];
7679 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_3 */
7680
7681 /**
7682 * geographic information.
7683 * @GEO_NO_INFO: no special info for this geo profile.
7684 * @GEO_WMM_ETSI_5GHZ_INFO: this geo profile limits the WMM params
7685 * for the 5 GHz band.
7686 */
7687 #define IWX_GEO_NO_INFO 0
7688 #define IWX_GEO_WMM_ETSI_5GHZ_INFO (1 << 0)
7689
7690 /**
7691 * struct iwx_mcc_update_resp - response to MCC_UPDATE_CMD.
7692 * Contains the new channel control profile map, if changed, and the new MCC
7693 * (mobile country code).
7694 * The new MCC may be different than what was requested in MCC_UPDATE_CMD.
7695 * @status: see &enum iwl_mcc_update_status
7696 * @mcc: the new applied MCC
7697 * @cap: capabilities for all channels which matches the MCC
7698 * @time: time elapsed from the MCC test start (in units of 30 seconds)
7699 * @geo_info: geographic specific profile information
7700 * see IWX_GEO_*
7701 * @source_id: the MCC source, see IWX_MCC_SOURCE_*
7702 * @reserved: for four bytes alignment.
7703 * @n_channels: number of channels in @channels_data.
7704 * @channels: channel control data map, DWORD for each channel. Only the first
7705 * 16bits are used.
7706 */
7707 struct iwx_mcc_update_resp {
7708 uint32_t status;
7709 uint16_t mcc;
7710 uint16_t cap;
7711 uint16_t time;
7712 uint16_t geo_info;
7713 uint8_t source_id;
7714 uint8_t reserved[3];
7715 uint32_t n_channels;
7716 uint32_t channels[0];
7717 } __packed; /* LAR_UPDATE_MCC_CMD_RESP_S_VER_4 */
7718
7719 /**
7720 * struct iwx_mcc_chub_notif - chub notifies of mcc change
7721 * (MCC_CHUB_UPDATE_CMD = 0xc9)
7722 * The Chub (Communication Hub, CommsHUB) is a HW component that connects to
7723 * the cellular and connectivity cores that gets updates of the mcc, and
7724 * notifies the ucode directly of any mcc change.
7725 * The ucode requests the driver to request the device to update geographic
7726 * regulatory profile according to the given MCC (Mobile Country Code).
7727 * The MCC is two letter-code, ascii upper case[A-Z] or '00' for world domain.
7728 * 'ZZ' MCC will be used to switch to NVM default profile; in this case, the
7729 * MCC in the cmd response will be the relevant MCC in the NVM.
7730 * @mcc: given mobile country code
7731 * @source_id: identity of the change originator, see IWX_MCC_SOURCE_*
7732 * @reserved1: reserved for alignment
7733 */
7734 struct iwx_mcc_chub_notif {
7735 uint16_t mcc;
7736 uint8_t source_id;
7737 uint8_t reserved1;
7738 } __packed; /* LAR_MCC_NOTIFY_S */
7739
7740 enum iwx_mcc_update_status {
7741 IWX_MCC_RESP_NEW_CHAN_PROFILE,
7742 IWX_MCC_RESP_SAME_CHAN_PROFILE,
7743 IWX_MCC_RESP_INVALID,
7744 IWX_MCC_RESP_NVM_DISABLED,
7745 IWX_MCC_RESP_ILLEGAL,
7746 IWX_MCC_RESP_LOW_PRIORITY,
7747 IWX_MCC_RESP_TEST_MODE_ACTIVE,
7748 IWX_MCC_RESP_TEST_MODE_NOT_ACTIVE,
7749 IWX_MCC_RESP_TEST_MODE_DENIAL_OF_SERVICE,
7750 };
7751
7752 #define IWX_MCC_SOURCE_OLD_FW 0
7753 #define IWX_MCC_SOURCE_ME 1
7754 #define IWX_MCC_SOURCE_BIOS 2
7755 #define IWX_MCC_SOURCE_3G_LTE_HOST 3
7756 #define IWX_MCC_SOURCE_3G_LTE_DEVICE 4
7757 #define IWX_MCC_SOURCE_WIFI 5
7758 #define IWX_MCC_SOURCE_RESERVED 6
7759 #define IWX_MCC_SOURCE_DEFAULT 7
7760 #define IWX_MCC_SOURCE_UNINITIALIZED 8
7761 #define IWX_MCC_SOURCE_MCC_API 9
7762 #define IWX_MCC_SOURCE_GET_CURRENT 0x10
7763 #define IWX_MCC_SOURCE_GETTING_MCC_TEST_MODE 0x11
7764
7765 /*
7766 * From Linux commit ab02165ccec4c78162501acedeef1a768acdb811:
7767 * As the firmware is slowly running out of command IDs and grouping of
7768 * commands is desirable anyway, the firmware is extending the command
7769 * header from 4 bytes to 8 bytes to introduce a group (in place of the
7770 * former flags field, since that's always 0 on commands and thus can
7771 * be easily used to distinguish between the two).
7772 *
7773 * These functions retrieve specific information from the id field in
7774 * the iwx_host_cmd struct which contains the command id, the group id,
7775 * and the version of the command.
7776 */
7777 static inline uint8_t
iwx_cmd_opcode(uint32_t cmdid)7778 iwx_cmd_opcode(uint32_t cmdid)
7779 {
7780 return cmdid & 0xff;
7781 }
7782
7783 static inline uint8_t
iwx_cmd_groupid(uint32_t cmdid)7784 iwx_cmd_groupid(uint32_t cmdid)
7785 {
7786 return ((cmdid & 0Xff00) >> 8);
7787 }
7788
7789 static inline uint8_t
iwx_cmd_version(uint32_t cmdid)7790 iwx_cmd_version(uint32_t cmdid)
7791 {
7792 return ((cmdid & 0xff0000) >> 16);
7793 }
7794
7795 static inline uint32_t
iwx_cmd_id(uint8_t opcode,uint8_t groupid,uint8_t version)7796 iwx_cmd_id(uint8_t opcode, uint8_t groupid, uint8_t version)
7797 {
7798 return opcode + (groupid << 8) + (version << 16);
7799 }
7800
7801 /* make uint16_t wide id out of uint8_t group and opcode */
7802 #define IWX_WIDE_ID(grp, opcode) ((grp << 8) | opcode)
7803
7804 struct iwx_cmd_header {
7805 uint8_t code;
7806 uint8_t flags;
7807 uint8_t idx;
7808 uint8_t qid;
7809 } __packed;
7810
7811 struct iwx_cmd_header_wide {
7812 uint8_t opcode;
7813 uint8_t group_id;
7814 uint8_t idx;
7815 uint8_t qid;
7816 uint16_t length;
7817 uint8_t reserved;
7818 uint8_t version;
7819 } __packed;
7820
7821 #define IWX_POWER_SCHEME_CAM 1
7822 #define IWX_POWER_SCHEME_BPS 2
7823 #define IWX_POWER_SCHEME_LP 3
7824
7825 #define IWX_DEF_CMD_PAYLOAD_SIZE 320
7826 #define IWX_MAX_CMD_PAYLOAD_SIZE (4096 - sizeof(struct iwx_cmd_header_wide))
7827 #define IWX_CMD_FAILED_MSK 0x40
7828
7829 /**
7830 * struct iwx_device_cmd
7831 *
7832 * For allocation of the command and tx queues, this establishes the overall
7833 * size of the largest command we send to uCode, except for commands that
7834 * aren't fully copied and use other TFD space.
7835 */
7836 struct iwx_device_cmd {
7837 union {
7838 struct {
7839 struct iwx_cmd_header hdr;
7840 uint8_t data[IWX_DEF_CMD_PAYLOAD_SIZE];
7841 };
7842 struct {
7843 struct iwx_cmd_header_wide hdr_wide;
7844 uint8_t data_wide[IWX_DEF_CMD_PAYLOAD_SIZE -
7845 sizeof(struct iwx_cmd_header_wide) +
7846 sizeof(struct iwx_cmd_header)];
7847 };
7848 };
7849 } __packed;
7850
7851 struct iwx_rx_packet {
7852 /*
7853 * The first 4 bytes of the RX frame header contain both the RX frame
7854 * size and some flags.
7855 * Bit fields:
7856 * 31: flag flush RB request
7857 * 30: flag ignore TC (terminal counter) request
7858 * 29: flag fast IRQ request
7859 * 28-26: Reserved
7860 * 25: Offload enabled
7861 * 24: RPF enabled
7862 * 23: RSS enabled
7863 * 22: Checksum enabled
7864 * 21-16: RX queue
7865 * 15-14: Reserved
7866 * 13-00: RX frame size
7867 */
7868 uint32_t len_n_flags;
7869 struct iwx_cmd_header hdr;
7870 uint8_t data[];
7871 } __packed;
7872
7873 #define IWX_FH_RSCSR_FRAME_SIZE_MSK 0x00003fff
7874 #define IWX_FH_RSCSR_FRAME_INVALID 0x55550000
7875 #define IWX_FH_RSCSR_FRAME_ALIGN 0x40
7876 #define IWX_FH_RSCSR_RPA_EN (1 << 25)
7877 #define IWX_FH_RSCSR_RADA_EN (1 << 26)
7878 #define IWX_FH_RSCSR_RXQ_POS 16
7879 #define IWX_FH_RSCSR_RXQ_MASK 0x3F0000
7880
7881 static uint32_t
iwx_rx_packet_len(const struct iwx_rx_packet * pkt)7882 iwx_rx_packet_len(const struct iwx_rx_packet *pkt)
7883 {
7884
7885 return le32toh(pkt->len_n_flags) & IWX_FH_RSCSR_FRAME_SIZE_MSK;
7886 }
7887
7888 #pragma clang diagnostic push
7889 #pragma clang diagnostic ignored "-Wunused-function"
7890 static uint32_t
iwx_rx_packet_payload_len(const struct iwx_rx_packet * pkt)7891 iwx_rx_packet_payload_len(const struct iwx_rx_packet *pkt)
7892 {
7893
7894 return iwx_rx_packet_len(pkt) - sizeof(pkt->hdr);
7895 }
7896 #pragma clang diagnostic pop
7897
7898 #define IWX_MIN_DBM -100
7899 #define IWX_MAX_DBM -33 /* realistic guess */
7900
7901 #define IWX_READ(sc, reg) \
7902 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg))
7903
7904 #define IWX_WRITE(sc, reg, val) \
7905 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val))
7906
7907 #define IWX_WRITE_1(sc, reg, val) \
7908 bus_space_write_1((sc)->sc_st, (sc)->sc_sh, (reg), (val))
7909
7910 #define IWX_SETBITS(sc, reg, mask) { \
7911 IWX_WRITE(sc, reg, IWX_READ(sc, reg) | (mask)); }
7912
7913 #define IWX_CLRBITS(sc, reg, mask) \
7914 IWX_WRITE(sc, reg, IWX_READ(sc, reg) & ~(mask))
7915
7916 #define IWX_BARRIER_WRITE(sc) \
7917 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
7918 BUS_SPACE_BARRIER_WRITE)
7919
7920 #define IWX_BARRIER_READ_WRITE(sc) \
7921 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, (sc)->sc_sz, \
7922 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE)
7923