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/freebsd/sys/contrib/device-tree/Bindings/usb/
H A Dpxa-usb.txt6 - compatible: Should be "marvell,pxa-ohci" for USB controllers
10 - "marvell,enable-port1", "marvell,enable-port2", "marvell,enable-port3"
11 If present, enables the appropriate USB port of the controller.
12 - "marvell,port-mode" selects the mode of the ports:
16 - "marvell,power-sense-low" - power sense pin is low-active.
17 - "marvell,power-control-low" - power control pin is low-active.
18 - "marvell,no-oc-protection" - disable over-current protection.
19 - "marvell,oc-mode-perport" - enable per-port over-current protection.
20 - "marvell,power_on_delay" Power On to Power Good time - in ms.
25 compatible = "marvell,pxa-ohci";
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H A Dmediatek,mtu3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Chunfeng Yun <chunfeng.yun@mediatek.com>
14 - $ref: usb-drd.yaml
17 The DRD controller has a glue layer IPPC (IP Port Control), and its host is
23 - enum:
24 - mediatek,mt2712-mtu3
25 - mediatek,mt8173-mtu3
26 - mediatek,mt8183-mtu3
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H A Dfsl,imx8mp-dwc3.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc
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H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdr
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H A Dmediatek,mtk-xhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/usb/mediatek,mtk-xhc
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H A Dmediatek,mtu3.txt4 - compatible : should be "mediatek,<soc-model>-mtu3", "mediatek,mtu3",
5 soc-model is the name of SoC, such as mt8173, mt2712 etc,
8 - "mediatek,mt8173-mtu3"
9 - reg : specifies physical base address and size of the registers
10 - reg-names: should be "mac" for device IP and "ippc" for IP port control
11 - interrupts : interrupt used by the device IP
12 - power-domains : a phandle to USB power domain node to control USB's
14 - vusb33-supply : regulator of USB avdd3.3v
15 - clocks : a list of phandle + clock-specifier pairs, one for each
16 entry in clock-names
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H A Dmediatek,mtk-xhci.txt6 the second one supports dual-role mode, and the host is based on xHCI
11 ------------------------------------------------------------------------
14 - compatible : should be "mediatek,<soc-model>-xhci", "mediatek,mtk-xhci",
15 soc-model is the name of SoC, such as mt8173, mt2712 etc, when using
16 "mediatek,mtk-xhci" compatible string, you need SoC specific ones in
18 - "mediatek,mt8173-xhci"
19 - reg : specifies physical base address and size of the registers
20 - reg-names: should be "mac" for xHCI MAC and "ippc" for IP port control
21 - interrupts : interrupt used by the controller
22 - power-domains : a phandle to USB power domain node to control USB's
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/freebsd/share/misc/
H A Dscsi_modes35 # 'i' is a byte-sized integral types, followed by a field width of
38 # 'b' is a bit-sized integral type
39 # 't' is a bitfield type- followed by a bit field width
42 # 'z' values are null-padded strings
55 0x0a "Control" {
81 {Extended Self-Test Completion Time} i2
84 0x0a,0x01 "Control Extension" {
95 0x02 "Disconnect-Reconnect" {
111 0x16 "Extended Device-Type Specific";
121 0x1a "Power Condition" {
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/freebsd/sys/dev/igc/
H A Digc_phy.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
45 #define IGP01IGC_PHY_PORT_CONFIG 0x10 /* Port Config */
47 #define IGP01IGC_PHY_PORT_CTRL 0x12 /* Control */
49 #define IGP02IGC_PHY_POWER_MGMT 0x19 /* Power Management */
54 #define IGC_I225_PHPM 0x0E14 /* I225 PHY Power Management */
55 #define IGC_I225_PHPM_DIS_1000_D3 0x0008 /* Disable 1G in D3 */
58 #define IGC_I225_PHPM_DIS_1000 0x0040 /* Disable 1G globally */
59 #define IGC_I225_PHPM_SPD_B2B_EN 0x0080 /* Smart Power Down Back2Back */
61 #define IGC_I225_PHPM_DIS_100_D3 0x0200 /* Disable 100M in D3 */
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/freebsd/sys/dev/le/
H A Dlancereg.h3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
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/freebsd/sbin/ifconfig/
H A Difconfig.81 .\"-
2 .\" SPDX-License-Identifier: BSD-3-Clause
93 .Bl -tag -width indent
118 Control the output format of
120 The format is specified as a comma-separated list of
141 .Bl -tag -width default
145 .Bl -tag -width default -compact
158 Adjust the display of link-level ethernet (MAC) addresses:
160 .Bl -tag -width default -compact
175 .Bl -tag -width default -compact
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/freebsd/sys/dev/mii/
H A Drlswitch.c1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
19 * 4. Neither the name of the author nor the names of any co-contributors
128 sc->mii_capabilities = BMSR_100TXFDX & sc->mii_capmask; in rlswitch_attach()
139 /* Global Control 0 */ in rlswitch_attach()
143 val |= 1 << 8; /* disable VLAN tag admit control */ in rlswitch_attach()
149 MIIBUS_WRITEREG(sc->mii_dev, 0, 16, val); in rlswitch_attach()
151 /* Global Control 2 */ in rlswitch_attach()
156 val |= 1 << 12; /* forward reserved control frames */ in rlswitch_attach()
157 val |= 1 << 11; /* disable forwarding unicast frames to other VLAN's */ in rlswitch_attach()
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/freebsd/sys/dev/vge/
H A Dif_vgereg.h1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
54 #define VGE_RXCTL 0x06 /* RX control register */
55 #define VGE_TXCTL 0x07 /* TX control register */
76 #define VGE_INTCTL0 0x20 /* interrupt control register */
80 #define VGE_INTCTL1 0x21 /* interrupt control register */
85 #define VGE_TXSTS_PORT 0x2C /* Transmit status port (???) */
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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dcs35l35.txt5 - compatible : "cirrus,cs35l35"
7 - reg : the I2C address of the device for I2C
9 - VA-supply, VP-supply : power supplies for the device,
13 - interrupts : IRQ line info CS35L35.
14 (See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
17 - cirrus,boost-in
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/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_nb_regs.h1 /*-
10 found at http://www.gnu.org/licenses/gpl-2.0.html
101 /* [0x6c] Read-only that reflects CPU Cluster Local GIC base high address */
103 /* [0x70] Read-only that reflects CPU Cluster Local GIC base low address */
105 /* [0x74] Read-only that reflects the device's IOGIC base high address. */
107 /* [0x78] Read-only that reflects IOGIC base low address */
310 /* [0x20] Specifies the state of the CPU with reference to power modes. */
334 /* [0x0] PMU Global Control Register */
336 /* [0x4] PMU Global Control Register */
343 /* [0x4] Counter Control Register */
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/freebsd/sys/dev/msk/
H A Dif_mskreg.h17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
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/freebsd/sys/dev/usb/serial/
H A Dumcs.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
48 #define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1,
50 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong
52 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong
59 #define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2,
62 #define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3,
65 #define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4,
67 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */
71 * endpoint control, R/W */
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/freebsd/sys/dev/e1000/
H A De1000_82571.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2020, Intel Corporation
38 * 82571EB Dual Port Gigabit Mezzanine Adapter
39 * 82571EB Quad Port Gigabit Mezzanine Adapter
40 * 82571PT Gigabit PT Quad Port Server ExpressModule
88 * e1000_init_phy_params_82571 - Init PHY func ptrs.
93 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82571()
98 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82571()
99 phy->type = e1000_phy_none; in e1000_init_phy_params_82571()
103 phy->addr = 1; in e1000_init_phy_params_82571()
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/freebsd/sbin/camcontrol/
H A Dcamcontrol.833 .Nd CAM control program
145 .Bk -words
171 .Op Fl a Ar enable|disable
172 .Op Fl A Ar enable|disable
173 .Op Fl s Ar enable|disable
174 .Op Fl S Ar enable|disable
208 .Op Fl D Ar enable|disable
213 .Op Fl T Ar enable|disable
384 utility allows users to access and control the
402 .Bl -tag -width 14n
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/freebsd/contrib/unbound/doc/
H A Dunbound.conf.53 .\" unbound.conf.5 -- unbound.conf manual
12 \- Unbound configuration file.
27 \fIunbound\-checkconf\fR(8)
34 $ unbound \-c /etc/unbound/unbound.conf
53 # mount \-\-bind \-n /dev/urandom /etc/unbound/dev/urandom
54 # and mount \-\-bind \-n /dev/log /etc/unbound/dev/log
62 access\-control: 10.0.0.0/8 allow
63 access\-control: 2001:DB8::/64 allow
82 .B include\-toplevel:
99 .B statistics\-interval: \fI<seconds>
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H A Dunbound.conf.5.in3 .\" unbound.conf.5 -- unbound.conf manual
12 \- Unbound configuration file.
27 \fIunbound\-checkconf\fR(8)
34 $ unbound \-c /etc/unbound/unbound.conf
53 # mount \-\-bind \-n /dev/urandom /etc/unbound/dev/urandom
54 # and mount \-\-bind \-n /dev/log /etc/unbound/dev/log
62 access\-control: 10.0.0.0/8 allow
63 access\-control: 2001:DB8::/64 allow
82 .B include\-toplevel:
99 .B statistics\-interval: \fI<seconds>
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/freebsd/sys/contrib/device-tree/Bindings/connector/
H A Dusb-connector.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/connector/usb-connector.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ro
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/freebsd/share/man/man4/
H A Dahci.41 .\" Copyright (c) 2009-2013 Alexander Motin <mav@FreeBSD.org>
35 .Bd -ragged -offset indent
44 .Bd -literal -offset indent
50 .Bl -ohang
54 .Bl -tag -width 4n -offset indent -compact
64 Non-zero value enables CCC and defines maximum time (in ms), request can wait
79 controls SATA interface Power Management for the specified channel,
80 allowing some power to be saved at the cost of additional command
84 .Bl -tag -width 4n -offset indent -compact
86 interface Power Management is disabled (default);
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/freebsd/sys/contrib/device-tree/src/arm64/qcom/
H A Dsdm845-cheza.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
25 stdout-path = "serial0:115200n8";
29 compatible = "pwm-backlight";
31 enable-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>;
32 power
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/freebsd/sys/dev/usb/controller/
H A Dehcireg.h1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
45 #define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */
59 * (least-significant byte) and
70 #define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */
78 #define EHCI_HCSP_PORTROUTE 0x0c /* RO Companion port route description */
109 #define EHCI_STS_PCD 0x00000004 /* RWC port change detect */
126 #define EHCI_INTR_PCIE 0x00000004 /* port change ena */
132 #define EHCI_CTRLDSSEGMENT 0x10 /* RW Control Data Structure Segment */
140 #define EHCI_PORTSC(n) (0x40+(4*(n))) /* RO, RW, RWC Port Status reg */
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