Lines Matching +full:disable +full:- +full:port +full:- +full:power +full:- +full:control
3 /*-
4 * SPDX-License-Identifier: BSD-2-Clause
34 /*-
70 * - Am7990 Local Area Network Controller for Ethernet (LANCE)
71 * (and its descendent Am79c90 C-LANCE).
73 * - Am79c900 Integrated Local Area Communications Controller (ILACC)
75 * - Am79c960 PCnet-ISA Single-Chip Ethernet Controller for ISA
77 * - Am79c961 PCnet-ISA+ Jumperless Single-Chip Ethernet Controller
80 * - Am79c961A PCnet-ISA II Jumperless Full-Duplex Single-Chip
83 * - Am79c965A PCnet-32 Single-Chip 32-bit Ethernet Controller
86 * - Am79c970 PCnet-PCI Single-Chip Ethernet Controller for PCI
89 * - Am79c970A PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller
92 * - Am79c971 PCnet-FAST Single-Chip Full-Duplex 10/100Mbps
95 * - Am79c972 PCnet-FAST+ Enhanced 10/100Mbps PCI Ethernet Controller
98 * - Am79c973/Am79c975 PCnet-FAST III Single-Chip 10/100Mbps PCI
101 * - Am79c978 PCnet-Home Single-Chip 1/10 Mbps PCI Home
107 * 16-bit software model (LANCE) am7990reg.h
109 * 32-bit software model (ILACC) am79900reg.h
112 * belong to follow-on chips to the original LANCE. Only CSR0-CSR3 are
122 #define LEMINSIZE (ETHER_MIN_LEN - ETHER_CRC_LEN)
124 #define LE_INITADDR(sc) (sc->sc_initaddr)
125 #define LE_RMDADDR(sc, bix) (sc->sc_rmdaddr + sizeof(struct lermd) * (bix))
126 #define LE_TMDADDR(sc, bix) (sc->sc_tmdaddr + sizeof(struct letmd) * (bix))
127 #define LE_RBUFADDR(sc, bix) (sc->sc_rbufaddr + LEBLEN * (bix))
128 #define LE_TBUFADDR(sc, bix) (sc->sc_tbufaddr + LEBLEN * (bix))
137 * Control and Status Register addresses
139 #define LE_CSR0 0x0000 /* Control and status register */
142 #define LE_CSR3 0x0003 /* Bus master and control */
143 #define LE_CSR4 0x0004 /* Test and features control */
144 #define LE_CSR5 0x0005 /* Extended control and Interrupt 1 */
146 #define LE_CSR7 0x0007 /* Extended control and interrupt 2 */
203 Threshold Control */
214 #define LE_CSR116 0x0074 /* OnNow Power Mode Register */
215 #define LE_CSR122 0x007a /* Advanced Feature Control */
217 #define LE_CSR125 0x007d /* MAC Enhanced Configuration Control */
229 #define LE_BCR9 0x0009 /* Full-duplex Control */
232 #define LE_BCR18 0x0012 /* Burst and Bus Control Register */
233 #define LE_BCR19 0x0013 /* EEPROM Control and Status */
240 #define LE_BCR27 0x001b /* SRAM Interface Control Register */
241 #define LE_BCR28 0x001c /* Exp. Bus Port Addr lower */
242 #define LE_BCR29 0x001d /* Exp. Bus Port Addr upper */
243 #define LE_BCR30 0x001e /* Exp. Bus Data Port */
245 #define LE_BCR32 0x0020 /* PHY Control and Status Register */
249 #define LE_BCR36 0x0024 /* PCI Power Management Cap. Alias */
264 /* Control and status register 0 (csr0) */
278 #define LE_C0_STOP 0x0004 /* disable all external activity */
286 /* Control and status register 3 (csr3) */
293 #define LE_C3_DXSUFLO 0x0040 /* disable tx stop on underflow */
295 #define LE_C3_DXMT2PD 0x0010 /* disable tx two part deferral */
298 #define LE_C3_ACON 0x0002 /* ALE control, eh? */
299 #define LE_C3_BCON 0x0001 /* byte control */
301 /* Control and status register 4 (csr4) */
303 #define LE_C4_DMAPLUS 0x4000 /* always set (PCnet-PCI) */
305 #define LE_C4_TXDPOLL 0x1000 /* disable transmit polling */
318 /* Control and status register 5 (csr5) */
319 #define LE_C5_TOKINTD 0x8000 /* transmit ok interrupt disable */
333 /* Control and status register 6 (csr6) */
337 /* Control and status register 7 (csr7) */
340 #define LE_C7_RDXPOLL 0x1000 /* receive disable polling */
346 #define LE_C7_MAPINT 0x0080 /* PHY management auto-poll intr */
347 #define LE_C7_MAPINTE 0x0040 /* PHY management auto-poll intr
362 /* Control and status register 15 (csr15) */
364 #define LE_C15_DRCVBC 0x4000 /* disable Rx of broadcast */
365 #define LE_C15_DRCVPA 0x2000 /* disable Rx of physical address */
366 #define LE_C15_DLNKTST 0x1000 /* disable link status */
367 #define LE_C15_DAPC 0x0800 /* disable auto-polarity correction */
371 #define LE_C15_PORTSEL(x) ((x) << 7) /* port select */
373 #define LE_C15_DRTY 0x0020 /* disable retry */
375 #define LE_C15_DXMTFCS 0x0008 /* disable Tx FCS (ADD_FCS overrides) */
377 #define LE_C15_DTX 0x0002 /* disable transmit */
378 #define LE_C15_DRX 0x0001 /* disable receiver */
386 /* control and status register 80 (csr80) */
395 /* control and status register 116 (csr116) */
406 /* control and status register 122 (csr122) */
409 /* control and status register 124 (csr124) */
412 /* control and status register 125 (csr125) */
413 #define LE_C125_IPG 0xff00 /* inter-packet gap */
414 #define LE_C125_IFS1 0x00ff /* inter-frame spacing part 1 */
427 #define LE_B2_DXCVRCTL 0x0020 /* DXCVR control */
430 #define LE_B2_AWAKE 0x0004 /* power saving mode select */
431 #define LE_B2_ASEL 0x0002 /* auto-select PORTSEL */
441 #define LE_B4_LEDDIS 0x2000 /* LED disable */
444 #define LE_B4_FDLSE 0x0100 /* full-duplex link status enable */
449 #define LE_B4_POWER 0x0008 /* power enable */
455 #define LE_B9_FDRPAD 0x0004 /* full-duplex runt packet accept
456 disable */
457 #define LE_B9_AUIFD 0x0002 /* AUI full-duplex */
458 #define LE_B9_FDEN 0x0001 /* full-duplex enable */
465 #define LE_B18_DWIO 0x0080 /* double-word I/O */
480 #define LE_B19_EEN 0x0010 /* EEPROM port enable */
488 #define LE_B20_CSRPCNET 0x0200 /* PCnet-style CSRs (0 = ILACC) */
489 #define LE_B20_SSIZE32 0x0100 /* Software Size 32-bit */
491 #define LE_B20_SSTYLE_LANCE 0 /* LANCE/PCnet-ISA (16-bit) */
492 #define LE_B20_SSTYLE_ILACC 1 /* ILACC (32-bit) */
493 #define LE_B20_SSTYLE_PCNETPCI2 2 /* PCnet-PCI (32-bit) */
494 #define LE_B20_SSTYLE_PCNETPCI3 3 /* PCnet-PCI II (32-bit) */
519 #define LE_B28_EADDRL 0xffff /* expansion port address lower */
524 #define LE_B29_EPADDRU 0x0007 /* expansion port address upper */
527 #define LE_B30_EBDATA 0xffff /* expansion bus data port */
536 #define LE_B32_APEP 0x0800 /* auto-poll PHY */
537 #define LE_B32_APDW 0x0700 /* auto-poll dwell time */
538 #define LE_B32_DANAS 0x0080 /* disable autonegotiation */
541 #define LE_B32_XPHYFD 0x0010 /* PHY full-duplex */
550 #define LE_B33_FDX 0x0800 /* full-duplex */
560 #define LE_B49_PCNET 0x8000 /* PCnet mode - Must Be One */
572 /* 0x4000 - 0x0080 are not available on LANCE 7990. */
573 #define LE_MODE_DRCVBC 0x4000 /* disable receive broadcast */
574 #define LE_MODE_DRCVPA 0x2000 /* disable physical address detection */
575 #define LE_MODE_DLNKTST 0x1000 /* disable link status */
576 #define LE_MODE_DAPC 0x0800 /* disable automatic polarity correction */
580 #define LE_MODE_PSEL1 0x0100 /* port selection bit1 */
581 #define LE_MODE_PSEL0 0x0080 /* port selection bit0 */
583 #define LE_MODE_DRTY 0x0020 /* disable retry */
585 #define LE_MODE_DTCR 0x0008 /* disable transmit CRC */
587 #define LE_MODE_DTX 0x0002 /* disable transmitter */
588 #define LE_MODE_DRX 0x0001 /* disable receiver */