Lines Matching +full:disable +full:- +full:port +full:- +full:power +full:- +full:control
17 * are provided to you under the BSD-type license terms provided
22 * - Redistributions of source code must retain the above copyright
24 * - Redistributions in binary form must reproduce the above
28 * - Neither the name of Marvell nor the names of its contributors
48 /*-
49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause
65 * 4. Neither the name of the author nor the names of any co-contributors
82 /*-
110 * D-Link PCI vendor ID
154 * D-Link gigabit ethernet device ID
245 #define PEX_DEV_CTRL 0xe8 /* 16 bit PEX Device Control */
248 #define PEX_LNK_CTRL 0xf0 /* 16 bit PEX Link Control */
262 #define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
263 #define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */
264 #define PCI_Y2_PHY2_COMA BIT_29 /* Set PHY 2 to Coma Mode (YUKON-2) */
265 #define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
266 #define PCI_Y2_PHY2_POWD BIT_27 /* Set PHY 2 to Power Down (YUKON-2) */
267 #define PCI_Y2_PHY1_POWD BIT_26 /* Set PHY 1 to Power Down (YUKON-2) */
268 #define PCI_DIS_BOOT BIT_24 /* Disable BOOT via ROM */
272 /* 0 = Disable addr. dec */
279 #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
281 #define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */
282 #define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */
283 #define PCI_DIS_MWI BIT_11 /* Disable Mem Write & Invalidate */
285 #define PCI_BURST_DIS BIT_9 /* Burst Disable */
286 #define PCI_DIS_PCI_CLK BIT_8 /* Disable PCI clock driving */
289 #define PCI_CLS_OPT BIT_3 /* Cache Line Size opt. PCI-X (YUKON-2) */
310 /* PCI_OUR_STATUS 32 bit Adapter Status Register (Yukon-2) */
312 #define PCI_OS_PCIX BIT_30 /* PCI-X Bus */
313 #define PCI_OS_MODE_MSK (3<<28) /* Bit 29..28: PCI-X Bus Mode Mask */
315 #define PCI_OS_PCI_X BIT_26 /* PCI/PCI-X Bus (0 = PEX) */
320 #define PCI_OS_SPEED(val) ((val & PCI_OS_MODE_MSK) >> 28) /* PCI-X Speed */
323 #define PCI_OS_SPD_X66 1 /* PCI-X 66MHz Bus */
324 #define PCI_OS_SPD_X100 2 /* PCI-X 100MHz Bus */
325 #define PCI_OS_SPD_X133 3 /* PCI-X 133MHz Bus */
327 /* PCI_OUR_REG_3 32 bit Our Register 3 (Yukon-ECU only) */
328 #define PCI_CLK_MACSEC_DIS BIT_17 /* Disable Clock MACSec. */
330 /* PCI_OUR_REG_4 32 bit Our Register 4 (Yukon-ECU only) */
337 #define PCI_ASPM_CLKREQ_PAD_CTL BIT_3 /* CLKREQ PAD Control (A1 only) */
342 /* PCI_OUR_REG_5 32 bit Our Register 5 (Yukon-ECU only) */
345 #define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */
346 #define PCI_CTL_BYPASS_VMAIN_AV BIT_29 /* Bypass En. for Vmain_av De-Glitch */
351 #define PCI_REL_PCIE_RST_DE_ASS BIT_26 /* PCIe Reset De-Asserted */
354 #define PCI_REL_MAIN_PWR_AVAIL BIT_23 /* Main Power Available */
366 #define PCI_GAT_MAIN_PWR_N_AVAIL BIT_7 /* Main Power Not Available */
369 #define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
380 #define PCI_CF1_REL_PCIE_RESET BIT_21 /* PCI-E reset */
383 #define PCI_CF1_GAT_PCIE_RX_IDLE BIT_19 /* PCI-E Rx Electrical idle */
384 #define PCI_CF1_GAT_PCIE_RESET BIT_18 /* PCI-E Reset */
385 #define PCI_CF1_PRST_PHY_CLKREQ BIT_17 /* Enable PCI-E rst & PM2PHY gen. CLKREQ */
386 #define PCI_CF1_PCIE_RST_CLKREQ BIT_16 /* Enable PCI-E rst generate CLKREQ */
392 /* PEX_DEV_CTRL 16 bit PEX Device Control (Yukon-2) */
395 #define PEX_DC_EN_AUX_POW BIT_10 /* Enable AUX Power */
402 #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */
407 /* PEX_LNK_STAT 16 bit PEX Link Status (Yukon-2) */
414 /* PEX_UNC_ERR_STAT PEX Uncorrectable Errors Status Register (Yukon-2) */
420 #define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */
426 /* Control Register File (Address Map) */
431 #define B0_RAP 0x0000 /* 8 bit Register Address Port */
432 #define B0_CTST 0x0004 /* 16 bit Control/Status register */
434 #define B0_POWER_CTRL 0x0007 /* 8 Bit Power Control reg (YUKON only) */
441 /* Special ISR registers (Yukon-2 only) */
446 #define B0_Y2_SP_ICR 0x002c /* 32 bit Interrupt Control Reg */
450 * - completely empty (this is the RAP Block window)
466 #define B2_Y2_CLK_GATE 0x011d /* 8 bit Clock Gating (Yukon-2) */
467 #define B2_Y2_HW_RES 0x011e /* 8 bit HW Resources (Yukon-2) */
469 #define B2_Y2_CLK_CTRL 0x0120 /* 32 bit Core Clock Frequency Control */
472 #define B2_TI_CTRL 0x0138 /* 8 bit Timer Control */
476 #define B2_IRQM_CTRL 0x0148 /* 8 bit IRQ Moderation Timer Control */
480 #define B2_TST_CTRL1 0x0158 /* 8 bit Test Control Register 1 */
481 #define B2_TST_CTRL2 0x0159 /* 8 bit Test Control Register 2 */
483 #define B2_I2C_CTRL 0x0160 /* 32 bit I2C HW Control Register */
486 #define B2_I2C_SW 0x016c /* 32 bit I2C SW Port Register */
499 #define SELECT_RAM_BUFFER(rb, addr) (addr | (rb << 6)) /* Yukon-2 only */
502 /* Yukon-2: use SELECT_RAM_BUFFER() to access the RAM buffer */
504 * The HW-Spec. calls this registers Timeout Value 0..11. But this names are
521 #define B3_RI_CTRL 0x01a0 /* 16 bit RAM Interface Control Register */
525 * Bank 4 - 5
532 #define TXA_CTRL 0x0210 /* 8 bit Tx Arbiter Control Register */
538 /* RSS key registers for Yukon-2 Family */
539 #define B4_RSS_KEY 0x0220 /* 4x32 bit RSS Key register (Yukon-2) */
545 /* 0x0280 - 0x0292: MAC 2 */
546 #define RSS_KEY_ADDR(Port, KeyIndex) \ argument
547 ((B4_RSS_KEY | ( ((Port) == 0) ? 0 : 0x80)) + (KeyIndex))
550 * Bank 8 - 15
562 #define Q_CSR 0x34 /* 32 bit BMU Control/Status Register */
585 #define PREF_UNIT_CTRL_REG 0x00 /* 32 bit Prefetch Control register */
601 * Bank 16 - 23
617 #define RB_CTRL 0x28 /* 8 bit RAM Buffer Control Register */
624 /* Receive GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
627 #define RX_GMF_CTRL_T 0x0c48 /* 32 bit Rx GMAC FIFO Control/Test */
630 #define RX_GMF_TR_THR 0x0c54 /* 32 bit Rx Truncation Threshold (Yukon-2) */
631 #define RX_GMF_UP_THR 0x0c58 /* 16 bit Rx Upper Pause Thr (Yukon-EC_U) */
632 #define RX_GMF_LP_THR 0x0c5a /* 16 bit Rx Lower Pause Thr (Yukon-EC_U) */
633 #define RX_GMF_VLAN 0x0c5c /* 32 bit Rx VLAN Type Register (Yukon-2) */
642 /* 0x0c80 - 0x0cbf: MAC 2 */
643 /* 0x0cc0 - 0x0cff: reserved */
648 /* Transmit GMAC FIFO (YUKON and Yukon-2), use MR_ADDR() to access */
651 #define TX_GMF_CTRL_T 0x0d48 /* 32 bit Tx GMAC FIFO Control/Test */
652 #define TX_GMF_VLAN 0x0d5c /* 32 bit Tx VLAN Type Register (Yukon-2) */
663 /* 0x0d80 - 0x0dbf: MAC 2 */
664 /* 0x0daa - 0x0dff: reserved */
678 /* Polling Unit Registers (Yukon-2 only) */
679 #define POLL_CTRL 0x0e20 /* 32 bit Polling Unit Control Reg */
683 /* ASF Subsystem Registers (Yukon-2 only) */
685 #define B28_Y2_SMB_CSD_REG 0x0e44 /* 32 bit ASF SMB Control/Status/Data */
700 /* Status BMU Registers (Yukon-2 only)*/
701 #define STAT_CTRL 0x0e80 /* 32 bit Status BMU Control Reg */
711 /* FIFO Control/Status Registers (Yukon-2 only)*/
719 /* Level and ISR Timer Registers (Yukon-2 only)*/
722 #define STAT_LEV_TIMER_CTRL 0x0eb8 /* 8 bit Level Timer Control Reg */
726 #define STAT_TX_TIMER_CTRL 0x0ec8 /* 8 bit Tx Timer Control Reg */
730 #define STAT_ISR_TIMER_CTRL 0x0ed8 /* 8 bit ISR Timer Control Reg */
741 /* GMAC and GPHY Control Registers (YUKON only) */
742 #define GMAC_CTRL 0x0f00 /* 32 bit GMAC Control Reg */
743 #define GPHY_CTRL 0x0f04 /* 32 bit GPHY Control Reg */
746 #define GMAC_LINK_CTRL 0x0f10 /* 16 bit Link Control Reg */
748 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
750 #define WOL_REG_OFFS 0x20 /* HW-Bug: Address is + 0x20 against spec. */
752 #define WOL_CTRL_STAT 0x0f20 /* 16 bit WOL Control/Status Reg */
753 #define WOL_MATCH_CTL 0x0f22 /* 8 bit WOL Match Control Reg */
757 #define WOL_PATT_PME 0x0f2a /* 8 bit WOL PME Match Enable (Yukon-2) */
758 #define WOL_PATT_ASFM 0x0f2b /* 8 bit WOL ASF Match Enable (Yukon-2) */
772 * Bank 32 - 33
777 /* offset to configuration space on Yukon-2 */
783 * Control Register Bit Definitions:
785 /* B0_CTST 24 bit Control/Status register */
786 #define Y2_VMAIN_AVAIL BIT_17 /* VMAIN available (YUKON-2 only) */
787 #define Y2_VAUX_AVAIL BIT_16 /* VAUX available (YUKON-2 only) */
788 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */
789 #define Y2_HW_WOL_OFF BIT_14 /* HW WOL Off (Yukon-EC Ultra A1 only) */
790 #define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */
791 #define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */
792 #define Y2_CLK_RUN_ENA BIT_11 /* CLK_RUN Enable (YUKON-2 only) */
793 #define Y2_CLK_RUN_DIS BIT_10 /* CLK_RUN Disable (YUKON-2 only) */
794 #define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */
795 #define Y2_LED_STAT_OFF BIT_8 /* Status LED Off (YUKON-2 only) */
808 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
810 #define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
812 #define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
826 #define Y2_IS_PORT_MASK(Port, Mask) ((Mask) << (Port*8)) argument
848 #define Y2_IS_L1_MASK 0x0000001f /* IRQ Mask for port 1 */
850 #define Y2_IS_L2_MASK 0x00001f00 /* IRQ Mask for port 2 */
866 #define Y2_IS_PCI_EXP BIT_25 /* PCI-Express interrupt */
867 #define Y2_IS_PCI_NEXP BIT_24 /* PCI-Express error similar to PCI error */
892 #define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */
898 #define CHIP_ID_YUKON_LITE 0xb1 /* Chip ID for YUKON-Lite (Rev. A1-A3) */
899 #define CHIP_ID_YUKON_LP 0xb2 /* Chip ID for YUKON-LP */
900 #define CHIP_ID_YUKON_XL 0xb3 /* Chip ID for YUKON-2 XL */
901 #define CHIP_ID_YUKON_EC_U 0xb4 /* Chip ID for YUKON-2 EC Ultra */
902 #define CHIP_ID_YUKON_EX 0xb5 /* Chip ID for YUKON-2 Extreme */
903 #define CHIP_ID_YUKON_EC 0xb6 /* Chip ID for YUKON-2 EC */
904 #define CHIP_ID_YUKON_FE 0xb7 /* Chip ID for YUKON-2 FE */
905 #define CHIP_ID_YUKON_FE_P 0xb8 /* Chip ID for YUKON-2 FE+ */
906 #define CHIP_ID_YUKON_SUPR 0xb9 /* Chip ID for YUKON-2 Supreme */
907 #define CHIP_ID_YUKON_UL_2 0xba /* Chip ID for YUKON-2 Ultra 2 */
909 #define CHIP_ID_YUKON_OPT 0xbc /* Chip ID for YUKON-2 Optima */
911 #define CHIP_REV_YU_XL_A0 0 /* Chip Rev. for Yukon-2 A0 */
912 #define CHIP_REV_YU_XL_A1 1 /* Chip Rev. for Yukon-2 A1 */
913 #define CHIP_REV_YU_XL_A2 2 /* Chip Rev. for Yukon-2 A2 */
914 #define CHIP_REV_YU_XL_A3 3 /* Chip Rev. for Yukon-2 A3 */
916 #define CHIP_REV_YU_EC_A1 0 /* Chip Rev. for Yukon-EC A1/A0 */
917 #define CHIP_REV_YU_EC_A2 1 /* Chip Rev. for Yukon-EC A2 */
918 #define CHIP_REV_YU_EC_A3 2 /* Chip Rev. for Yukon-EC A3 */
923 #define CHIP_REV_YU_FE_P_A0 0 /* Chip Rev. for Yukon-2 FE+ A0 */
925 #define CHIP_REV_YU_EX_A0 1 /* Chip Rev. for Yukon-2 EX A0 */
926 #define CHIP_REV_YU_EX_B0 2 /* Chip Rev. for Yukon-2 EX B0 */
928 #define CHIP_REV_YU_SU_A0 0 /* Chip Rev. for Yukon-2 SUPR A0 */
929 #define CHIP_REV_YU_SU_B0 1 /* Chip Rev. for Yukon-2 SUPR B0 */
930 #define CHIP_REV_YU_SU_B1 3 /* Chip Rev. for Yukon-2 SUPR B1 */
932 /* B2_Y2_CLK_GATE 8 bit Clock Gating (Yukon-2 only) */
934 #define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */
935 #define Y2_COR_CLK_LNK2_DIS BIT_5 /* Disable Core clock Link 2 */
936 #define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */
938 #define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */
939 #define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */
940 #define Y2_PCI_CLK_LNK1_DIS BIT_0 /* Disable PCI clock Link 1 */
942 /* B2_Y2_HW_RES 8 bit HW Resources (Yukon-2 only) */
953 /* B2_Y2_CLK_CTRL 32 bit Core Clock Frequency Control Register (Yukon-2/EC) */
954 /* Yukon-EC/FE */
957 /* Yukon-2 */
963 #define Y2_CLK_DIV_DIS BIT_0 /* Disable Core Clock Division */
965 /* B2_TI_CTRL 8 bit Timer control */
966 /* B2_IRQM_CTRL 8 bit IRQ Moderation Timer Control */
986 /* B2_TST_CTRL1 8 bit Test Control Register 1 */
994 #define TST_CFG_WRITE_OFF BIT_0 /* Disable Config Reg WR */
1000 #define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */
1002 #define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */
1008 /* B2_I2C_CTRL 32 bit I2C HW Control Register */
1027 /* B2_I2C_SW 32 bit (8 bit access) I2C HW SW Port Register */
1029 #define I2C_DATA BIT_1 /* I2C Data Port */
1030 #define I2C_CLK BIT_0 /* I2C Clock Port */
1036 /* B2_BSC_CTRL 8 bit Blink Source Counter Control */
1048 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
1056 /* B3_RI_CTRL 16 bit RAM Interface Control Register */
1071 /* TXA_CTRL 8 bit Tx Arbiter Control Register */
1073 #define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */
1075 #define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */
1076 #define TXA_START_RC BIT_3 /* Start sync Rate Control */
1077 #define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */
1079 #define TXA_DIS_ARB BIT_0 /* Disable Tx Arbiter */
1095 /* Rx BMU Control / Status Registers (Yukon-2) */
1100 #define BMU_DIS_RX_RSS_HASH BIT_14 /* Disable Rx RSS Hash */
1102 #define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */
1121 /* Tx BMU Control / Status Registers (Yukon-2) */
1124 #define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */
1129 #define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/
1130 #define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/
1135 #define F_M_RX_RAM_DIS BIT_24 /* MAC Rx RAM Read Port disable */
1140 /* Queue Prefetch Unit Offsets, use Y2_PREF_Q_ADDR() to address (Yukon-2 only)*/
1141 /* PREF_UNIT_CTRL_REG 32 bit Prefetch Control register */
1174 /* RB_CTRL 8 bit RAM Buffer Control Register */
1176 #define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */
1178 #define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */
1187 /* Threshold values for Yukon-EC Ultra */
1221 /* WOL_CTRL_STAT 16 bit WOL Control/Status Reg */
1247 /* WOL_MATCH_CTL 8 bit WOL Match Control Reg */
1250 /* WOL_PATT_PME 8 bit WOL PME Match Enable (Yukon-2) */
1256 * Marvel-PHY Registers, indirect addressed over GMAC
1258 #define PHY_MARV_CTRL 0x00 /* 16 bit r/w PHY Control Register */
1262 #define PHY_MARV_AUNE_ADV 0x04 /* 16 bit r/w Auto-Neg. Advertisement */
1264 #define PHY_MARV_AUNE_EXP 0x06 /* 16 bit r/o Auto-Neg. Expansion Reg */
1267 /* Marvel-specific registers */
1268 #define PHY_MARV_1000T_CTRL 0x09 /* 16 bit r/w 1000Base-T Control Reg */
1269 #define PHY_MARV_1000T_STAT 0x0a /* 16 bit r/o 1000Base-T Status Reg */
1270 /* 0x0b - 0x0e: reserved */
1272 #define PHY_MARV_PHY_CTRL 0x10 /* 16 bit r/w PHY Specific Control Reg */
1279 #define PHY_MARV_PORT_IRQ 0x17 /* 16 bit r/o Port 0 IRQ (88E1111 only) */
1280 #define PHY_MARV_LED_CTRL 0x18 /* 16 bit r/w LED Control Reg */
1293 #define PHY_MARV_FE_SPEC_2 0x1c /* 16 bit r/w Specific Control Reg. 2 */
1298 #define PHY_CT_ANE (1<<12) /* Bit 12: Auto-Negotiation Enabled */
1299 #define PHY_CT_PDOWN (1<<11) /* Bit 11: Power Down Mode */
1301 #define PHY_CT_RE_CFG (1<<9) /* Bit 9: (sc) Restart Auto-Negotiation */
1312 #define PHY_ST_AN_OVER (1<<5) /* Bit 5: Auto-Negotiation Over */
1314 #define PHY_ST_AN_CAP (1<<3) /* Bit 3: Auto-Negotiation Capability */
1327 #define PHY_MARV_ID1_B2 0x0C25 /* Yukon-Plus (PHY 88E1011) */
1328 #define PHY_MARV_ID1_C2 0x0CC2 /* Yukon-EC (PHY 88E1111) */
1329 #define PHY_MARV_ID1_Y2 0x0C91 /* Yukon-2 (PHY 88E1112) */
1330 #define PHY_MARV_ID1_FE 0x0C83 /* Yukon-FE (PHY 88E3082 Rev.A1) */
1331 #define PHY_MARV_ID1_ECU 0x0CB0 /* Yukon-2 (PHY 88E1149 Rev.B2?) */
1333 /***** PHY_MARV_1000T_STAT 16 bit r/o 1000Base-T Status Reg *****/
1342 /***** PHY_MARV_AUNE_ADV 16 bit r/w Auto-Negotiation Advertisement *****/
1349 #define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */
1350 #define PHY_M_AN_100_FD BIT_8 /* Advertise 100Base-TX Full Duplex */
1351 #define PHY_M_AN_100_HD BIT_7 /* Advertise 100Base-TX Half Duplex */
1352 #define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
1353 #define PHY_M_AN_10_HD BIT_5 /* Advertise 10Base-TX Half Duplex */
1359 #define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
1360 #define PHY_M_AN_1000X_AFD BIT_5 /* Advertise 10000Base-X Full Duplex */
1368 /***** PHY_MARV_1000T_CTRL 16 bit r/w 1000Base-T Control Reg *****/
1372 #define PHY_M_1000C_MPD BIT_10 /* Multi-Port Device */
1384 #define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */
1385 #define PHY_M_PC_MAC_POW_UP BIT_3 /* MAC Power up */
1388 #define PHY_M_PC_DIS_JABBER BIT_0 /* Disable Jabber */
1399 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1400 #define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */
1403 /* !!! Errata in spec. (1 = disable) */
1412 #define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */
1414 #define PHY_M_PC_DIS_NLP_GN BIT_11 /* Disable Normal Link Puls Generation */
1415 #define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */
1416 #define PHY_M_PC_DIS_FEFI BIT_8 /* Disable Far End Fault Indic. (FEFI) */
1446 #define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */
1450 #define PHY_M_IS_AN_COMPL BIT_11 /* Auto-Negotiation Completed */
1458 #define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */
1468 #define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */
1476 /* !!! Errata in spec. (1 = disable) */
1477 #define PHY_M_EC_RX_TIM_CT BIT_7 /* RGMII Rx Timing Control*/
1479 #define PHY_M_EC_FIB_AN_ENA BIT_3 /* Fiber Auto-Neg. Enable (88E1011S only) */
1481 #define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */
1482 #define PHY_M_EC_TRANS_DIS BIT_0 /* Transmitter Disable (88E1111 only) */
1498 /***** PHY_MARV_LED_CTRL 16 bit r/w LED Control Reg *****/
1499 #define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */
1503 #define PHY_M_LEDC_DP_C_LSB BIT_7 /* Duplex Control (LSB, 88E1111 only) */
1504 #define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */
1505 #define PHY_M_LEDC_LK_C_MSK (7<<3) /* Bit 5.. 3: Link Control Mask */
1507 #define PHY_M_LEDC_LINK_MSK (3<<3) /* Bit 4.. 3: Link Control Mask */
1509 #define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */
1510 #define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */
1513 #define PHY_M_LEDC_TX_C_MSB BIT_0 /* Tx Control (MSB, 88E1111 only) */
1562 #define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */
1565 #define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */
1570 #define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */
1610 /***** PHY_MARV_FE_SPEC_2 16 bit r/w Specific Control Reg. 2 *****/
1611 #define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */
1613 #define PHY_M_FESC_SEL_CL_A BIT_0 /* Select Class A driver (100B-TX) */
1615 /* for Yukon-2 Gigabit Ethernet PHY (88E1112 only) */
1619 #define PHY_M_FIB_TX_DIS BIT_3 /* Transmitter Disable */
1623 #define PHY_M_MAC_MD_AUTO 3 /* Auto Copper/1000Base-X */
1625 #define PHY_M_MAC_MD_1000BX 7 /* 1000Base-X only */
1628 /***** PHY_MARV_PHY_CTRL (page 3) 16 bit r/w LED Control Reg. *****/
1639 /***** PHY_MARV_PHY_STAT (page 3) 16 bit r/w Polarity Control Reg. *****/
1664 /* Port Registers */
1666 #define GM_GP_CTRL 0x0004 /* 16 bit r/w General Purpose Control */
1667 #define GM_TX_CTRL 0x0008 /* 16 bit r/w Transmit Control Reg. */
1668 #define GM_RX_CTRL 0x000c /* 16 bit r/w Receive Control Reg. */
1669 #define GM_TX_FLOW_CTRL 0x0010 /* 16 bit r/w Transmit Flow-Control */
1698 #define GM_SMI_CTRL 0x0080 /* 16 bit r/w SMI Control Register */
1707 * MIB Counters base address definitions (low word) -
1737 (GM_MIB_CNT_BASE + 104) /* 65-127 Byte Rx Frame */
1739 (GM_MIB_CNT_BASE + 112) /* 128-255 Byte Rx Frame */
1741 (GM_MIB_CNT_BASE + 120) /* 256-511 Byte Rx Frame */
1743 (GM_MIB_CNT_BASE + 128) /* 512-1023 Byte Rx Frame */
1745 (GM_MIB_CNT_BASE + 136) /* 1024-1518 Byte Rx Frame */
1747 (GM_MIB_CNT_BASE + 144) /* 1519-MaxSize Byte Rx Frame */
1773 (GM_MIB_CNT_BASE + 248) /* 65-127 Byte Tx Frame */
1775 (GM_MIB_CNT_BASE + 256) /* 128-255 Byte Tx Frame */
1777 (GM_MIB_CNT_BASE + 264) /* 256-511 Byte Tx Frame */
1779 (GM_MIB_CNT_BASE + 272) /* 512-1023 Byte Tx Frame */
1781 (GM_MIB_CNT_BASE + 280) /* 1024-1518 Byte Tx Frame */
1783 (GM_MIB_CNT_BASE + 288) /* 1519-MaxSize Byte Tx Frame */
1799 /*----------------------------------------------------------------------------*/
1811 #define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */
1813 #define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */
1822 #define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */
1824 /* GM_GP_CTRL 16 bit r/w General Purpose Control Register */
1825 #define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */
1826 #define GM_GPCR_RMII_LB_ENA BIT_14 /* Enable RMII Loopback (Yukon-FE only) */
1827 #define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */
1835 #define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */
1836 #define GM_GPCR_SPEED_100 BIT_3 /* Port Speed 100 Mbps */
1837 #define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */
1838 #define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */
1839 #define GM_GPCR_AU_SPD_DIS BIT_0 /* Disable Auto-Update Speed */
1845 /* GM_TX_CTRL 16 bit r/w Transmit Control Register */
1846 #define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */
1847 #define GM_TXCR_CRC_DIS BIT_14 /* Disable insertion of CRC */
1848 #define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */
1851 /* (Yukon-2 only) */
1856 /* GM_RX_CTRL 16 bit r/w Receive Control Register */
1859 #define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */
1860 #define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */
1867 /* (Yukon-2 only) */
1881 /* r/o on Yukon, r/w on Yukon-EC */
1885 #define GM_SMOD_IPG_MSK 0x1f /* Bit 4.. 0: Inter-Packet Gap (IPG) */
1893 /* GM_SMI_CTRL 16 bit r/w SMI Control Register */
1915 #define GMR_FS_GOOD_FC BIT_7 /* Good Flow-Control Packet */
1916 #define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
1956 /* RX_GMF_CTRL_T 32 bit Rx GMAC FIFO Control/Test */
1958 #define RX_TRUNC_OFF BIT_26 /* disable packet truncation */
1960 #define RX_VLAN_STRIP_OFF BIT_24 /* disable VLAN stripping */
1964 #define GMF_RX_OVER_OFF BIT_18 /* disable flushing on receive overrun */
1966 #define GMF_ASF_RX_OVER_OFF BIT_16 /* disable flushing of ASF when overrun */
1982 /* TX_GMF_CTRL_T 32 bit Tx GMAC FIFO Control/Test (YUKON and Yukon-2) */
1983 #define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
1984 #define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */
1986 #define TX_VLAN_TAG_OFF BIT_24 /* disable VLAN tagging */
1987 #define TX_JUMBO_ENA BIT_23 /* Enable Jumbo Mode (Yukon-EC Ultra) */
1988 #define TX_JUMBO_DIS BIT_22 /* Disable Jumbo Mode (Yukon-EC Ultra) */
2009 /* POLL_CTRL 32 bit Polling Unit control register (Yukon-2 only) */
2028 /* B28_Y2_ASF_HCU_CCSR 32bit CPU Control and Status Register (Yukon EX) */
2055 /* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
2062 /* GMAC_CTRL 32 bit GMAC Control Reg (YUKON only) */
2080 /* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
2081 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
2084 #define GPC_DIS_FC BIT_25 /* Disable Automatic Fiber/Copper Detection */
2085 #define GPC_DIS_SLEEP BIT_24 /* Disable Energy Detect */
2092 #define GPC_DIS_125 BIT_17 /* Disable 125 MHz clock */
2116 /* GMAC_LINK_CTRL 16 bit GMAC Link Control Reg (YUKON only) */
2125 bus_write_4((sc)->msk_res[0], (reg), (val))
2127 bus_write_2((sc)->msk_res[0], (reg), (val))
2129 bus_write_1((sc)->msk_res[0], (reg), (val))
2132 bus_read_4((sc)->msk_res[0], (reg))
2134 bus_read_2((sc)->msk_res[0], (reg))
2136 bus_read_1((sc)->msk_res[0], (reg))
2139 bus_write_4((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2141 bus_write_2((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2143 bus_write_1((sc)->msk_res[0], Y2_CFG_SPC + (reg), (val))
2146 bus_read_4((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2148 bus_read_2((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2150 bus_read_1((sc)->msk_res[0], Y2_CFG_SPC + (reg))
2153 CSR_READ_4((sc_if)->msk_softc, (reg))
2155 CSR_READ_2((sc_if)->msk_softc, (reg))
2157 CSR_READ_1((sc_if)->msk_softc, (reg))
2160 CSR_WRITE_4((sc_if)->msk_softc, (reg), (val))
2162 CSR_WRITE_2((sc_if)->msk_softc, (reg), (val))
2164 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))
2166 #define GMAC_REG(port, reg) \ argument
2167 ((BASE_GMAC_1 + (port) * (BASE_GMAC_2 - BASE_GMAC_1)) | (reg))
2168 #define GMAC_WRITE_2(sc, port, reg, val) \ argument
2169 CSR_WRITE_2((sc), GMAC_REG((port), (reg)), (val))
2170 #define GMAC_READ_2(sc, port, reg) \ argument
2171 CSR_READ_2((sc), GMAC_REG((port), (reg)))
2173 /* GPHY address (bits 15..11 of SMI control reg) */
2200 /* mask and shift value to get Tx async queue status for port 1 */
2204 /* mask and shift value to get Tx sync queue status for port 1 */
2208 /* mask and shift value to get Tx async queue status for port 2 */
2215 /* mask and shift value to get Tx sync queue status for port 2 */
2221 /* YUKON-2 bit values */
2227 /* YUKON-2 Control flags */
2244 /* YUKON-2 Rx/Tx opcodes defines */
2265 /* YUKON-2 STATUS opcodes defines */
2275 /* YUKON-2 SPECIAL opcodes defines */
2293 /* TxCtrl Transmit Buffer Control Field */
2294 /* RxCtrl Receive Buffer Control Field */
2302 #define BMU_NO_FCS BIT_25 /* (Tx) Disable MAC FCS (CRC) generation */
2357 #define MSK_JUMBO_MTU (MSK_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2359 (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)
2360 #define MSK_MIN_FRAMELEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
2412 ((sc)->msk_rdata.msk_tx_ring_paddr + sizeof(struct msk_tx_desc) * (i))
2414 ((sc)->msk_rdata.msk_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2416 ((sc)->msk_rdata.msk_jumbo_rx_ring_paddr + sizeof(struct msk_rx_desc) * (i))
2442 #define MSK_PROC_MAX (MSK_RX_RING_CNT - 1)
2450 int port; member
2543 #define MSK_LOCK(_sc) mtx_lock(&(_sc)->msk_mtx)
2544 #define MSK_UNLOCK(_sc) mtx_unlock(&(_sc)->msk_mtx)
2545 #define MSK_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->msk_mtx, MA_OWNED)
2546 #define MSK_IF_LOCK(_sc) MSK_LOCK((_sc)->msk_softc)
2547 #define MSK_IF_UNLOCK(_sc) MSK_UNLOCK((_sc)->msk_softc)
2548 #define MSK_IF_LOCK_ASSERT(_sc) MSK_LOCK_ASSERT((_sc)->msk_softc)
2550 #define MSK_USECS(sc, us) ((sc)->msk_clock * (us))
2557 int32_t msk_port; /* port # on controller */