Lines Matching +full:disable +full:- +full:port +full:- +full:power +full:- +full:control
1 /*-
2 * SPDX-License-Identifier: BSD-4-Clause
18 * 4. Neither the name of the author nor the names of any co-contributors
37 * Definitions for the built-in copper PHY can be found in vgphy.h.
41 * using 32-bit I/O cycles, but some of them are less than 32 bits
54 #define VGE_RXCTL 0x06 /* RX control register */
55 #define VGE_TXCTL 0x07 /* TX control register */
76 #define VGE_INTCTL0 0x20 /* interrupt control register */
80 #define VGE_INTCTL1 0x21 /* interrupt control register */
85 #define VGE_TXSTS_PORT 0x2C /* Transmit status port (???) */
109 #define VGE_CAMCTL 0x69 /* CAM control register */
112 #define VGE_MIICFG 0x6C /* MII port config register */
113 #define VGE_MIISTS 0x6D /* MII port status register */
119 #define VGE_SSTIMER 0x74 /* single-shot timer */
129 #define VGE_PWRMGMT 0x82 /* power management shadow register */
130 #define VGE_PWRSTAT 0x83 /* power state shadow register */
131 #define VGE_MIBCSR 0x84 /* MIB control/status register */
136 #define VGE_EECSR 0x93 /* EEPROM control/status */
143 #define VGE_DBGCTL 0x9E /* Chip debug control */
144 #define VGE_DIAGCTL 0x9F /* Chip diagnostic control */
147 #define VGE_PWRCFGS 0xA2 /* Power management config set */
151 #define VGE_PWRCFGC 0xA6 /* Power management config clear */
182 /* Receive control register */
193 /* Transmit control register */
195 #define VGE_TXCTL_LOOPCTL 0x03 /* loopback control */
196 #define VGE_TXCTL_COLLCTL 0x0C /* collision retry control */
216 #define VGE_CR1_NOUCAST 0x01 /* disable unicast reception */
217 #define VGE_CR1_NOPOLL 0x08 /* disable RX/TX desc polling */
226 #define VGE_CR2_HDX_FLOWCTL_ENABLE 0x10 /* half duplex flow control */
227 #define VGE_CR2_FDX_RXFLOWCTL_ENABLE 0x20 /* full duplex RX flow control */
228 #define VGE_CR2_FDX_TXFLOWCTL_ENABLE 0x40 /* full duplex TX flow control */
229 #define VGE_CR2_XON_ENABLE 0x80 /* 802.3x XON/XOFF flow control */
233 #define VGE_CR3_INT_SWPEND 0x01 /* disable multi-level int bits */
240 /* Interrupt control register */
246 #define VGE_INTCTL_RXINTSUP_DISABLE 0x20 /* disable RX int supression */
247 #define VGE_INTCTL_TXINTSUP_DISABLE 0x40 /* disable TX int supression */
287 #define VGE_ISR_PWR 0x00040000 /* wake up power event */
325 #define VGE_IMR_PWR 0x00040000 /* wake up power event */
338 /* TX descriptor queue control/status register */
357 /* RX descriptor queue control/status register */
386 * - The behavior of the MAR0/MAR1 registers at offset 0x10 (the
387 * page select bits control whether the MAR0/MAR1 registers affect
389 * - The behavior of the interrupt holdoff timer register at offset
393 * - The behavior the WOL pattern programming registers at offset
414 /* MII port config register */
425 /* MII port status register */
431 #define VGE_PHYSTS_TXFLOWCAP 0x01 /* resolved TX flow control cap */
432 #define VGE_PHYSTS_RXFLOWCAP 0x02 /* resolved RX flow control cap */
456 #define VGE_CHIPCFG0_PACPI 0x01 /* pre-ACPI wakeup function */
481 #define VGE_CHIPCFG3_IODISABLE 0x80 /* disable I/O access mode */
501 #define VGE_DMACFG1_PERR_DIS 0x10 /* disable parity error checking */
502 #define VGE_DMACFG1_XMRL 0x20 /* disable memory read line support */
537 #define VGE_TXCFG_NONBLK 0x02 /* priority TX/non-blocking mode */
538 #define VGE_TXCFG_NONBLK_THR 0x0C /* non-blocking threshold */
546 /* MIB control/status register */
590 #define VGE_MIB_CNT (VGE_MIB_TX_LATECOLLS - VGE_MIB_RX_FRAMES + 1)
602 /* WOL pattern control */
613 /* WOL event control */
630 /* EEPROM control/status register */
645 #define VGE_EECMD_EWDIS 0x08 /* EEPROM write disable */
648 /* Chip operation and diagnostic control register */
653 #define VGE_DIAGCTL_LPSEL_DIS 0x08 /* disable LPSEL field */
665 * Each TX DMA descriptor has a control and status word, and 7
712 #define VGE_TDCTL_NOCRC 0x00010000 /* disable CRC generation */